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usbdrvasm15.inc 17KB

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  1. /* Name: usbdrvasm15.inc
  2. * Project: AVR USB driver
  3. * Author: contributed by V. Bosch
  4. * Creation Date: 2007-08-06
  5. * Tabsize: 4
  6. * Copyright: (c) 2007 by OBJECTIVE DEVELOPMENT Software GmbH
  7. * License: GNU GPL v2 (see License.txt) or proprietary (CommercialLicense.txt)
  8. * Revision: $Id$
  9. */
  10. /* Do not link this file! Link usbdrvasm.S instead, which includes the
  11. * appropriate implementation!
  12. */
  13. /*
  14. General Description:
  15. This file is the 15 MHz version of the asssembler part of the USB driver. It
  16. requires a 15 MHz crystal (not a ceramic resonator and not a calibrated RC
  17. oscillator).
  18. See usbdrv.h for a description of the entire driver.
  19. Since almost all of this code is timing critical, don't change unless you
  20. really know what you are doing! Many parts require not only a maximum number
  21. of CPU cycles, but even an exact number of cycles!
  22. */
  23. ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
  24. ;nominal frequency: 15 MHz -> 10.0 cycles per bit, 80.0 cycles per byte
  25. ; Numbers in brackets are clocks counted from center of last sync bit
  26. ; when instruction starts
  27. ;----------------------------------------------------------------------------
  28. ; order of registers pushed:
  29. ; YL, SREG [sofError] YH, shift, x1, x2, x3, bitcnt, cnt, x4
  30. ;----------------------------------------------------------------------------
  31. USB_INTR_VECTOR:
  32. push YL ;2 push only what is necessary to sync with edge ASAP
  33. in YL, SREG ;1
  34. push YL ;2
  35. ;----------------------------------------------------------------------------
  36. ; Synchronize with sync pattern:
  37. ;
  38. ; sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
  39. ; sync up with J to K edge during sync pattern -- use fastest possible loops
  40. ; first part has no timeout because it waits for IDLE or SE1 (== disconnected)
  41. ;-------------------------------------------------------------------------------
  42. waitForJ: ;-
  43. sbis USBIN, USBMINUS ;1 <-- sample: wait for D- == 1
  44. rjmp waitForJ ;2
  45. ;-------------------------------------------------------------------------------
  46. ; The following code results in a sampling window of < 1/4 bit
  47. ; which meets the spec.
  48. ;-------------------------------------------------------------------------------
  49. waitForK: ;-
  50. sbis USBIN, USBMINUS ;1 [00] <-- sample
  51. rjmp foundK ;2 [01]
  52. sbis USBIN, USBMINUS ; <-- sample
  53. rjmp foundK
  54. sbis USBIN, USBMINUS ; <-- sample
  55. rjmp foundK
  56. sbis USBIN, USBMINUS ; <-- sample
  57. rjmp foundK
  58. sbis USBIN, USBMINUS ; <-- sample
  59. rjmp foundK
  60. sbis USBIN, USBMINUS ; <-- sample
  61. rjmp foundK
  62. #if USB_COUNT_SOF
  63. lds YL, usbSofCount
  64. inc YL
  65. sts usbSofCount, YL
  66. #endif /* USB_COUNT_SOF */
  67. rjmp sofError
  68. ;------------------------------------------------------------------------------
  69. ; {3, 5} after falling D- edge, average delay: 4 cycles [we want 5 for
  70. ; center sampling]
  71. ; we have 1 bit time for setup purposes, then sample again.
  72. ; Numbers in brackets are cycles from center of first sync (double K)
  73. ; bit after the instruction
  74. ;------------------------------------------------------------------------------
  75. foundK: ;- [02]
  76. lds YL, usbInputBufOffset;2 [03+04] tx loop
  77. push YH ;2 [05+06]
  78. clr YH ;1 [07]
  79. subi YL, lo8(-(usbRxBuf)) ;1 [08] [rx loop init]
  80. sbci YH, hi8(-(usbRxBuf)) ;1 [09] [rx loop init]
  81. push shift ;2 [10+11]
  82. ser shift ;1 [12]
  83. sbis USBIN, USBMINUS ;1 [-1] [13] <--sample:we want two bits K (sample 1 cycle too early)
  84. rjmp haveTwoBitsK ;2 [00] [14]
  85. pop shift ;2 [15+16] undo the push from before
  86. pop YH ;2 [17+18] undo the push from before
  87. rjmp waitForK ;2 [19+20] this was not the end of sync, retry
  88. ; The entire loop from waitForK until rjmp waitForK above must not exceed two
  89. ; bit times (= 20 cycles).
  90. ;----------------------------------------------------------------------------
  91. ; push more registers and initialize values while we sample the first bits:
  92. ;----------------------------------------------------------------------------
  93. haveTwoBitsK: ;- [01]
  94. push x1 ;2 [02+03]
  95. push x2 ;2 [04+05]
  96. push x3 ;2 [06+07]
  97. push bitcnt ;2 [08+09]
  98. in x1, USBIN ;1 [00] [10] <-- sample bit 0
  99. bst x1, USBMINUS ;1 [01]
  100. bld shift, 0 ;1 [02]
  101. push cnt ;2 [03+04]
  102. ldi cnt, USB_BUFSIZE ;1 [05]
  103. push x4 ;2 [06+07] tx loop
  104. rjmp rxLoop ;2 [08]
  105. ;----------------------------------------------------------------------------
  106. ; Receiver loop (numbers in brackets are cycles within byte after instr)
  107. ;----------------------------------------------------------------------------
  108. unstuff0: ;- [07] (branch taken)
  109. andi x3, ~0x01 ;1 [08]
  110. mov x1, x2 ;1 [09] x2 contains last sampled (stuffed) bit
  111. in x2, USBIN ;1 [00] [10] <-- sample bit 1 again
  112. andi x2, USBMASK ;1 [01]
  113. breq se0Hop ;1 [02] SE0 check for bit 1
  114. ori shift, 0x01 ;1 [03] 0b00000001
  115. nop ;1 [04]
  116. rjmp didUnstuff0 ;2 [05]
  117. ;-----------------------------------------------------
  118. unstuff1: ;- [05] (branch taken)
  119. mov x2, x1 ;1 [06] x1 contains last sampled (stuffed) bit
  120. andi x3, ~0x02 ;1 [07]
  121. ori shift, 0x02 ;1 [08] 0b00000010
  122. nop ;1 [09]
  123. in x1, USBIN ;1 [00] [10] <-- sample bit 2 again
  124. andi x1, USBMASK ;1 [01]
  125. breq se0Hop ;1 [02] SE0 check for bit 2
  126. rjmp didUnstuff1 ;2 [03]
  127. ;-----------------------------------------------------
  128. unstuff2: ;- [05] (branch taken)
  129. andi x3, ~0x04 ;1 [06]
  130. ori shift, 0x04 ;1 [07] 0b00000100
  131. mov x1, x2 ;1 [08] x2 contains last sampled (stuffed) bit
  132. nop ;1 [09]
  133. in x2, USBIN ;1 [00] [10] <-- sample bit 3
  134. andi x2, USBMASK ;1 [01]
  135. breq se0Hop ;1 [02] SE0 check for bit 3
  136. rjmp didUnstuff2 ;2 [03]
  137. ;-----------------------------------------------------
  138. unstuff3: ;- [00] [10] (branch taken)
  139. in x2, USBIN ;1 [01] [11] <-- sample stuffed bit 3 one cycle too late
  140. andi x2, USBMASK ;1 [02]
  141. breq se0Hop ;1 [03] SE0 check for stuffed bit 3
  142. andi x3, ~0x08 ;1 [04]
  143. ori shift, 0x08 ;1 [05] 0b00001000
  144. rjmp didUnstuff3 ;2 [06]
  145. ;----------------------------------------------------------------------------
  146. ; extra jobs done during bit interval:
  147. ;
  148. ; bit 0: store, clear [SE0 is unreliable here due to bit dribbling in hubs],
  149. ; overflow check, jump to the head of rxLoop
  150. ; bit 1: SE0 check
  151. ; bit 2: SE0 check, recovery from delay [bit 0 tasks took too long]
  152. ; bit 3: SE0 check, recovery from delay [bit 0 tasks took too long]
  153. ; bit 4: SE0 check, none
  154. ; bit 5: SE0 check, none
  155. ; bit 6: SE0 check, none
  156. ; bit 7: SE0 check, reconstruct: x3 is 0 at bit locations we changed, 1 at others
  157. ;----------------------------------------------------------------------------
  158. rxLoop: ;- [09]
  159. in x2, USBIN ;1 [00] [10] <-- sample bit 1 (or possibly bit 0 stuffed)
  160. andi x2, USBMASK ;1 [01]
  161. brne SkipSe0Hop ;1 [02]
  162. se0Hop: ;- [02]
  163. rjmp se0 ;2 [03] SE0 check for bit 1
  164. SkipSe0Hop: ;- [03]
  165. ser x3 ;1 [04]
  166. andi shift, 0xf9 ;1 [05] 0b11111001
  167. breq unstuff0 ;1 [06]
  168. didUnstuff0: ;- [06]
  169. eor x1, x2 ;1 [07]
  170. bst x1, USBMINUS ;1 [08]
  171. bld shift, 1 ;1 [09]
  172. in x1, USBIN ;1 [00] [10] <-- sample bit 2 (or possibly bit 1 stuffed)
  173. andi x1, USBMASK ;1 [01]
  174. breq se0Hop ;1 [02] SE0 check for bit 2
  175. andi shift, 0xf3 ;1 [03] 0b11110011
  176. breq unstuff1 ;1 [04] do remaining work for bit 1
  177. didUnstuff1: ;- [04]
  178. eor x2, x1 ;1 [05]
  179. bst x2, USBMINUS ;1 [06]
  180. bld shift, 2 ;1 [07]
  181. nop2 ;2 [08+09]
  182. in x2, USBIN ;1 [00] [10] <-- sample bit 3 (or possibly bit 2 stuffed)
  183. andi x2, USBMASK ;1 [01]
  184. breq se0Hop ;1 [02] SE0 check for bit 3
  185. andi shift, 0xe7 ;1 [03] 0b11100111
  186. breq unstuff2 ;1 [04]
  187. didUnstuff2: ;- [04]
  188. eor x1, x2 ;1 [05]
  189. bst x1, USBMINUS ;1 [06]
  190. bld shift, 3 ;1 [07]
  191. didUnstuff3: ;- [07]
  192. andi shift, 0xcf ;1 [08] 0b11001111
  193. breq unstuff3 ;1 [09]
  194. in x1, USBIN ;1 [00] [10] <-- sample bit 4
  195. andi x1, USBMASK ;1 [01]
  196. breq se0Hop ;1 [02] SE0 check for bit 4
  197. eor x2, x1 ;1 [03]
  198. bst x2, USBMINUS ;1 [04]
  199. bld shift, 4 ;1 [05]
  200. didUnstuff4: ;- [05]
  201. andi shift, 0x9f ;1 [06] 0b10011111
  202. breq unstuff4 ;1 [07]
  203. nop2 ;2 [08+09]
  204. in x2, USBIN ;1 [00] [10] <-- sample bit 5
  205. andi x2, USBMASK ;1 [01]
  206. breq se0 ;1 [02] SE0 check for bit 5
  207. eor x1, x2 ;1 [03]
  208. bst x1, USBMINUS ;1 [04]
  209. bld shift, 5 ;1 [05]
  210. didUnstuff5: ;- [05]
  211. andi shift, 0x3f ;1 [06] 0b00111111
  212. breq unstuff5 ;1 [07]
  213. nop2 ;2 [08+09]
  214. in x1, USBIN ;1 [00] [10] <-- sample bit 6
  215. andi x1, USBMASK ;1 [01]
  216. breq se0 ;1 [02] SE0 check for bit 6
  217. eor x2, x1 ;1 [03]
  218. bst x2, USBMINUS ;1 [04]
  219. bld shift, 6 ;1 [05]
  220. didUnstuff6: ;- [05]
  221. cpi shift, 0x02 ;1 [06] 0b00000010
  222. brlo unstuff6 ;1 [07]
  223. nop2 ;2 [08+09]
  224. in x2, USBIN ;1 [00] [10] <-- sample bit 7
  225. andi x2, USBMASK ;1 [01]
  226. breq se0 ;1 [02] SE0 check for bit 7
  227. eor x1, x2 ;1 [03]
  228. bst x1, USBMINUS ;1 [04]
  229. bld shift, 7 ;1 [05]
  230. didUnstuff7: ;- [05]
  231. cpi shift, 0x04 ;1 [06] 0b00000100
  232. brlo unstuff7 ;1 [07]
  233. eor x3, shift ;1 [08] reconstruct: x3 is 0 at bit locations we changed, 1 at others
  234. nop ;1 [09]
  235. in x1, USBIN ;1 [00] [10] <-- sample bit 0
  236. st y+, x3 ;2 [01+02] store data
  237. eor x2, x1 ;1 [03]
  238. bst x2, USBMINUS ;1 [04]
  239. bld shift, 0 ;1 [05]
  240. subi cnt, 1 ;1 [06]
  241. brcs overflow ;1 [07]
  242. rjmp rxLoop ;2 [08]
  243. ;-----------------------------------------------------
  244. unstuff4: ;- [08]
  245. andi x3, ~0x10 ;1 [09]
  246. in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 4
  247. andi x1, USBMASK ;1 [01]
  248. breq se0 ;1 [02] SE0 check for stuffed bit 4
  249. ori shift, 0x10 ;1 [03]
  250. rjmp didUnstuff4 ;2 [04]
  251. ;-----------------------------------------------------
  252. unstuff5: ;- [08]
  253. ori shift, 0x20 ;1 [09]
  254. in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 5
  255. andi x2, USBMASK ;1 [01]
  256. breq se0 ;1 [02] SE0 check for stuffed bit 5
  257. andi x3, ~0x20 ;1 [03]
  258. rjmp didUnstuff5 ;2 [04]
  259. ;-----------------------------------------------------
  260. unstuff6: ;- [08]
  261. andi x3, ~0x40 ;1 [09]
  262. in x1, USBIN ;1 [00] [10] <-- sample stuffed bit 6
  263. andi x1, USBMASK ;1 [01]
  264. breq se0 ;1 [02] SE0 check for stuffed bit 6
  265. ori shift, 0x40 ;1 [03]
  266. rjmp didUnstuff6 ;2 [04]
  267. ;-----------------------------------------------------
  268. unstuff7: ;- [08]
  269. andi x3, ~0x80 ;1 [09]
  270. in x2, USBIN ;1 [00] [10] <-- sample stuffed bit 7
  271. andi x2, USBMASK ;1 [01]
  272. breq se0 ;1 [02] SE0 check for stuffed bit 7
  273. ori shift, 0x80 ;1 [03]
  274. rjmp didUnstuff7 ;2 [04]
  275. macro POP_STANDARD ; 16 cycles
  276. pop x4
  277. pop cnt
  278. pop bitcnt
  279. pop x3
  280. pop x2
  281. pop x1
  282. pop shift
  283. pop YH
  284. endm
  285. macro POP_RETI ; 5 cycles
  286. pop YL
  287. out SREG, YL
  288. pop YL
  289. endm
  290. #include "asmcommon.inc"
  291. ;---------------------------------------------------------------------------
  292. ; USB spec says:
  293. ; idle = J
  294. ; J = (D+ = 0), (D- = 1)
  295. ; K = (D+ = 1), (D- = 0)
  296. ; Spec allows 7.5 bit times from EOP to SOP for replies
  297. ;---------------------------------------------------------------------------
  298. bitstuffN: ;- [04]
  299. eor x1, x4 ;1 [05]
  300. clr x2 ;1 [06]
  301. nop ;1 [07]
  302. rjmp didStuffN ;1 [08]
  303. ;---------------------------------------------------------------------------
  304. bitstuff6: ;- [04]
  305. eor x1, x4 ;1 [05]
  306. clr x2 ;1 [06]
  307. rjmp didStuff6 ;1 [07]
  308. ;---------------------------------------------------------------------------
  309. bitstuff7: ;- [02]
  310. eor x1, x4 ;1 [03]
  311. clr x2 ;1 [06]
  312. nop ;1 [05]
  313. rjmp didStuff7 ;1 [06]
  314. ;---------------------------------------------------------------------------
  315. sendNakAndReti: ;- [-19]
  316. ldi x3, USBPID_NAK ;1 [-18]
  317. rjmp sendX3AndReti ;1 [-17]
  318. ;---------------------------------------------------------------------------
  319. sendAckAndReti: ;- [-17]
  320. ldi cnt, USBPID_ACK ;1 [-16]
  321. sendCntAndReti: ;- [-16]
  322. mov x3, cnt ;1 [-15]
  323. sendX3AndReti: ;- [-15]
  324. ldi YL, 20 ;1 [-14] x3==r20 address is 20
  325. ldi YH, 0 ;1 [-13]
  326. ldi cnt, 2 ;1 [-12]
  327. ; rjmp usbSendAndReti fallthrough
  328. ;---------------------------------------------------------------------------
  329. ;usbSend:
  330. ;pointer to data in 'Y'
  331. ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
  332. ;uses: x1...x4, btcnt, shift, cnt, Y
  333. ;Numbers in brackets are time since first bit of sync pattern is sent
  334. ;We need not to match the transfer rate exactly because the spec demands
  335. ;only 1.5% precision anyway.
  336. usbSendAndReti: ;- [-13] 13 cycles until SOP
  337. in x2, USBDDR ;1 [-12]
  338. ori x2, USBMASK ;1 [-11]
  339. sbi USBOUT, USBMINUS ;2 [-09-10] prepare idle state; D+ and D- must have been 0 (no pullups)
  340. in x1, USBOUT ;1 [-08] port mirror for tx loop
  341. out USBDDR, x2 ;1 [-07] <- acquire bus
  342. ; need not init x2 (bitstuff history) because sync starts with 0
  343. ldi x4, USBMASK ;1 [-06] exor mask
  344. ldi shift, 0x80 ;1 [-05] sync byte is first byte sent
  345. ldi bitcnt, 6 ;1 [-04]
  346. txBitLoop: ;- [-04] [06]
  347. sbrs shift, 0 ;1 [-03] [07]
  348. eor x1, x4 ;1 [-02] [08]
  349. ror shift ;1 [-01] [09]
  350. didStuffN: ;- [09]
  351. out USBOUT, x1 ;1 [00] [10] <-- out N
  352. ror x2 ;1 [01]
  353. cpi x2, 0xfc ;1 [02]
  354. brcc bitstuffN ;1 [03]
  355. dec bitcnt ;1 [04]
  356. brne txBitLoop ;1 [05]
  357. sbrs shift, 0 ;1 [06]
  358. eor x1, x4 ;1 [07]
  359. ror shift ;1 [08]
  360. didStuff6: ;- [08]
  361. nop ;1 [09]
  362. out USBOUT, x1 ;1 [00] [10] <-- out 6
  363. ror x2 ;1 [01]
  364. cpi x2, 0xfc ;1 [02]
  365. brcc bitstuff6 ;1 [03]
  366. sbrs shift, 0 ;1 [04]
  367. eor x1, x4 ;1 [05]
  368. ror shift ;1 [06]
  369. ror x2 ;1 [07]
  370. didStuff7: ;- [07]
  371. ldi bitcnt, 6 ;1 [08]
  372. cpi x2, 0xfc ;1 [09]
  373. out USBOUT, x1 ;1 [00] [10] <-- out 7
  374. brcc bitstuff7 ;1 [01]
  375. ld shift, y+ ;2 [02+03]
  376. dec cnt ;1 [04]
  377. brne txBitLoop ;1 [05]
  378. makeSE0:
  379. cbr x1, USBMASK ;1 [06] prepare SE0 [spec says EOP may be 19 to 23 cycles]
  380. lds x2, usbNewDeviceAddr;2 [07+08]
  381. lsl x2 ;1 [09] we compare with left shifted address
  382. ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
  383. ;set address only after data packet was sent, not after handshake
  384. out USBOUT, x1 ;1 [00] [10] <-- out SE0-- from now 2 bits==20 cycl. until bus idle
  385. subi YL, 20 + 2 ;1 [01] Only assign address on data packets, not ACK/NAK in x3
  386. sbci YH, 0 ;1 [02]
  387. breq skipAddrAssign ;1 [03]
  388. sts usbDeviceAddr, x2 ;2 [04+05] if not skipped: SE0 is one cycle longer
  389. ;----------------------------------------------------------------------------
  390. ;end of usbDeviceAddress transfer
  391. skipAddrAssign: ;- [03/04]
  392. ldi x2, 1<<USB_INTR_PENDING_BIT ;1 [05] int0 occurred during TX -- clear pending flag
  393. USB_STORE_PENDING(x2) ;1 [06]
  394. ori x1, USBIDLE ;1 [07]
  395. in x2, USBDDR ;1 [08]
  396. cbr x2, USBMASK ;1 [09] set both pins to input
  397. mov x3, x1 ;1 [10]
  398. cbr x3, USBMASK ;1 [11] configure no pullup on both pins
  399. ldi x4, 3 ;1 [12]
  400. se0Delay: ;- [12] [15]
  401. dec x4 ;1 [13] [16]
  402. brne se0Delay ;1 [14] [17]
  403. nop2 ;2 [18+19]
  404. out USBOUT, x1 ;1 [20] <--out J (idle) -- end of SE0 (EOP sig.)
  405. out USBDDR, x2 ;1 [21] <--release bus now
  406. out USBOUT, x3 ;1 [22] <--ensure no pull-up resistors are active
  407. rjmp doReturn ;1 [23]
  408. ;---------------------------------------------------------------------------