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USI_TWI_Master.h 6.1KB

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  1. /*****************************************************************************
  2. *
  3. * Atmel Corporation
  4. *
  5. * File : USI_TWI_Master.h
  6. * Date : $Date: 2016-7-15 $
  7. * Updated by : $Author: Atmel $
  8. *
  9. * Support mail : avr@atmel.com
  10. *
  11. * Supported devices : All device with USI module can be used.
  12. * The example is written for the ATmega169, ATtiny26 and ATtiny2313
  13. *
  14. * AppNote : AVR310 - Using the USI module as a TWI Master
  15. *
  16. * Description : This is an implementation of an TWI master using
  17. * the USI module as basis. The implementation assumes the AVR to
  18. * be the only TWI master in the system and can therefore not be
  19. * used in a multi-master system.
  20. * Usage : Initialize the USI module by calling the USI_TWI_Master_Initialise()
  21. * function. Hence messages/data are transceived on the bus using
  22. * the USI_TWI_Start_Transceiver_With_Data() function. If the transceiver
  23. * returns with a fail, then use USI_TWI_Get_Status_Info to evaluate the
  24. * couse of the failure.
  25. *
  26. ****************************************************************************/
  27. #if __GNUC__
  28. #ifndef F_CPU
  29. #define F_CPU 16500000
  30. #endif
  31. #include <avr/io.h>
  32. #include <util/delay.h>
  33. #endif
  34. //********** Defines **********//
  35. // Defines controlling timing limits
  36. #define TWI_FAST_MODE
  37. #define SYS_CLK (F_CPU / 1000.0) // [kHz]
  38. #ifdef TWI_FAST_MODE // TWI FAST mode timing limits. SCL = 100-400kHz
  39. #define T2_TWI ((SYS_CLK * 1300) / 1000000) + 1 // >1,3us
  40. #define T4_TWI ((SYS_CLK * 600) / 1000000) + 1 // >0,6us
  41. #else // TWI STANDARD mode timing limits. SCL <= 100kHz
  42. #define T2_TWI ((SYS_CLK * 4700) / 1000000) + 1 // >4,7us
  43. #define T4_TWI ((SYS_CLK * 4000) / 1000000) + 1 // >4,0us
  44. #endif
  45. // Defines controling code generating
  46. //#define PARAM_VERIFICATION
  47. //#define NOISE_TESTING
  48. //#define SIGNAL_VERIFY
  49. // USI_TWI messages and flags and bit masks
  50. //#define SUCCESS 7
  51. //#define MSG 0
  52. /****************************************************************************
  53. Bit and byte definitions
  54. ****************************************************************************/
  55. #define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte".
  56. #define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte.
  57. #define TWI_NACK_BIT 0 // Bit position for (N)ACK bit.
  58. #define USI_TWI_NO_DATA 0x00 // Transmission buffer is empty
  59. #define USI_TWI_DATA_OUT_OF_BOUND 0x01 // Transmission buffer is outside SRAM space
  60. #define USI_TWI_UE_START_CON 0x02 // Unexpected Start Condition
  61. #define USI_TWI_UE_STOP_CON 0x03 // Unexpected Stop Condition
  62. #define USI_TWI_UE_DATA_COL 0x04 // Unexpected Data Collision (arbitration)
  63. #define USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data
  64. #define USI_TWI_NO_ACK_ON_ADDRESS 0x06 // The slave did not acknowledge the address
  65. #define USI_TWI_MISSING_START_CON 0x07 // Generated Start Condition not detected on bus
  66. #define USI_TWI_MISSING_STOP_CON 0x08 // Generated Stop Condition not detected on bus
  67. // Device dependant defines
  68. #if __GNUC__
  69. #if defined(__AVR_AT90Mega169__) || defined(__AVR_ATmega169PA__) || defined(__AVR_AT90Mega165__) \
  70. || defined(__AVR_ATmega165__) || defined(__AVR_ATmega325__) || defined(__AVR_ATmega3250__) \
  71. || defined(__AVR_ATmega645__) || defined(__AVR_ATmega6450__) || defined(__AVR_ATmega329__) \
  72. || defined(__AVR_ATmega3290__) || defined(__AVR_ATmega649__) || defined(__AVR_ATmega6490__)
  73. #define DDR_USI DDRE
  74. #define PORT_USI PORTE
  75. #define PIN_USI PINE
  76. #define PORT_USI_SDA PORTE5
  77. #define PORT_USI_SCL PORTE4
  78. #define PIN_USI_SDA PINE5
  79. #define PIN_USI_SCL PINE4
  80. #endif
  81. #if defined(__AVR_ATtiny25__) || defined(__AVR_ATtiny45__) || defined(__AVR_ATtiny85__) || defined(__AVR_AT90Tiny26__) \
  82. || defined(__AVR_ATtiny26__)
  83. #define DDR_USI DDRB
  84. #define PORT_USI PORTB
  85. #define PIN_USI PINB
  86. #define PORT_USI_SDA PORTB0
  87. #define PORT_USI_SCL PORTB2
  88. #define PIN_USI_SDA PINB0
  89. #define PIN_USI_SCL PINB2
  90. #endif
  91. #if defined(__AVR_AT90Tiny2313__) || defined(__AVR_ATtiny2313__)
  92. #define DDR_USI DDRB
  93. #define PORT_USI PORTB
  94. #define PIN_USI PINB
  95. #define PORT_USI_SDA PORTB5
  96. #define PORT_USI_SCL PORTB7
  97. #define PIN_USI_SDA PINB5
  98. #define PIN_USI_SCL PINB7
  99. #endif
  100. #else //__GNUC__
  101. #if defined(__AT90Mega169__) || defined(__ATmega169__) || defined(__AT90Mega165__) || defined(__ATmega165__) \
  102. || defined(__ATmega325__) || defined(__ATmega3250__) || defined(__ATmega645__) || defined(__ATmega6450__) \
  103. || defined(__ATmega329__) || defined(__ATmega3290__) || defined(__ATmega649__) || defined(__ATmega6490__)
  104. #define DDR_USI DDRE
  105. #define PORT_USI PORTE
  106. #define PIN_USI PINE
  107. #define PORT_USI_SDA PORTE5
  108. #define PORT_USI_SCL PORTE4
  109. #define PIN_USI_SDA PINE5
  110. #define PIN_USI_SCL PINE4
  111. #endif
  112. #if defined(__ATtiny25__) || defined(__ATtiny45__) || defined(__ATtiny85__) || defined(__AT90Tiny26__) \
  113. || defined(__ATtiny26__)
  114. #define DDR_USI DDRB
  115. #define PORT_USI PORTB
  116. #define PIN_USI PINB
  117. #define PORT_USI_SDA PORTB0
  118. #define PORT_USI_SCL PORTB2
  119. #define PIN_USI_SDA PINB0
  120. #define PIN_USI_SCL PINB2
  121. #endif
  122. #if defined(__AT90Tiny2313__) || defined(__ATtiny2313__)
  123. #define DDR_USI DDRB
  124. #define PORT_USI PORTB
  125. #define PIN_USI PINB
  126. #define PORT_USI_SDA PORTB5
  127. #define PORT_USI_SCL PORTB7
  128. #define PIN_USI_SDA PINB5
  129. #define PIN_USI_SCL PINB7
  130. #endif
  131. #endif //__GNUC__
  132. // General defines
  133. #define TRUE 1
  134. #define FALSE 0
  135. #if __GNUC__
  136. #define DELAY_T2TWI (_delay_us(T2_TWI / 4))
  137. #define DELAY_T4TWI (_delay_us(T4_TWI / 4))
  138. #else
  139. #define DELAY_T2TWI (__delay_cycles(T2_TWI))
  140. #define DELAY_T4TWI (__delay_cycles(T4_TWI))
  141. #endif
  142. //********** Prototypes **********//
  143. void USI_TWI_Master_Initialise(void);
  144. #ifndef __GNUC__
  145. __x // AVR compiler
  146. #endif
  147. unsigned char
  148. USI_TWI_Start_Transceiver_With_Data(unsigned char *, unsigned char);
  149. unsigned char USI_TWI_Get_State_Info(void);