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drumkit.kicad_pro 11KB

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  3. "3dviewports": [],
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  7. "copper_line_width": 0.19999999999999998,
  8. "copper_text_italic": false,
  9. "copper_text_size_h": 1.5,
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  13. "courtyard_line_width": 0.049999999999999996,
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  15. "dimension_units": 3,
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  66. "copper_edge_clearance": "error",
  67. "copper_sliver": "warning",
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  70. "diff_pair_uncoupled_length_too_long": "error",
  71. "drill_out_of_range": "error",
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  74. "footprint": "error",
  75. "footprint_type_mismatch": "ignore",
  76. "hole_clearance": "error",
  77. "hole_near_hole": "error",
  78. "invalid_outline": "error",
  79. "isolated_copper": "warning",
  80. "item_on_disabled_layer": "error",
  81. "items_not_allowed": "error",
  82. "length_out_of_range": "error",
  83. "lib_footprint_issues": "warning",
  84. "lib_footprint_mismatch": "warning",
  85. "malformed_courtyard": "error",
  86. "microvia_drill_out_of_range": "error",
  87. "missing_courtyard": "ignore",
  88. "missing_footprint": "warning",
  89. "net_conflict": "warning",
  90. "npth_inside_courtyard": "ignore",
  91. "padstack": "warning",
  92. "pth_inside_courtyard": "ignore",
  93. "shorting_items": "error",
  94. "silk_edge_clearance": "warning",
  95. "silk_over_copper": "warning",
  96. "silk_overlap": "warning",
  97. "skew_out_of_range": "error",
  98. "solder_mask_bridge": "error",
  99. "starved_thermal": "error",
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  103. "too_many_vias": "error",
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  105. "track_width": "error",
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  176. 1.0,
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  185. "zones_allow_external_fillets": false
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  190. "boards": [],
  191. "cvpcb": {
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  194. "erc": {
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  369. "rule_severities": {
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  371. "bus_entry_needed": "error",
  372. "bus_to_bus_conflict": "error",
  373. "bus_to_net_conflict": "error",
  374. "conflicting_netclasses": "error",
  375. "different_unit_footprint": "error",
  376. "different_unit_net": "error",
  377. "duplicate_reference": "error",
  378. "duplicate_sheet_names": "error",
  379. "endpoint_off_grid": "warning",
  380. "extra_units": "error",
  381. "global_label_dangling": "warning",
  382. "hier_label_mismatch": "error",
  383. "label_dangling": "error",
  384. "lib_symbol_issues": "warning",
  385. "missing_bidi_pin": "warning",
  386. "missing_input_pin": "warning",
  387. "missing_power_pin": "error",
  388. "missing_unit": "warning",
  389. "multiple_net_names": "warning",
  390. "net_not_bus_member": "warning",
  391. "no_connect_connected": "warning",
  392. "no_connect_dangling": "warning",
  393. "pin_not_connected": "error",
  394. "pin_not_driven": "error",
  395. "pin_to_pin": "warning",
  396. "power_pin_not_driven": "error",
  397. "similar_labels": "warning",
  398. "simulation_model_issue": "error",
  399. "unannotated": "error",
  400. "unit_value_mismatch": "error",
  401. "unresolved_variable": "error",
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  403. }
  404. },
  405. "libraries": {
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  409. "meta": {
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  411. "version": 1
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  413. "net_settings": {
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  417. "clearance": 0.2,
  418. "diff_pair_gap": 0.25,
  419. "diff_pair_via_gap": 0.25,
  420. "diff_pair_width": 0.2,
  421. "line_style": 0,
  422. "microvia_diameter": 0.3,
  423. "microvia_drill": 0.1,
  424. "name": "Default",
  425. "pcb_color": "rgba(0, 0, 0, 0.000)",
  426. "schematic_color": "rgba(0, 0, 0, 0.000)",
  427. "track_width": 0.25,
  428. "via_diameter": 0.8,
  429. "via_drill": 0.4,
  430. "wire_width": 6
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  432. ],
  433. "meta": {
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  436. "net_colors": null,
  437. "netclass_assignments": null,
  438. "netclass_patterns": []
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  440. "pcbnew": {
  441. "last_paths": {
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  443. "idf": "",
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  445. "specctra_dsn": "",
  446. "step": "",
  447. "vrml": ""
  448. },
  449. "page_layout_descr_file": ""
  450. },
  451. "schematic": {
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  453. "drawing": {
  454. "dashed_lines_dash_length_ratio": 12.0,
  455. "dashed_lines_gap_length_ratio": 3.0,
  456. "default_line_thickness": 6.0,
  457. "default_text_size": 50.0,
  458. "field_names": [],
  459. "intersheets_ref_own_page": false,
  460. "intersheets_ref_prefix": "",
  461. "intersheets_ref_short": false,
  462. "intersheets_ref_show": false,
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  464. "junction_size_choice": 3,
  465. "label_size_ratio": 0.375,
  466. "pin_symbol_size": 25.0,
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  468. },
  469. "legacy_lib_dir": "",
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  474. "net_format_name": "",
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  476. "plot_directory": "",
  477. "spice_current_sheet_as_root": false,
  478. "spice_external_command": "spice \"%I\"",
  479. "spice_model_current_sheet_as_root": true,
  480. "spice_save_all_currents": false,
  481. "spice_save_all_voltages": false,
  482. "subpart_first_id": 65,
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  485. "sheets": [
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