|
@@ -0,0 +1,741 @@
|
|
1
|
+/******************************************************************************
|
|
2
|
+ * The MIT License
|
|
3
|
+ *
|
|
4
|
+ * Copyright (c) 2010 Perry Hung.
|
|
5
|
+ *
|
|
6
|
+ * Permission is hereby granted, free of charge, to any person
|
|
7
|
+ * obtaining a copy of this software and associated documentation
|
|
8
|
+ * files (the "Software"), to deal in the Software without
|
|
9
|
+ * restriction, including without limitation the rights to use, copy,
|
|
10
|
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
|
|
11
|
+ * of the Software, and to permit persons to whom the Software is
|
|
12
|
+ * furnished to do so, subject to the following conditions:
|
|
13
|
+ *
|
|
14
|
+ * The above copyright notice and this permission notice shall be
|
|
15
|
+ * included in all copies or substantial portions of the Software.
|
|
16
|
+ *
|
|
17
|
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
|
18
|
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
|
19
|
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
|
20
|
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
|
21
|
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
|
22
|
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
|
23
|
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
|
24
|
+ * SOFTWARE.
|
|
25
|
+ *****************************************************************************/
|
|
26
|
+
|
|
27
|
+/**
|
|
28
|
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
|
|
29
|
+ * @brief Wirish SPI implementation.
|
|
30
|
+ */
|
|
31
|
+
|
|
32
|
+#ifdef __STM32F1__
|
|
33
|
+
|
|
34
|
+#include "SPI.h"
|
|
35
|
+
|
|
36
|
+#include <libmaple/timer.h>
|
|
37
|
+#include <libmaple/util.h>
|
|
38
|
+#include <libmaple/rcc.h>
|
|
39
|
+
|
|
40
|
+#include <boards.h>
|
|
41
|
+#include <wirish.h>
|
|
42
|
+
|
|
43
|
+/** Time in ms for DMA receive timeout */
|
|
44
|
+#define DMA_TIMEOUT 100
|
|
45
|
+
|
|
46
|
+#if CYCLES_PER_MICROSECOND != 72
|
|
47
|
+ #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
|
|
48
|
+#endif
|
|
49
|
+
|
|
50
|
+struct spi_pins {
|
|
51
|
+ uint8_t nss;
|
|
52
|
+ uint8_t sck;
|
|
53
|
+ uint8_t miso;
|
|
54
|
+ uint8_t mosi;
|
|
55
|
+};
|
|
56
|
+
|
|
57
|
+static const spi_pins* dev_to_spi_pins(spi_dev *dev);
|
|
58
|
+static void configure_gpios(spi_dev *dev, bool as_master);
|
|
59
|
+static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq);
|
|
60
|
+
|
|
61
|
+#if (BOARD_NR_SPI >= 3) && !defined(STM32_HIGH_DENSITY)
|
|
62
|
+ #error "The SPI library is misconfigured: 3 SPI ports only available on high density STM32 devices"
|
|
63
|
+#endif
|
|
64
|
+
|
|
65
|
+static const spi_pins board_spi_pins[] __FLASH__ = {
|
|
66
|
+ #if BOARD_NR_SPI >= 1
|
|
67
|
+ { BOARD_SPI1_NSS_PIN,
|
|
68
|
+ BOARD_SPI1_SCK_PIN,
|
|
69
|
+ BOARD_SPI1_MISO_PIN,
|
|
70
|
+ BOARD_SPI1_MOSI_PIN },
|
|
71
|
+ #endif
|
|
72
|
+ #if BOARD_NR_SPI >= 2
|
|
73
|
+ { BOARD_SPI2_NSS_PIN,
|
|
74
|
+ BOARD_SPI2_SCK_PIN,
|
|
75
|
+ BOARD_SPI2_MISO_PIN,
|
|
76
|
+ BOARD_SPI2_MOSI_PIN },
|
|
77
|
+ #endif
|
|
78
|
+ #if BOARD_NR_SPI >= 3
|
|
79
|
+ { BOARD_SPI3_NSS_PIN,
|
|
80
|
+ BOARD_SPI3_SCK_PIN,
|
|
81
|
+ BOARD_SPI3_MISO_PIN,
|
|
82
|
+ BOARD_SPI3_MOSI_PIN },
|
|
83
|
+ #endif
|
|
84
|
+};
|
|
85
|
+
|
|
86
|
+#if BOARD_NR_SPI >= 1
|
|
87
|
+ static void (*_spi1_this);
|
|
88
|
+#endif
|
|
89
|
+#if BOARD_NR_SPI >= 2
|
|
90
|
+ static void (*_spi2_this);
|
|
91
|
+#endif
|
|
92
|
+#if BOARD_NR_SPI >= 3
|
|
93
|
+ static void (*_spi3_this);
|
|
94
|
+#endif
|
|
95
|
+
|
|
96
|
+/**
|
|
97
|
+ * Constructor
|
|
98
|
+ */
|
|
99
|
+SPIClass::SPIClass(uint32_t spi_num) {
|
|
100
|
+ _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
|
|
101
|
+
|
|
102
|
+ switch (spi_num) {
|
|
103
|
+ #if BOARD_NR_SPI >= 1
|
|
104
|
+ case 1:
|
|
105
|
+ _currentSetting->spi_d = SPI1;
|
|
106
|
+ _spi1_this = (void*)this;
|
|
107
|
+ break;
|
|
108
|
+ #endif
|
|
109
|
+ #if BOARD_NR_SPI >= 2
|
|
110
|
+ case 2:
|
|
111
|
+ _currentSetting->spi_d = SPI2;
|
|
112
|
+ _spi2_this = (void*)this;
|
|
113
|
+ break;
|
|
114
|
+ #endif
|
|
115
|
+ #if BOARD_NR_SPI >= 3
|
|
116
|
+ case 3:
|
|
117
|
+ _currentSetting->spi_d = SPI3;
|
|
118
|
+ _spi3_this = (void*)this;
|
|
119
|
+ break;
|
|
120
|
+ #endif
|
|
121
|
+ default: ASSERT(0);
|
|
122
|
+ }
|
|
123
|
+
|
|
124
|
+ // Init things specific to each SPI device
|
|
125
|
+ // clock divider setup is a bit of hack, and needs to be improved at a later date.
|
|
126
|
+ #if BOARD_NR_SPI >= 1
|
|
127
|
+ _settings[0].spi_d = SPI1;
|
|
128
|
+ _settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
|
|
129
|
+ _settings[0].spiDmaDev = DMA1;
|
|
130
|
+ _settings[0].spiTxDmaChannel = DMA_CH3;
|
|
131
|
+ _settings[0].spiRxDmaChannel = DMA_CH2;
|
|
132
|
+ #endif
|
|
133
|
+ #if BOARD_NR_SPI >= 2
|
|
134
|
+ _settings[1].spi_d = SPI2;
|
|
135
|
+ _settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
|
|
136
|
+ _settings[1].spiDmaDev = DMA1;
|
|
137
|
+ _settings[1].spiTxDmaChannel = DMA_CH5;
|
|
138
|
+ _settings[1].spiRxDmaChannel = DMA_CH4;
|
|
139
|
+ #endif
|
|
140
|
+ #if BOARD_NR_SPI >= 3
|
|
141
|
+ _settings[2].spi_d = SPI3;
|
|
142
|
+ _settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
|
|
143
|
+ _settings[2].spiDmaDev = DMA2;
|
|
144
|
+ _settings[2].spiTxDmaChannel = DMA_CH2;
|
|
145
|
+ _settings[2].spiRxDmaChannel = DMA_CH1;
|
|
146
|
+ #endif
|
|
147
|
+
|
|
148
|
+ // added for DMA callbacks.
|
|
149
|
+ _currentSetting->state = SPI_STATE_IDLE;
|
|
150
|
+}
|
|
151
|
+
|
|
152
|
+/*
|
|
153
|
+ * Set up/tear down
|
|
154
|
+ */
|
|
155
|
+void SPIClass::updateSettings() {
|
|
156
|
+ uint32_t flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
|
|
157
|
+ spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
|
|
158
|
+}
|
|
159
|
+
|
|
160
|
+void SPIClass::begin() {
|
|
161
|
+ spi_init(_currentSetting->spi_d);
|
|
162
|
+ configure_gpios(_currentSetting->spi_d, 1);
|
|
163
|
+ updateSettings();
|
|
164
|
+ // added for DMA callbacks.
|
|
165
|
+ _currentSetting->state = SPI_STATE_READY;
|
|
166
|
+}
|
|
167
|
+
|
|
168
|
+void SPIClass::beginSlave() {
|
|
169
|
+ spi_init(_currentSetting->spi_d);
|
|
170
|
+ configure_gpios(_currentSetting->spi_d, 0);
|
|
171
|
+ uint32_t flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize);
|
|
172
|
+ spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
|
|
173
|
+ // added for DMA callbacks.
|
|
174
|
+ _currentSetting->state = SPI_STATE_READY;
|
|
175
|
+}
|
|
176
|
+
|
|
177
|
+void SPIClass::end() {
|
|
178
|
+ if (!spi_is_enabled(_currentSetting->spi_d))
|
|
179
|
+ return;
|
|
180
|
+
|
|
181
|
+ // Follows RM0008's sequence for disabling a SPI in master/slave
|
|
182
|
+ // full duplex mode.
|
|
183
|
+ while (spi_is_rx_nonempty(_currentSetting->spi_d)) {
|
|
184
|
+ // FIXME [0.1.0] remove this once you have an interrupt based driver
|
|
185
|
+ volatile uint16_t rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
|
|
186
|
+ }
|
|
187
|
+ while (!spi_is_tx_empty(_currentSetting->spi_d)) {};
|
|
188
|
+ while (spi_is_busy(_currentSetting->spi_d)) {};
|
|
189
|
+
|
|
190
|
+ spi_peripheral_disable(_currentSetting->spi_d);
|
|
191
|
+ // added for DMA callbacks.
|
|
192
|
+ // Need to add unsetting the callbacks for the DMA channels.
|
|
193
|
+ _currentSetting->state = SPI_STATE_IDLE;
|
|
194
|
+}
|
|
195
|
+
|
|
196
|
+/* Roger Clark added 3 functions */
|
|
197
|
+void SPIClass::setClockDivider(uint32_t clockDivider) {
|
|
198
|
+ _currentSetting->clockDivider = clockDivider;
|
|
199
|
+ uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
|
|
200
|
+ _currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
|
|
201
|
+}
|
|
202
|
+
|
|
203
|
+void SPIClass::setBitOrder(BitOrder bitOrder) {
|
|
204
|
+ _currentSetting->bitOrder = bitOrder;
|
|
205
|
+ uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
|
|
206
|
+ if (bitOrder == LSBFIRST) cr1 |= SPI_CR1_LSBFIRST;
|
|
207
|
+ _currentSetting->spi_d->regs->CR1 = cr1;
|
|
208
|
+}
|
|
209
|
+
|
|
210
|
+/* Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
|
|
211
|
+* Input parameter should be SPI_CR1_DFF set to 0 or 1 on a 32bit word.
|
|
212
|
+*
|
|
213
|
+*/
|
|
214
|
+void SPIClass::setDataSize(uint32_t datasize) {
|
|
215
|
+ _currentSetting->dataSize = datasize;
|
|
216
|
+ uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
|
|
217
|
+ uint8_t en = spi_is_enabled(_currentSetting->spi_d);
|
|
218
|
+ spi_peripheral_disable(_currentSetting->spi_d);
|
|
219
|
+ _currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
|
|
220
|
+}
|
|
221
|
+
|
|
222
|
+void SPIClass::setDataMode(uint8_t dataMode) {
|
|
223
|
+ /* Notes:
|
|
224
|
+ As far as I can tell, the AVR numbers for dataMode appear to match the numbers required by the STM32
|
|
225
|
+ From the AVR doc http://www.atmel.com/images/doc2585.pdf section 2.4
|
|
226
|
+ SPI Mode CPOL CPHA Shift SCK-edge Capture SCK-edge
|
|
227
|
+ 0 0 0 Falling Rising
|
|
228
|
+ 1 0 1 Rising Falling
|
|
229
|
+ 2 1 0 Rising Falling
|
|
230
|
+ 3 1 1 Falling Rising
|
|
231
|
+
|
|
232
|
+ On the STM32 it appears to be
|
|
233
|
+
|
|
234
|
+ bit 1 - CPOL : Clock polarity
|
|
235
|
+ (This bit should not be changed when communication is ongoing)
|
|
236
|
+ 0 : CLK to 0 when idle
|
|
237
|
+ 1 : CLK to 1 when idle
|
|
238
|
+
|
|
239
|
+ bit 0 - CPHA : Clock phase
|
|
240
|
+ (This bit should not be changed when communication is ongoing)
|
|
241
|
+ 0 : The first clock transition is the first data capture edge
|
|
242
|
+ 1 : The second clock transition is the first data capture edge
|
|
243
|
+
|
|
244
|
+ If someone finds this is not the case or sees a logic error with this let me know ;-)
|
|
245
|
+ */
|
|
246
|
+ _currentSetting->dataMode = dataMode;
|
|
247
|
+ uint32_t cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
|
|
248
|
+ _currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
|
|
249
|
+}
|
|
250
|
+
|
|
251
|
+void SPIClass::beginTransaction(uint8_t pin, SPISettings settings) {
|
|
252
|
+ setBitOrder(settings.bitOrder);
|
|
253
|
+ setDataMode(settings.dataMode);
|
|
254
|
+ setDataSize(settings.dataSize);
|
|
255
|
+ setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
|
|
256
|
+ begin();
|
|
257
|
+}
|
|
258
|
+
|
|
259
|
+void SPIClass::beginTransactionSlave(SPISettings settings) {
|
|
260
|
+ setBitOrder(settings.bitOrder);
|
|
261
|
+ setDataMode(settings.dataMode);
|
|
262
|
+ setDataSize(settings.dataSize);
|
|
263
|
+ beginSlave();
|
|
264
|
+}
|
|
265
|
+
|
|
266
|
+void SPIClass::endTransaction() { }
|
|
267
|
+
|
|
268
|
+
|
|
269
|
+/*
|
|
270
|
+ * I/O
|
|
271
|
+ */
|
|
272
|
+
|
|
273
|
+uint16_t SPIClass::read() {
|
|
274
|
+ while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
|
|
275
|
+ return (uint16)spi_rx_reg(_currentSetting->spi_d);
|
|
276
|
+}
|
|
277
|
+
|
|
278
|
+void SPIClass::read(uint8_t *buf, uint32_t len) {
|
|
279
|
+ if (len == 0) return;
|
|
280
|
+ spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it.
|
|
281
|
+ spi_reg_map * regs = _currentSetting->spi_d->regs;
|
|
282
|
+ // start sequence: write byte 0
|
|
283
|
+ regs->DR = 0x00FF; // write the first byte
|
|
284
|
+ // main loop
|
|
285
|
+ while ( (--len) ) {
|
|
286
|
+ while( !(regs->SR & SPI_SR_TXE) ); // wait for TXE flag
|
|
287
|
+ noInterrupts(); // go atomic level - avoid interrupts to surely get the previously received data
|
|
288
|
+ regs->DR = 0x00FF; // write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
|
|
289
|
+ while ( !(regs->SR & SPI_SR_RXNE) ); // wait till data is available in the DR register
|
|
290
|
+ *buf++ = (uint8)(regs->DR); // read and store the received byte. This clears the RXNE flag.
|
|
291
|
+ interrupts(); // let systick do its job
|
|
292
|
+ }
|
|
293
|
+ // read remaining last byte
|
|
294
|
+ while ( !(regs->SR & SPI_SR_RXNE) ) {} // wait till data is available in the Rx register
|
|
295
|
+ *buf++ = (uint8)(regs->DR); // read and store the received byte
|
|
296
|
+}
|
|
297
|
+
|
|
298
|
+void SPIClass::write(uint16_t data) {
|
|
299
|
+ /* Added for 16bit data Victor Perez. Roger Clark
|
|
300
|
+ * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
|
|
301
|
+ * by taking the Tx code from transfer(byte)
|
|
302
|
+ * This almost doubles the speed of this function.
|
|
303
|
+ */
|
|
304
|
+ spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
|
|
305
|
+ while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
306
|
+ while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
307
|
+}
|
|
308
|
+
|
|
309
|
+void SPIClass::write16(uint16_t data) {
|
|
310
|
+ // Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0)
|
|
311
|
+ spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte
|
|
312
|
+ while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
|
|
313
|
+ spi_tx_reg(_currentSetting->spi_d, data); // write low byte
|
|
314
|
+ while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
|
|
315
|
+ while (spi_is_busy(_currentSetting->spi_d) != 0); // wait until BSY=0
|
|
316
|
+}
|
|
317
|
+
|
|
318
|
+void SPIClass::write(uint16_t data, uint32_t n) {
|
|
319
|
+ // Added by stevstrong: Repeatedly send same data by the specified number of times
|
|
320
|
+ spi_reg_map * regs = _currentSetting->spi_d->regs;
|
|
321
|
+ while ( (n--)>0 ) {
|
|
322
|
+ regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
|
|
323
|
+ while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
|
|
324
|
+ }
|
|
325
|
+ while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning
|
|
326
|
+}
|
|
327
|
+
|
|
328
|
+void SPIClass::write(const void *data, uint32_t length) {
|
|
329
|
+ spi_dev * spi_d = _currentSetting->spi_d;
|
|
330
|
+ spi_tx(spi_d, data, length); // data can be array of bytes or words
|
|
331
|
+ while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
332
|
+ while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
333
|
+}
|
|
334
|
+
|
|
335
|
+uint8_t SPIClass::transfer(uint8_t byte) const {
|
|
336
|
+ spi_dev * spi_d = _currentSetting->spi_d;
|
|
337
|
+ spi_rx_reg(spi_d); // read any previous data
|
|
338
|
+ spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
|
|
339
|
+ while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
340
|
+ while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
341
|
+ return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
|
|
342
|
+}
|
|
343
|
+
|
|
344
|
+uint16_t SPIClass::transfer16(uint16_t data) const {
|
|
345
|
+ // Modified by stevestrong: write & read two consecutive bytes in 8 bit mode (DFF=0)
|
|
346
|
+ // This is more effective than two distinct byte transfers
|
|
347
|
+ spi_dev * spi_d = _currentSetting->spi_d;
|
|
348
|
+ spi_rx_reg(spi_d); // read any previous data
|
|
349
|
+ spi_tx_reg(spi_d, data>>8); // write high byte
|
|
350
|
+ while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
|
|
351
|
+ while (spi_is_busy(spi_d) != 0); // wait until BSY=0
|
|
352
|
+ uint16_t ret = spi_rx_reg(spi_d)<<8; // read and shift high byte
|
|
353
|
+ spi_tx_reg(spi_d, data); // write low byte
|
|
354
|
+ while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
|
|
355
|
+ while (spi_is_busy(spi_d) != 0); // wait until BSY=0
|
|
356
|
+ ret += spi_rx_reg(spi_d); // read low byte
|
|
357
|
+ return ret;
|
|
358
|
+}
|
|
359
|
+
|
|
360
|
+/* Roger Clark and Victor Perez, 2015
|
|
361
|
+* Performs a DMA SPI transfer with at least a receive buffer.
|
|
362
|
+* If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer.
|
|
363
|
+* On exit TX buffer is not modified, and RX buffer cotains the received data.
|
|
364
|
+* Still in progress.
|
|
365
|
+*/
|
|
366
|
+void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) {
|
|
367
|
+ dma_init(_currentSetting->spiDmaDev);
|
|
368
|
+ //spi_rx_dma_enable(_currentSetting->spi_d);
|
|
369
|
+ //spi_tx_dma_enable(_currentSetting->spi_d);
|
|
370
|
+ dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
|
|
371
|
+ dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR,
|
|
372
|
+ dma_bit_size, receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT ));// receive buffer DMA
|
|
373
|
+ if (!transmitBuf) {
|
|
374
|
+ transmitBuf = &ff;
|
|
375
|
+ dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR,
|
|
376
|
+ dma_bit_size, (volatile void*)transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly
|
|
377
|
+ }
|
|
378
|
+ else {
|
|
379
|
+ dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR,
|
|
380
|
+ dma_bit_size, (volatile void*)transmitBuf, dma_bit_size, (DMA_MINC_MODE | DMA_FROM_MEM ));// Transmit buffer DMA
|
|
381
|
+ }
|
|
382
|
+ dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
|
|
383
|
+ dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
|
|
384
|
+}
|
|
385
|
+
|
|
386
|
+uint8_t SPIClass::dmaTransferRepeat(uint16_t length) {
|
|
387
|
+ if (length == 0) return 0;
|
|
388
|
+ if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d);
|
|
389
|
+ _currentSetting->state = SPI_STATE_TRANSFER;
|
|
390
|
+ dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
|
|
391
|
+ dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
|
392
|
+ dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
|
|
393
|
+ dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
|
394
|
+ spi_rx_dma_enable(_currentSetting->spi_d);
|
|
395
|
+ spi_tx_dma_enable(_currentSetting->spi_d);
|
|
396
|
+ if (_currentSetting->receiveCallback)
|
|
397
|
+ return 0;
|
|
398
|
+
|
|
399
|
+ //uint32_t m = millis();
|
|
400
|
+ uint8_t b = 0;
|
|
401
|
+ uint32_t m = millis();
|
|
402
|
+ while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1) == 0) {
|
|
403
|
+ //Avoid interrupts and just loop waiting for the flag to be set.
|
|
404
|
+ if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
405
|
+ }
|
|
406
|
+
|
|
407
|
+ while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
408
|
+ while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
409
|
+ spi_tx_dma_disable(_currentSetting->spi_d);
|
|
410
|
+ spi_rx_dma_disable(_currentSetting->spi_d);
|
|
411
|
+ dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
412
|
+ dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
|
413
|
+ dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
|
414
|
+ dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
415
|
+ _currentSetting->state = SPI_STATE_READY;
|
|
416
|
+ return b;
|
|
417
|
+}
|
|
418
|
+
|
|
419
|
+/* Roger Clark and Victor Perez, 2015
|
|
420
|
+ * Performs a DMA SPI transfer with at least a receive buffer.
|
|
421
|
+ * If a TX buffer is not provided, FF is sent over and over for the length of the transfer.
|
|
422
|
+ * On exit TX buffer is not modified, and RX buffer contains the received data.
|
|
423
|
+ * Still in progress.
|
|
424
|
+ */
|
|
425
|
+uint8_t SPIClass::dmaTransfer(const void *transmitBuf, void *receiveBuf, uint16_t length) {
|
|
426
|
+ dmaTransferSet(transmitBuf, receiveBuf);
|
|
427
|
+ return dmaTransferRepeat(length);
|
|
428
|
+}
|
|
429
|
+
|
|
430
|
+/* Roger Clark and Victor Perez, 2015
|
|
431
|
+ * Performs a DMA SPI send using a TX buffer.
|
|
432
|
+ * On exit TX buffer is not modified.
|
|
433
|
+ * Still in progress.
|
|
434
|
+ * 2016 - stevstrong - reworked to automatically detect bit size from SPI setting
|
|
435
|
+ */
|
|
436
|
+void SPIClass::dmaSendSet(const void * transmitBuf, bool minc) {
|
|
437
|
+ uint32_t flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
|
|
438
|
+ dma_init(_currentSetting->spiDmaDev);
|
|
439
|
+ dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
|
|
440
|
+ dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
|
|
441
|
+ (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
|
|
442
|
+ dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
|
|
443
|
+}
|
|
444
|
+
|
|
445
|
+uint8_t SPIClass::dmaSendRepeat(uint16_t length) {
|
|
446
|
+ if (length == 0) return 0;
|
|
447
|
+
|
|
448
|
+ dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
449
|
+ dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
|
450
|
+ _currentSetting->state = SPI_STATE_TRANSMIT;
|
|
451
|
+ dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
|
452
|
+ spi_tx_dma_enable(_currentSetting->spi_d);
|
|
453
|
+ if (_currentSetting->transmitCallback)
|
|
454
|
+ return 0;
|
|
455
|
+
|
|
456
|
+ uint32_t m = millis();
|
|
457
|
+ uint8_t b = 0;
|
|
458
|
+ while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
|
459
|
+ //Avoid interrupts and just loop waiting for the flag to be set.
|
|
460
|
+ if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
461
|
+ }
|
|
462
|
+ while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
463
|
+ while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
464
|
+ spi_tx_dma_disable(_currentSetting->spi_d);
|
|
465
|
+ dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
466
|
+ dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
467
|
+ _currentSetting->state = SPI_STATE_READY;
|
|
468
|
+ return b;
|
|
469
|
+}
|
|
470
|
+
|
|
471
|
+uint8_t SPIClass::dmaSend(const void * transmitBuf, uint16_t length, bool minc) {
|
|
472
|
+ dmaSendSet(transmitBuf, minc);
|
|
473
|
+ return dmaSendRepeat(length);
|
|
474
|
+}
|
|
475
|
+
|
|
476
|
+uint8_t SPIClass::dmaSendAsync(const void * transmitBuf, uint16_t length, bool minc) {
|
|
477
|
+ uint8_t b = 0;
|
|
478
|
+
|
|
479
|
+ if (_currentSetting->state != SPI_STATE_READY) {
|
|
480
|
+ uint32_t m = millis();
|
|
481
|
+ while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
|
|
482
|
+ //Avoid interrupts and just loop waiting for the flag to be set.
|
|
483
|
+ //delayMicroseconds(10);
|
|
484
|
+ if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
|
|
485
|
+ }
|
|
486
|
+
|
|
487
|
+ while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
488
|
+ while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
|
|
489
|
+ spi_tx_dma_disable(_currentSetting->spi_d);
|
|
490
|
+ dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
491
|
+ _currentSetting->state = SPI_STATE_READY;
|
|
492
|
+ }
|
|
493
|
+
|
|
494
|
+ if (length == 0) return 0;
|
|
495
|
+ uint32_t flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
|
|
496
|
+
|
|
497
|
+ dma_init(_currentSetting->spiDmaDev);
|
|
498
|
+ // TX
|
|
499
|
+ dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
|
|
500
|
+ dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR,
|
|
501
|
+ dma_bit_size, (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
|
|
502
|
+ dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
|
|
503
|
+ dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
504
|
+ dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
|
|
505
|
+ spi_tx_dma_enable(_currentSetting->spi_d);
|
|
506
|
+
|
|
507
|
+ _currentSetting->state = SPI_STATE_TRANSMIT;
|
|
508
|
+ return b;
|
|
509
|
+}
|
|
510
|
+
|
|
511
|
+
|
|
512
|
+/**
|
|
513
|
+ * New functions added to manage callbacks.
|
|
514
|
+ * Victor Perez 2017
|
|
515
|
+ */
|
|
516
|
+void SPIClass::onReceive(void(*callback)(void)) {
|
|
517
|
+ _currentSetting->receiveCallback = callback;
|
|
518
|
+ if (callback) {
|
|
519
|
+ switch (_currentSetting->spi_d->clk_id) {
|
|
520
|
+ #if BOARD_NR_SPI >= 1
|
|
521
|
+ case RCC_SPI1:
|
|
522
|
+ dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback);
|
|
523
|
+ break;
|
|
524
|
+ #endif
|
|
525
|
+ #if BOARD_NR_SPI >= 2
|
|
526
|
+ case RCC_SPI2:
|
|
527
|
+ dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback);
|
|
528
|
+ break;
|
|
529
|
+ #endif
|
|
530
|
+ #if BOARD_NR_SPI >= 3
|
|
531
|
+ case RCC_SPI3:
|
|
532
|
+ dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback);
|
|
533
|
+ break;
|
|
534
|
+ #endif
|
|
535
|
+ default:
|
|
536
|
+ ASSERT(0);
|
|
537
|
+ }
|
|
538
|
+ }
|
|
539
|
+ else {
|
|
540
|
+ dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
|
541
|
+ }
|
|
542
|
+}
|
|
543
|
+
|
|
544
|
+void SPIClass::onTransmit(void(*callback)(void)) {
|
|
545
|
+ _currentSetting->transmitCallback = callback;
|
|
546
|
+ if (callback) {
|
|
547
|
+ switch (_currentSetting->spi_d->clk_id) {
|
|
548
|
+ #if BOARD_NR_SPI >= 1
|
|
549
|
+ case RCC_SPI1:
|
|
550
|
+ dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback);
|
|
551
|
+ break;
|
|
552
|
+ #endif
|
|
553
|
+ #if BOARD_NR_SPI >= 2
|
|
554
|
+ case RCC_SPI2:
|
|
555
|
+ dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback);
|
|
556
|
+ break;
|
|
557
|
+ #endif
|
|
558
|
+ #if BOARD_NR_SPI >= 3
|
|
559
|
+ case RCC_SPI3:
|
|
560
|
+ dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback);
|
|
561
|
+ break;
|
|
562
|
+ #endif
|
|
563
|
+ default:
|
|
564
|
+ ASSERT(0);
|
|
565
|
+ }
|
|
566
|
+ }
|
|
567
|
+ else {
|
|
568
|
+ dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
569
|
+ }
|
|
570
|
+}
|
|
571
|
+
|
|
572
|
+/**
|
|
573
|
+ * TODO: check if better to first call the customer code, next disable the DMA requests.
|
|
574
|
+ * Also see if we need to check whether callbacks are set or not, may be better to be checked
|
|
575
|
+ * during the initial setup and only set the callback to EventCallback if they are set.
|
|
576
|
+ */
|
|
577
|
+void SPIClass::EventCallback() {
|
|
578
|
+ while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
|
|
579
|
+ while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
|
|
580
|
+ switch (_currentSetting->state) {
|
|
581
|
+ case SPI_STATE_TRANSFER:
|
|
582
|
+ while (spi_is_rx_nonempty(_currentSetting->spi_d));
|
|
583
|
+ _currentSetting->state = SPI_STATE_READY;
|
|
584
|
+ spi_tx_dma_disable(_currentSetting->spi_d);
|
|
585
|
+ spi_rx_dma_disable(_currentSetting->spi_d);
|
|
586
|
+ //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
587
|
+ //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
|
|
588
|
+ if (_currentSetting->receiveCallback)
|
|
589
|
+ _currentSetting->receiveCallback();
|
|
590
|
+ break;
|
|
591
|
+ case SPI_STATE_TRANSMIT:
|
|
592
|
+ _currentSetting->state = SPI_STATE_READY;
|
|
593
|
+ spi_tx_dma_disable(_currentSetting->spi_d);
|
|
594
|
+ //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
|
|
595
|
+ if (_currentSetting->transmitCallback)
|
|
596
|
+ _currentSetting->transmitCallback();
|
|
597
|
+ break;
|
|
598
|
+ default:
|
|
599
|
+ break;
|
|
600
|
+ }
|
|
601
|
+}
|
|
602
|
+
|
|
603
|
+void SPIClass::attachInterrupt() {
|
|
604
|
+ // Should be enableInterrupt()
|
|
605
|
+}
|
|
606
|
+
|
|
607
|
+void SPIClass::detachInterrupt() {
|
|
608
|
+ // Should be disableInterrupt()
|
|
609
|
+}
|
|
610
|
+
|
|
611
|
+/*
|
|
612
|
+ * Pin accessors
|
|
613
|
+ */
|
|
614
|
+
|
|
615
|
+uint8_t SPIClass::misoPin() {
|
|
616
|
+ return dev_to_spi_pins(_currentSetting->spi_d)->miso;
|
|
617
|
+}
|
|
618
|
+
|
|
619
|
+uint8_t SPIClass::mosiPin() {
|
|
620
|
+ return dev_to_spi_pins(_currentSetting->spi_d)->mosi;
|
|
621
|
+}
|
|
622
|
+
|
|
623
|
+uint8_t SPIClass::sckPin() {
|
|
624
|
+ return dev_to_spi_pins(_currentSetting->spi_d)->sck;
|
|
625
|
+}
|
|
626
|
+
|
|
627
|
+uint8_t SPIClass::nssPin() {
|
|
628
|
+ return dev_to_spi_pins(_currentSetting->spi_d)->nss;
|
|
629
|
+}
|
|
630
|
+
|
|
631
|
+/*
|
|
632
|
+ * Deprecated functions
|
|
633
|
+ */
|
|
634
|
+
|
|
635
|
+uint8_t SPIClass::send(uint8_t data) {
|
|
636
|
+ this->write(data);
|
|
637
|
+ return 1;
|
|
638
|
+}
|
|
639
|
+
|
|
640
|
+uint8_t SPIClass::send(uint8_t *buf, uint32_t len) {
|
|
641
|
+ this->write(buf, len);
|
|
642
|
+ return len;
|
|
643
|
+}
|
|
644
|
+
|
|
645
|
+uint8_t SPIClass::recv() {
|
|
646
|
+ return this->read();
|
|
647
|
+}
|
|
648
|
+
|
|
649
|
+/*
|
|
650
|
+ * DMA call back functions, one per port.
|
|
651
|
+ */
|
|
652
|
+#if BOARD_NR_SPI >= 1
|
|
653
|
+ void SPIClass::_spi1EventCallback() {
|
|
654
|
+ reinterpret_cast<class SPIClass*>(_spi1_this)->EventCallback();
|
|
655
|
+ }
|
|
656
|
+#endif
|
|
657
|
+#if BOARD_NR_SPI >= 2
|
|
658
|
+ void SPIClass::_spi2EventCallback() {
|
|
659
|
+ reinterpret_cast<class SPIClass*>(_spi2_this)->EventCallback();
|
|
660
|
+ }
|
|
661
|
+#endif
|
|
662
|
+#if BOARD_NR_SPI >= 3
|
|
663
|
+ void SPIClass::_spi3EventCallback() {
|
|
664
|
+ reinterpret_cast<class SPIClass*>(_spi3_this)->EventCallback();
|
|
665
|
+ }
|
|
666
|
+#endif
|
|
667
|
+
|
|
668
|
+/*
|
|
669
|
+ * Auxiliary functions
|
|
670
|
+ */
|
|
671
|
+static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
|
|
672
|
+ switch (dev->clk_id) {
|
|
673
|
+ #if BOARD_NR_SPI >= 1
|
|
674
|
+ case RCC_SPI1: return board_spi_pins;
|
|
675
|
+ #endif
|
|
676
|
+ #if BOARD_NR_SPI >= 2
|
|
677
|
+ case RCC_SPI2: return board_spi_pins + 1;
|
|
678
|
+ #endif
|
|
679
|
+ #if BOARD_NR_SPI >= 3
|
|
680
|
+ case RCC_SPI3: return board_spi_pins + 2;
|
|
681
|
+ #endif
|
|
682
|
+ default: return NULL;
|
|
683
|
+ }
|
|
684
|
+}
|
|
685
|
+
|
|
686
|
+static void disable_pwm(const stm32_pin_info *i) {
|
|
687
|
+ if (i->timer_device)
|
|
688
|
+ timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
|
|
689
|
+}
|
|
690
|
+
|
|
691
|
+static void configure_gpios(spi_dev *dev, bool as_master) {
|
|
692
|
+ const spi_pins *pins = dev_to_spi_pins(dev);
|
|
693
|
+ if (!pins) return;
|
|
694
|
+
|
|
695
|
+ const stm32_pin_info *nssi = &PIN_MAP[pins->nss],
|
|
696
|
+ *scki = &PIN_MAP[pins->sck],
|
|
697
|
+ *misoi = &PIN_MAP[pins->miso],
|
|
698
|
+ *mosii = &PIN_MAP[pins->mosi];
|
|
699
|
+
|
|
700
|
+ disable_pwm(nssi);
|
|
701
|
+ disable_pwm(scki);
|
|
702
|
+ disable_pwm(misoi);
|
|
703
|
+ disable_pwm(mosii);
|
|
704
|
+
|
|
705
|
+ spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
|
|
706
|
+ scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
|
|
707
|
+ mosii->gpio_bit);
|
|
708
|
+}
|
|
709
|
+
|
|
710
|
+static const spi_baud_rate baud_rates[8] __FLASH__ = {
|
|
711
|
+ SPI_BAUD_PCLK_DIV_2,
|
|
712
|
+ SPI_BAUD_PCLK_DIV_4,
|
|
713
|
+ SPI_BAUD_PCLK_DIV_8,
|
|
714
|
+ SPI_BAUD_PCLK_DIV_16,
|
|
715
|
+ SPI_BAUD_PCLK_DIV_32,
|
|
716
|
+ SPI_BAUD_PCLK_DIV_64,
|
|
717
|
+ SPI_BAUD_PCLK_DIV_128,
|
|
718
|
+ SPI_BAUD_PCLK_DIV_256,
|
|
719
|
+};
|
|
720
|
+
|
|
721
|
+/*
|
|
722
|
+* Note: This assumes you're on a LeafLabs-style board
|
|
723
|
+* (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
|
|
724
|
+*/
|
|
725
|
+static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
|
|
726
|
+ uint32_t clock = 0;
|
|
727
|
+ switch (rcc_dev_clk(dev->clk_id)) {
|
|
728
|
+ case RCC_AHB:
|
|
729
|
+ case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
|
|
730
|
+ case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
|
|
731
|
+ }
|
|
732
|
+ clock >>= 1;
|
|
733
|
+
|
|
734
|
+ uint8_t i = 0;
|
|
735
|
+ while (i < 7 && freq < clock) { clock >>= 1; i++; }
|
|
736
|
+ return baud_rates[i];
|
|
737
|
+}
|
|
738
|
+
|
|
739
|
+SPIClass SPI(1);
|
|
740
|
+
|
|
741
|
+#endif // __STM32F1__
|