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@@ -22,391 +22,297 @@
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#ifdef TARGET_LPC1768
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-#include "../../core/macros.h"
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-#include "../HAL.h"
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+#include "../../inc/MarlinConfig.h"
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#include "HardwareSerial.h"
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-#define UART3 3
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-HardwareSerial Serial3 = HardwareSerial(UART3);
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-
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-volatile uint32_t UART0Status, UART1Status, UART2Status, UART3Status;
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-volatile uint8_t UART0TxEmpty = 1, UART1TxEmpty = 1, UART2TxEmpty=1, UART3TxEmpty=1;
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-volatile uint8_t UART0Buffer[UARTRXQUEUESIZE], UART1Buffer[UARTRXQUEUESIZE], UART2Buffer[UARTRXQUEUESIZE], UART3Buffer[UARTRXQUEUESIZE];
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-volatile uint32_t UART0RxQueueWritePos = 0, UART1RxQueueWritePos = 0, UART2RxQueueWritePos = 0, UART3RxQueueWritePos = 0;
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-volatile uint32_t UART0RxQueueReadPos = 0, UART1RxQueueReadPos = 0, UART2RxQueueReadPos = 0, UART3RxQueueReadPos = 0;
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-volatile uint8_t dummy;
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-
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- void HardwareSerial::begin(uint32_t baudrate) {
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- uint32_t Fdiv;
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- uint32_t pclkdiv, pclk;
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-
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- if ( PortNum == 0 )
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- {
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- LPC_PINCON->PINSEL0 &= ~0x000000F0;
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- LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 6~7 is for UART0 */
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- pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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-
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- LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART0->DLM = Fdiv / 256;
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- LPC_UART0->DLL = Fdiv % 256;
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- LPC_UART0->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART0_IRQn);
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-
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- LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART0 interrupt */
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- }
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- else if ( PortNum == 1 )
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- {
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- LPC_PINCON->PINSEL4 &= ~0x0000000F;
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- LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
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-
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 8,9 are for UART1 */
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- pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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-
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- LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART1->DLM = Fdiv / 256;
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- LPC_UART1->DLL = Fdiv % 256;
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- LPC_UART1->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART1_IRQn);
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-
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- LPC_UART1->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART1 interrupt */
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- }
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- else if ( PortNum == 2 )
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- {
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- //LPC_PINCON->PINSEL4 &= ~0x000F0000; /*Pinsel4 Bits 16-19*/
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- //LPC_PINCON->PINSEL4 |= 0x000A0000; /* RxD2 is P2.9 and TxD2 is P2.8, value 10*/
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- LPC_PINCON->PINSEL0 &= ~0x00F00000; /*Pinsel0 Bits 20-23*/
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- LPC_PINCON->PINSEL0 |= 0x00500000; /* RxD2 is P0.11 and TxD2 is P0.10, value 01*/
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-
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- LPC_SC->PCONP |= 1<<24; //Enable PCUART2
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 6~7 is for UART3 */
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- pclkdiv = (LPC_SC->PCLKSEL1 >> 16) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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- LPC_UART2->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART2->DLM = Fdiv / 256;
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- LPC_UART2->DLL = Fdiv % 256;
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- LPC_UART2->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART2->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART2_IRQn);
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-
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- LPC_UART2->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
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- }
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- else if ( PortNum == 3 )
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- {
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- LPC_PINCON->PINSEL0 &= ~0x0000000F;
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- LPC_PINCON->PINSEL0 |= 0x0000000A; /* RxD3 is P0.1 and TxD3 is P0.0 */
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- LPC_SC->PCONP |= 1<<4 | 1<<25; //Enable PCUART1
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 6~7 is for UART3 */
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- pclkdiv = (LPC_SC->PCLKSEL1 >> 18) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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- LPC_UART3->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART3->DLM = Fdiv / 256;
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- LPC_UART3->DLL = Fdiv % 256;
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- LPC_UART3->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART3->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART3_IRQn);
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-
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- LPC_UART3->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
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- }
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- }
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- int HardwareSerial::read() {
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- uint8_t rx;
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- if ( PortNum == 0 )
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- {
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- if (UART0RxQueueReadPos == UART0RxQueueWritePos)
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- return -1;
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-
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- // Read from "head"
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- rx = UART0Buffer[UART0RxQueueReadPos]; // grab next byte
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- UART0RxQueueReadPos = (UART0RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- if ( PortNum == 1 )
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- {
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- if (UART1RxQueueReadPos == UART1RxQueueWritePos)
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- return -1;
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-
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- // Read from "head"
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- rx = UART1Buffer[UART1RxQueueReadPos]; // grab next byte
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- UART1RxQueueReadPos = (UART1RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- if ( PortNum == 2 )
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- {
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- if (UART2RxQueueReadPos == UART2RxQueueWritePos)
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- return -1;
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-
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- // Read from "head"
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- rx = UART2Buffer[UART2RxQueueReadPos]; // grab next byte
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- UART2RxQueueReadPos = (UART2RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- if ( PortNum == 3 )
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- {
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- if (UART3RxQueueReadPos == UART3RxQueueWritePos)
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- return -1;
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-
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- // Read from "head"
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- rx = UART3Buffer[UART3RxQueueReadPos]; // grab next byte
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- UART3RxQueueReadPos = (UART3RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- return 0;
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+HardwareSerial Serial = HardwareSerial(LPC_UART0);
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+HardwareSerial Serial1 = HardwareSerial((LPC_UART_TypeDef *) LPC_UART1);
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+HardwareSerial Serial2 = HardwareSerial(LPC_UART2);
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+HardwareSerial Serial3 = HardwareSerial(LPC_UART3);
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+
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+void HardwareSerial::begin(uint32_t baudrate) {
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+
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+ UART_CFG_Type UARTConfigStruct;
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+ PINSEL_CFG_Type PinCfg;
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+ UART_FIFO_CFG_Type FIFOConfig;
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+
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+ if (UARTx == LPC_UART0) {
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+ /*
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+ * Initialize UART0 pin connect
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+ */
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+ PinCfg.Funcnum = 1;
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+ PinCfg.OpenDrain = 0;
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+ PinCfg.Pinmode = 0;
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+ PinCfg.Pinnum = 2;
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+ PinCfg.Portnum = 0;
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+ PINSEL_ConfigPin(&PinCfg);
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+ PinCfg.Pinnum = 3;
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+ PINSEL_ConfigPin(&PinCfg);
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}
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-
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- size_t HardwareSerial::write(uint8_t send) {
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- if ( PortNum == 0 )
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- {
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- /* THRE status, contain valid data */
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- while ( !(UART0TxEmpty & 0x01) );
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- LPC_UART0->THR = send;
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- UART0TxEmpty = 0; /* not empty in the THR until it shifts out */
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- }
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- else if (PortNum == 1)
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- {
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-
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- /* THRE status, contain valid data */
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- while ( !(UART1TxEmpty & 0x01) );
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- LPC_UART1->THR = send;
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- UART1TxEmpty = 0; /* not empty in the THR until it shifts out */
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-
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-
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- }
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- else if ( PortNum == 2 )
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- {
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- /* THRE status, contain valid data */
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- while ( !(UART2TxEmpty & 0x01) );
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- LPC_UART2->THR = send;
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- UART2TxEmpty = 0; /* not empty in the THR until it shifts out */
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-
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- }
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- else if ( PortNum == 3 )
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- {
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- /* THRE status, contain valid data */
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- while ( !(UART3TxEmpty & 0x01) );
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- LPC_UART3->THR = send;
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- UART3TxEmpty = 0; /* not empty in the THR until it shifts out */
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-
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- }
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- return 0;
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+ else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1) {
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+ /*
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+ * Initialize UART1 pin connect
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+ */
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+ PinCfg.Funcnum = 1;
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+ PinCfg.OpenDrain = 0;
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+ PinCfg.Pinmode = 0;
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+ PinCfg.Pinnum = 15;
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+ PinCfg.Portnum = 0;
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+ PINSEL_ConfigPin(&PinCfg);
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+ PinCfg.Pinnum = 16;
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+ PINSEL_ConfigPin(&PinCfg);
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+ }
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+ else if (UARTx == LPC_UART2) {
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+ /*
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+ * Initialize UART2 pin connect
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+ */
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+ PinCfg.Funcnum = 1;
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+ PinCfg.OpenDrain = 0;
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+ PinCfg.Pinmode = 0;
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+ PinCfg.Pinnum = 10;
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+ PinCfg.Portnum = 0;
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+ PINSEL_ConfigPin(&PinCfg);
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+ PinCfg.Pinnum = 11;
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+ PINSEL_ConfigPin(&PinCfg);
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+ }
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+ else if (UARTx == LPC_UART3) {
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+ /*
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+ * Initialize UART2 pin connect
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+ */
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+ PinCfg.Funcnum = 1;
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+ PinCfg.OpenDrain = 0;
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+ PinCfg.Pinmode = 0;
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+ PinCfg.Pinnum = 0;
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+ PinCfg.Portnum = 0;
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+ PINSEL_ConfigPin(&PinCfg);
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+ PinCfg.Pinnum = 1;
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+ PINSEL_ConfigPin(&PinCfg);
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}
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- int HardwareSerial::available() {
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- if ( PortNum == 0 )
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-{
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- return (UART0RxQueueWritePos + UARTRXQUEUESIZE - UART0RxQueueReadPos) % UARTRXQUEUESIZE;
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-}
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-if ( PortNum == 1 )
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-{
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- return (UART1RxQueueWritePos + UARTRXQUEUESIZE - UART1RxQueueReadPos) % UARTRXQUEUESIZE;
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-}
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-if ( PortNum == 2 )
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-{
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- return (UART2RxQueueWritePos + UARTRXQUEUESIZE - UART2RxQueueReadPos) % UARTRXQUEUESIZE;
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-}
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-if ( PortNum == 3 )
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-{
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- return (UART3RxQueueWritePos + UARTRXQUEUESIZE - UART3RxQueueReadPos) % UARTRXQUEUESIZE;
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+ /* Initialize UART Configuration parameter structure to default state:
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+ * Baudrate = 9600bps
|
|
94
|
+ * 8 data bit
|
|
95
|
+ * 1 Stop bit
|
|
96
|
+ * None parity
|
|
97
|
+ */
|
|
98
|
+ UART_ConfigStructInit(&UARTConfigStruct);
|
|
99
|
+
|
|
100
|
+ // Re-configure baudrate
|
|
101
|
+ UARTConfigStruct.Baud_rate = baudrate;
|
|
102
|
+
|
|
103
|
+ // Initialize eripheral with given to corresponding parameter
|
|
104
|
+ UART_Init(UARTx, &UARTConfigStruct);
|
|
105
|
+
|
|
106
|
+ // Enable and reset the TX and RX FIFOs
|
|
107
|
+ UART_FIFOConfigStructInit(&FIFOConfig);
|
|
108
|
+ UART_FIFOConfig(UARTx, &FIFOConfig);
|
|
109
|
+
|
|
110
|
+ // Enable UART Transmit
|
|
111
|
+ UART_TxCmd(UARTx, ENABLE);
|
|
112
|
+
|
|
113
|
+ // Configure Interrupts
|
|
114
|
+ UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
|
|
115
|
+ UART_IntConfig(UARTx, UART_INTCFG_RLS, ENABLE);
|
|
116
|
+
|
|
117
|
+ if (UARTx == LPC_UART0)
|
|
118
|
+ NVIC_EnableIRQ(UART0_IRQn);
|
|
119
|
+ else if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
|
|
120
|
+ NVIC_EnableIRQ(UART1_IRQn);
|
|
121
|
+ else if (UARTx == LPC_UART2)
|
|
122
|
+ NVIC_EnableIRQ(UART2_IRQn);
|
|
123
|
+ else if (UARTx == LPC_UART3)
|
|
124
|
+ NVIC_EnableIRQ(UART3_IRQn);
|
|
125
|
+
|
|
126
|
+ RxQueueWritePos = RxQueueReadPos = 0;
|
|
127
|
+ #if TX_BUFFER_SIZE > 0
|
|
128
|
+ TxQueueWritePos = TxQueueReadPos = 0;
|
|
129
|
+ #endif
|
290
|
130
|
}
|
291
|
|
-return 0;
|
292
|
|
- }
|
293
|
131
|
|
294
|
|
- void HardwareSerial::flush() {
|
295
|
|
- if ( PortNum == 0 )
|
296
|
|
-{
|
297
|
|
- UART0RxQueueWritePos = 0;
|
298
|
|
- UART0RxQueueReadPos = 0;
|
|
132
|
+int HardwareSerial::peek() {
|
|
133
|
+ int byte = -1;
|
299
|
134
|
|
|
135
|
+ /* Temporarily lock out UART receive interrupts during this read so the UART receive
|
|
136
|
+ interrupt won't cause problems with the index values */
|
|
137
|
+ UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
|
|
138
|
+
|
|
139
|
+ if (RxQueueReadPos != RxQueueWritePos)
|
|
140
|
+ byte = RxBuffer[RxQueueReadPos];
|
|
141
|
+
|
|
142
|
+ /* Re-enable UART interrupts */
|
|
143
|
+ UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
|
|
144
|
+
|
|
145
|
+ return byte;
|
300
|
146
|
}
|
301
|
|
-if ( PortNum == 1 )
|
302
|
|
-{
|
303
|
|
- UART1RxQueueWritePos = 0;
|
304
|
|
- UART1RxQueueReadPos = 0;
|
305
|
|
-}
|
306
|
|
-if ( PortNum == 2 )
|
307
|
|
-{
|
308
|
|
- UART2RxQueueWritePos = 0;
|
309
|
|
- UART2RxQueueReadPos = 0;
|
310
|
|
-}
|
311
|
|
-if ( PortNum == 3 )
|
312
|
|
-{
|
313
|
|
- UART3RxQueueWritePos = 0;
|
314
|
|
- UART3RxQueueReadPos = 0;
|
315
|
|
-}
|
316
|
|
-return;
|
|
147
|
+
|
|
148
|
+int HardwareSerial::read() {
|
|
149
|
+ int byte = -1;
|
|
150
|
+
|
|
151
|
+ /* Temporarily lock out UART receive interrupts during this read so the UART receive
|
|
152
|
+ interrupt won't cause problems with the index values */
|
|
153
|
+ UART_IntConfig(UARTx, UART_INTCFG_RBR, DISABLE);
|
|
154
|
+
|
|
155
|
+ if (RxQueueReadPos != RxQueueWritePos) {
|
|
156
|
+ byte = RxBuffer[RxQueueReadPos];
|
|
157
|
+ RxQueueReadPos = (RxQueueReadPos + 1) % RX_BUFFER_SIZE;
|
317
|
158
|
}
|
318
|
159
|
|
319
|
|
- void HardwareSerial::printf(const char *format, ...) {
|
320
|
|
- static char buffer[256];
|
321
|
|
- va_list vArgs;
|
322
|
|
- va_start(vArgs, format);
|
323
|
|
- int length = vsnprintf((char *) buffer, 256, (char const *) format, vArgs);
|
324
|
|
- va_end(vArgs);
|
325
|
|
- if (length > 0 && length < 256) {
|
326
|
|
- for (int i = 0; i < length;) {
|
327
|
|
- write(buffer[i]);
|
328
|
|
- ++i;
|
329
|
|
- }
|
330
|
|
- }
|
|
160
|
+ /* Re-enable UART interrupts */
|
|
161
|
+ UART_IntConfig(UARTx, UART_INTCFG_RBR, ENABLE);
|
|
162
|
+
|
|
163
|
+ return byte;
|
|
164
|
+}
|
|
165
|
+
|
|
166
|
+size_t HardwareSerial::write(uint8_t send) {
|
|
167
|
+ #if TX_BUFFER_SIZE > 0
|
|
168
|
+ size_t bytes = 0;
|
|
169
|
+ uint32_t fifolvl = 0;
|
|
170
|
+
|
|
171
|
+ /* If the Tx Buffer is full, wait for space to clear */
|
|
172
|
+ if ((TxQueueWritePos+1) % TX_BUFFER_SIZE == TxQueueReadPos) flushTX();
|
|
173
|
+
|
|
174
|
+ /* Temporarily lock out UART transmit interrupts during this read so the UART transmit interrupt won't
|
|
175
|
+ cause problems with the index values */
|
|
176
|
+ UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
|
|
177
|
+
|
|
178
|
+ /* LPC17xx.h incorrectly defines FIFOLVL as a uint8_t, when it's actually a 32-bit register */
|
|
179
|
+ if ((LPC_UART1_TypeDef *) UARTx == LPC_UART1)
|
|
180
|
+ fifolvl = *(reinterpret_cast<volatile uint32_t *>(&((LPC_UART1_TypeDef *) UARTx)->FIFOLVL));
|
|
181
|
+ else
|
|
182
|
+ fifolvl = *(reinterpret_cast<volatile uint32_t *>(&UARTx->FIFOLVL));
|
|
183
|
+
|
|
184
|
+ /* If the queue is empty and there's space in the FIFO, immediately send the byte */
|
|
185
|
+ if (TxQueueWritePos == TxQueueReadPos && fifolvl < UART_TX_FIFO_SIZE) {
|
|
186
|
+ bytes = UART_Send(UARTx, &send, 1, BLOCKING);
|
331
|
187
|
}
|
|
188
|
+ /* Otherwiise, write the byte to the transmit buffer */
|
|
189
|
+ else if ((TxQueueWritePos+1) % TX_BUFFER_SIZE != TxQueueReadPos) {
|
|
190
|
+ TxBuffer[TxQueueWritePos] = send;
|
|
191
|
+ TxQueueWritePos = (TxQueueWritePos+1) % TX_BUFFER_SIZE;
|
|
192
|
+ bytes++;
|
|
193
|
+ }
|
|
194
|
+
|
|
195
|
+ /* Re-enable the TX Interrupt */
|
|
196
|
+ UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
|
|
197
|
+
|
|
198
|
+ return bytes;
|
|
199
|
+ #else
|
|
200
|
+ return UART_Send(UARTx, &send, 1, BLOCKING);
|
|
201
|
+ #endif
|
|
202
|
+}
|
332
|
203
|
|
333
|
|
-#ifdef __cplusplus
|
334
|
|
-extern "C" {
|
|
204
|
+#if TX_BUFFER_SIZE > 0
|
|
205
|
+ void HardwareSerial::flushTX() {
|
|
206
|
+ /* Wait for the tx buffer and FIFO to drain */
|
|
207
|
+ while (TxQueueWritePos != TxQueueReadPos && UART_CheckBusy(UARTx) == SET);
|
|
208
|
+ }
|
335
|
209
|
#endif
|
336
|
210
|
|
337
|
|
-/*****************************************************************************
|
338
|
|
-** Function name: UART0_IRQHandler
|
339
|
|
-**
|
340
|
|
-** Descriptions: UART0 interrupt handler
|
341
|
|
-**
|
342
|
|
-** parameters: None
|
343
|
|
-** Returned value: None
|
344
|
|
-**
|
345
|
|
-*****************************************************************************/
|
346
|
|
-void UART0_IRQHandler (void)
|
347
|
|
-{
|
348
|
|
- uint8_t IIRValue, LSRValue;
|
|
211
|
+int HardwareSerial::available() {
|
|
212
|
+ return (RxQueueWritePos + RX_BUFFER_SIZE - RxQueueReadPos) % RX_BUFFER_SIZE;
|
|
213
|
+}
|
|
214
|
+
|
|
215
|
+void HardwareSerial::flush() {
|
|
216
|
+ RxQueueWritePos = 0;
|
|
217
|
+ RxQueueReadPos = 0;
|
|
218
|
+}
|
|
219
|
+
|
|
220
|
+void HardwareSerial::printf(const char *format, ...) {
|
|
221
|
+ char RxBuffer[256];
|
|
222
|
+ va_list vArgs;
|
|
223
|
+ va_start(vArgs, format);
|
|
224
|
+ int length = vsnprintf(RxBuffer, 256, format, vArgs);
|
|
225
|
+ va_end(vArgs);
|
|
226
|
+ if (length > 0 && length < 256) {
|
|
227
|
+ for (int i = 0; i < length; ++i)
|
|
228
|
+ write(RxBuffer[i]);
|
|
229
|
+ }
|
|
230
|
+}
|
|
231
|
+
|
|
232
|
+void HardwareSerial::IRQHandler() {
|
|
233
|
+ uint32_t IIRValue;
|
|
234
|
+ uint8_t LSRValue, byte;
|
349
|
235
|
|
350
|
|
- IIRValue = LPC_UART0->IIR;
|
|
236
|
+ IIRValue = UART_GetIntId(UARTx);
|
|
237
|
+ IIRValue &= UART_IIR_INTID_MASK; /* check bit 1~3, interrupt identification */
|
351
|
238
|
|
352
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
353
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
354
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
|
239
|
+ if ( IIRValue == UART_IIR_INTID_RLS ) /* Receive Line Status */
|
355
|
240
|
{
|
356
|
|
- LSRValue = LPC_UART0->LSR;
|
|
241
|
+ LSRValue = UART_GetLineStatus(UARTx);
|
|
242
|
+
|
357
|
243
|
/* Receive Line Status */
|
358
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
|
244
|
+ if ( LSRValue & (UART_LSR_OE|UART_LSR_PE|UART_LSR_FE|UART_LSR_RXFE|UART_LSR_BI) )
|
359
|
245
|
{
|
360
|
246
|
/* There are errors or break interrupt */
|
361
|
247
|
/* Read LSR will clear the interrupt */
|
362
|
|
- UART0Status = LSRValue;
|
363
|
|
- dummy = LPC_UART0->RBR; /* Dummy read on RX to clear
|
364
|
|
- interrupt, then bail out */
|
|
248
|
+ Status = LSRValue;
|
|
249
|
+ byte = UART_ReceiveByte(UARTx); /* Dummy read on RX to clear
|
|
250
|
+ interrupt, then bail out */
|
365
|
251
|
return;
|
366
|
252
|
}
|
367
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
368
|
|
- {
|
369
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
370
|
|
- /* Note: read RBR will clear the interrupt */
|
371
|
|
- if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
|
|
253
|
+ }
|
|
254
|
+
|
|
255
|
+ if ( IIRValue == UART_IIR_INTID_RDA ) /* Receive Data Available */
|
|
256
|
+ {
|
|
257
|
+ /* Clear the FIFO */
|
|
258
|
+ while ( UART_Receive(UARTx, &byte, 1, NONE_BLOCKING) ) {
|
|
259
|
+ if ((RxQueueWritePos+1) % RX_BUFFER_SIZE != RxQueueReadPos)
|
372
|
260
|
{
|
373
|
|
- UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
|
374
|
|
- UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
|
261
|
+ RxBuffer[RxQueueWritePos] = byte;
|
|
262
|
+ RxQueueWritePos = (RxQueueWritePos+1) % RX_BUFFER_SIZE;
|
375
|
263
|
}
|
376
|
264
|
else
|
377
|
|
- dummy = LPC_UART0->RBR;
|
|
265
|
+ break;
|
378
|
266
|
}
|
379
|
267
|
}
|
380
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
381
|
|
- {
|
382
|
|
- /* Receive Data Available */
|
383
|
|
- if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
|
384
|
|
- {
|
385
|
|
- UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
|
386
|
|
- UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
387
|
|
- }
|
388
|
|
- else
|
389
|
|
- dummy = LPC_UART1->RBR;
|
390
|
|
- }
|
391
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
|
268
|
+ else if ( IIRValue == UART_IIR_INTID_CTI ) /* Character timeout indicator */
|
392
|
269
|
{
|
393
|
270
|
/* Character Time-out indicator */
|
394
|
|
- UART0Status |= 0x100; /* Bit 9 as the CTI error */
|
|
271
|
+ Status |= 0x100; /* Bit 9 as the CTI error */
|
395
|
272
|
}
|
396
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
397
|
|
- {
|
398
|
|
- /* THRE interrupt */
|
399
|
|
- LSRValue = LPC_UART0->LSR; /* Check status in the LSR to see if
|
400
|
|
- valid data in U0THR or not */
|
401
|
|
- if ( LSRValue & LSR_THRE )
|
402
|
|
- {
|
403
|
|
- UART0TxEmpty = 1;
|
404
|
|
- }
|
405
|
|
- else
|
406
|
|
- {
|
407
|
|
- UART0TxEmpty = 0;
|
|
273
|
+
|
|
274
|
+ #if TX_BUFFER_SIZE > 0
|
|
275
|
+ if (IIRValue == UART_IIR_INTID_THRE) {
|
|
276
|
+ /* Disable THRE interrupt */
|
|
277
|
+ UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
|
|
278
|
+
|
|
279
|
+ /* Wait for FIFO buffer empty */
|
|
280
|
+ while (UART_CheckBusy(UARTx) == SET);
|
|
281
|
+
|
|
282
|
+ /* Transfer up to UART_TX_FIFO_SIZE bytes of data */
|
|
283
|
+ for (int i = 0; i < UART_TX_FIFO_SIZE && TxQueueWritePos != TxQueueReadPos; i++) {
|
|
284
|
+ /* Move a piece of data into the transmit FIFO */
|
|
285
|
+ if (UART_Send(UARTx, &TxBuffer[TxQueueReadPos], 1, NONE_BLOCKING))
|
|
286
|
+ TxQueueReadPos = (TxQueueReadPos+1) % TX_BUFFER_SIZE;
|
|
287
|
+ else
|
|
288
|
+ break;
|
|
289
|
+ }
|
|
290
|
+
|
|
291
|
+ /* If there is no more data to send, disable the transmit interrupt - else enable it or keep it enabled */
|
|
292
|
+ if (TxQueueWritePos == TxQueueReadPos)
|
|
293
|
+ UART_IntConfig(UARTx, UART_INTCFG_THRE, DISABLE);
|
|
294
|
+ else
|
|
295
|
+ UART_IntConfig(UARTx, UART_INTCFG_THRE, ENABLE);
|
408
|
296
|
}
|
409
|
|
- }
|
|
297
|
+ #endif
|
|
298
|
+}
|
|
299
|
+
|
|
300
|
+#ifdef __cplusplus
|
|
301
|
+extern "C" {
|
|
302
|
+#endif
|
|
303
|
+
|
|
304
|
+/*****************************************************************************
|
|
305
|
+** Function name: UART0_IRQHandler
|
|
306
|
+**
|
|
307
|
+** Descriptions: UART0 interrupt handler
|
|
308
|
+**
|
|
309
|
+** parameters: None
|
|
310
|
+** Returned value: None
|
|
311
|
+**
|
|
312
|
+*****************************************************************************/
|
|
313
|
+void UART0_IRQHandler (void)
|
|
314
|
+{
|
|
315
|
+ Serial.IRQHandler();
|
410
|
316
|
}
|
411
|
317
|
|
412
|
318
|
/*****************************************************************************
|
|
@@ -420,69 +326,9 @@ void UART0_IRQHandler (void)
|
420
|
326
|
*****************************************************************************/
|
421
|
327
|
void UART1_IRQHandler (void)
|
422
|
328
|
{
|
423
|
|
- uint8_t IIRValue, LSRValue;
|
424
|
|
-
|
425
|
|
- IIRValue = LPC_UART1->IIR;
|
426
|
|
-
|
427
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
428
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
429
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
430
|
|
- {
|
431
|
|
- LSRValue = LPC_UART1->LSR;
|
432
|
|
- /* Receive Line Status */
|
433
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
434
|
|
- {
|
435
|
|
- /* There are errors or break interrupt */
|
436
|
|
- /* Read LSR will clear the interrupt */
|
437
|
|
- UART1Status = LSRValue;
|
438
|
|
- dummy = LPC_UART1->RBR; /* Dummy read on RX to clear
|
439
|
|
- interrupt, then bail out */
|
440
|
|
- return;
|
441
|
|
- }
|
442
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
443
|
|
- {
|
444
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
445
|
|
- /* Note: read RBR will clear the interrupt */
|
446
|
|
- if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
|
447
|
|
- {
|
448
|
|
- UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
|
449
|
|
- UART1RxQueueWritePos =(UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
450
|
|
- }
|
451
|
|
- else
|
452
|
|
- dummy = LPC_UART1->RBR;
|
453
|
|
- }
|
454
|
|
- }
|
455
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
456
|
|
- {
|
457
|
|
- /* Receive Data Available */
|
458
|
|
- if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
|
459
|
|
- {
|
460
|
|
- UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
|
461
|
|
- UART1RxQueueWritePos = (UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
462
|
|
- }
|
463
|
|
- else
|
464
|
|
- dummy = LPC_UART1->RBR;
|
465
|
|
- }
|
466
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
467
|
|
- {
|
468
|
|
- /* Character Time-out indicator */
|
469
|
|
- UART1Status |= 0x100; /* Bit 9 as the CTI error */
|
470
|
|
- }
|
471
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
472
|
|
- {
|
473
|
|
- /* THRE interrupt */
|
474
|
|
- LSRValue = LPC_UART1->LSR; /* Check status in the LSR to see if
|
475
|
|
- valid data in U0THR or not */
|
476
|
|
- if ( LSRValue & LSR_THRE )
|
477
|
|
- {
|
478
|
|
- UART1TxEmpty = 1;
|
479
|
|
- }
|
480
|
|
- else
|
481
|
|
- {
|
482
|
|
- UART1TxEmpty = 0;
|
483
|
|
- }
|
484
|
|
- }
|
|
329
|
+ Serial1.IRQHandler();
|
485
|
330
|
}
|
|
331
|
+
|
486
|
332
|
/*****************************************************************************
|
487
|
333
|
** Function name: UART2_IRQHandler
|
488
|
334
|
**
|
|
@@ -494,71 +340,13 @@ void UART1_IRQHandler (void)
|
494
|
340
|
*****************************************************************************/
|
495
|
341
|
void UART2_IRQHandler (void)
|
496
|
342
|
{
|
497
|
|
- uint8_t IIRValue, LSRValue;
|
498
|
|
-
|
499
|
|
- IIRValue = LPC_UART2->IIR;
|
500
|
|
-
|
501
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
502
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
503
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
504
|
|
- {
|
505
|
|
- LSRValue = LPC_UART2->LSR;
|
506
|
|
- /* Receive Line Status */
|
507
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
508
|
|
- {
|
509
|
|
- /* There are errors or break interrupt */
|
510
|
|
- /* Read LSR will clear the interrupt */
|
511
|
|
- UART2Status = LSRValue;
|
512
|
|
- dummy = LPC_UART2->RBR; /* Dummy read on RX to clear
|
513
|
|
- interrupt, then bail out */
|
514
|
|
- return;
|
515
|
|
- }
|
516
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
517
|
|
- {
|
518
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
519
|
|
- /* Note: read RBR will clear the interrupt */
|
520
|
|
- if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
|
521
|
|
- {
|
522
|
|
- UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
|
523
|
|
- UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
524
|
|
- }
|
525
|
|
- }
|
526
|
|
- }
|
527
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
528
|
|
- {
|
529
|
|
- /* Receive Data Available */
|
530
|
|
- if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
|
531
|
|
- {
|
532
|
|
- UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
|
533
|
|
- UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
534
|
|
- }
|
535
|
|
- else
|
536
|
|
- dummy = LPC_UART2->RBR;
|
537
|
|
- }
|
538
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
539
|
|
- {
|
540
|
|
- /* Character Time-out indicator */
|
541
|
|
- UART2Status |= 0x100; /* Bit 9 as the CTI error */
|
542
|
|
- }
|
543
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
544
|
|
- {
|
545
|
|
- /* THRE interrupt */
|
546
|
|
- LSRValue = LPC_UART2->LSR; /* Check status in the LSR to see if
|
547
|
|
- valid data in U0THR or not */
|
548
|
|
- if ( LSRValue & LSR_THRE )
|
549
|
|
- {
|
550
|
|
- UART2TxEmpty = 1;
|
551
|
|
- }
|
552
|
|
- else
|
553
|
|
- {
|
554
|
|
- UART2TxEmpty = 0;
|
555
|
|
- }
|
556
|
|
- }
|
|
343
|
+ Serial2.IRQHandler();
|
557
|
344
|
}
|
|
345
|
+
|
558
|
346
|
/*****************************************************************************
|
559
|
347
|
** Function name: UART3_IRQHandler
|
560
|
348
|
**
|
561
|
|
-** Descriptions: UART0 interrupt handler
|
|
349
|
+** Descriptions: UART3 interrupt handler
|
562
|
350
|
**
|
563
|
351
|
** parameters: None
|
564
|
352
|
** Returned value: None
|
|
@@ -566,66 +354,7 @@ void UART2_IRQHandler (void)
|
566
|
354
|
*****************************************************************************/
|
567
|
355
|
void UART3_IRQHandler (void)
|
568
|
356
|
{
|
569
|
|
- uint8_t IIRValue, LSRValue;
|
570
|
|
-
|
571
|
|
- IIRValue = LPC_UART3->IIR;
|
572
|
|
-
|
573
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
574
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
575
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
576
|
|
- {
|
577
|
|
- LSRValue = LPC_UART3->LSR;
|
578
|
|
- /* Receive Line Status */
|
579
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
580
|
|
- {
|
581
|
|
- /* There are errors or break interrupt */
|
582
|
|
- /* Read LSR will clear the interrupt */
|
583
|
|
- UART3Status = LSRValue;
|
584
|
|
- dummy = LPC_UART3->RBR; /* Dummy read on RX to clear
|
585
|
|
- interrupt, then bail out */
|
586
|
|
- return;
|
587
|
|
- }
|
588
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
589
|
|
- {
|
590
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
591
|
|
- /* Note: read RBR will clear the interrupt */
|
592
|
|
- if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
|
593
|
|
- {
|
594
|
|
- UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
|
595
|
|
- UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
596
|
|
- }
|
597
|
|
- }
|
598
|
|
- }
|
599
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
600
|
|
- {
|
601
|
|
- /* Receive Data Available */
|
602
|
|
- if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
|
603
|
|
- {
|
604
|
|
- UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
|
605
|
|
- UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
606
|
|
- }
|
607
|
|
- else
|
608
|
|
- dummy = LPC_UART3->RBR;
|
609
|
|
- }
|
610
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
611
|
|
- {
|
612
|
|
- /* Character Time-out indicator */
|
613
|
|
- UART3Status |= 0x100; /* Bit 9 as the CTI error */
|
614
|
|
- }
|
615
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
616
|
|
- {
|
617
|
|
- /* THRE interrupt */
|
618
|
|
- LSRValue = LPC_UART3->LSR; /* Check status in the LSR to see if
|
619
|
|
- valid data in U0THR or not */
|
620
|
|
- if ( LSRValue & LSR_THRE )
|
621
|
|
- {
|
622
|
|
- UART3TxEmpty = 1;
|
623
|
|
- }
|
624
|
|
- else
|
625
|
|
- {
|
626
|
|
- UART3TxEmpty = 0;
|
627
|
|
- }
|
628
|
|
- }
|
|
357
|
+ Serial3.IRQHandler();
|
629
|
358
|
}
|
630
|
359
|
|
631
|
360
|
#ifdef __cplusplus
|