Browse Source

FYSETC Cheetah 2.0 (#20897)

George Fu 3 years ago
parent
commit
5ac08a44c6
No account linked to committer's email address

+ 3
- 1
Marlin/src/HAL/STM32/eeprom_flash.cpp View File

@@ -61,7 +61,9 @@
61 61
     #define FLASH_UNIT_SIZE       0x20000 // 128kB
62 62
   #endif
63 63
 
64
-  #define FLASH_ADDRESS_START     (FLASH_END - ((FLASH_SECTOR_TOTAL - (FLASH_SECTOR)) * (FLASH_UNIT_SIZE)) + 1)
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+  #ifndef FLASH_ADDRESS_START
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+    #define FLASH_ADDRESS_START   (FLASH_END - ((FLASH_SECTOR_TOTAL - (FLASH_SECTOR)) * (FLASH_UNIT_SIZE)) + 1)
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+  #endif
65 67
   #define FLASH_ADDRESS_END       (FLASH_ADDRESS_START + FLASH_UNIT_SIZE  - 1)
66 68
 
67 69
   #define EEPROM_SLOTS            ((FLASH_UNIT_SIZE) / (MARLIN_EEPROM_SIZE))

+ 1
- 0
Marlin/src/core/boards.h View File

@@ -373,6 +373,7 @@
373 373
 #define BOARD_MKS_ROBIN_NANO_V3       4220  // MKS Robin Nano V3 (STM32F407VG)
374 374
 #define BOARD_ANET_ET4                4221  // ANET ET4 V1.x (STM32F407VGT6)
375 375
 #define BOARD_ANET_ET4P               4222  // ANET ET4P V1.x (STM32F407VGT6)
376
+#define BOARD_FYSETC_CHEETAH_V20      4223  // FYSETC Cheetah V2.0
376 377
 
377 378
 //
378 379
 // ARM Cortex M7

+ 2
- 0
Marlin/src/pins/pins.h View File

@@ -604,6 +604,8 @@
604 604
   #include "stm32f4/pins_ANET_ET4.h"            // STM32F4                                env:Anet_ET4_OpenBLT
605 605
 #elif MB(ANET_ET4P)
606 606
   #include "stm32f4/pins_ANET_ET4P.h"           // STM32F4                                env:Anet_ET4_OpenBLT
607
+#elif MB(FYSETC_CHEETAH_V20)
608
+  #include "stm32f4/pins_FYSETC_CHEETAH_V20.h"  // STM32F4                                env:FYSETC_CHEETAH_V20
607 609
 
608 610
 //
609 611
 // ARM Cortex M7

+ 271
- 0
Marlin/src/pins/stm32f4/pins_FYSETC_CHEETAH_V20.h View File

@@ -0,0 +1,271 @@
1
+/**
2
+ * Marlin 3D Printer Firmware
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+ * Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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+ *
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+ * Based on Sprinter and grbl.
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+ * Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
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+ *
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+ * This program is free software: you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
10
+ * the Free Software Foundation, either version 3 of the License, or
11
+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
19
+ * along with this program.  If not, see <https://www.gnu.org/licenses/>.
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+ *
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+ */
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+#pragma once
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+
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+#if NOT_TARGET(STM32F4)
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+  #error "Oops! Select an STM32F4 board in 'Tools > Board.'"
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+#endif
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+
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+#define DEFAULT_MACHINE_NAME "3D Printer"
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+
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+#define BOARD_INFO_NAME   "FYSETC Cheetah V2.0"
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+#define BOARD_WEBSITE_URL "fysetc.com"
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+
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+// USB Flash Drive support
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+//#define HAS_OTG_USB_HOST_SUPPORT
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+
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+// Ignore temp readings during development.
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+//#define BOGUS_TEMPERATURE_GRACE_PERIOD    2000
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+
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+#if EITHER(NO_EEPROM_SELECTED, FLASH_EEPROM_EMULATION)
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+  #define FLASH_EEPROM_EMULATION
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+  #define FLASH_EEPROM_LEVELING
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+
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+  #define FLASH_SECTOR          2
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+  #define FLASH_UNIT_SIZE       0x4000      // 16k
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+  #define FLASH_ADDRESS_START   0x8008000
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+#endif
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+
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+//
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+// Z Probe
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+//
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+#if ENABLED(BLTOUCH)
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+  #error "You need to set jumper to 5v for Bltouch, then comment out this line to proceed."
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+  #define SERVO0_PIN                        PA0
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+#elif !defined(Z_MIN_PROBE_PIN)
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+  #define Z_MIN_PROBE_PIN                   PA0
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+#endif
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+
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+//
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+// Limit Switches
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+//
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+#define X_STOP_PIN                          PB4
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+#define Y_STOP_PIN                          PB3
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+#define Z_STOP_PIN                          PB1
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+
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+//
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+// Filament runout
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+//
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+#define FIL_RUNOUT_PIN                      PB5
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+
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+//
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+// Steppers
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+//
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+#define X_STEP_PIN                          PC0
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+#define X_DIR_PIN                           PC1
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+#define X_ENABLE_PIN                        PA8
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+
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+#define Y_STEP_PIN                          PC14
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+#define Y_DIR_PIN                           PC13
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+#define Y_ENABLE_PIN                        PC15
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+
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+#define Z_STEP_PIN                          PB9
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+#define Z_DIR_PIN                           PB8
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+#define Z_ENABLE_PIN                        PC2
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+
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+#define E0_STEP_PIN                         PB2
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+#define E0_DIR_PIN                          PA15
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+#define E0_ENABLE_PIN                       PD2
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+
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+#if HAS_TMC_UART
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+  #define X_HARDWARE_SERIAL  Serial2
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+  #define Y_HARDWARE_SERIAL  Serial2
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+  #define Z_HARDWARE_SERIAL  Serial2
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+  #define E0_HARDWARE_SERIAL Serial2
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+
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+  // Default TMC slave addresses
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+  #ifndef X_SLAVE_ADDRESS
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+    #define X_SLAVE_ADDRESS  0
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+  #endif
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+  #ifndef Y_SLAVE_ADDRESS
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+    #define Y_SLAVE_ADDRESS  2
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+  #endif
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+  #ifndef Z_SLAVE_ADDRESS
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+    #define Z_SLAVE_ADDRESS  1
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+  #endif
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+  #ifndef E0_SLAVE_ADDRESS
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+    #define E0_SLAVE_ADDRESS 3
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+  #endif
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+#endif
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+
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+//
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+// Heaters / Fans
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+//
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+#define HEATER_0_PIN                        PC6
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+#define HEATER_BED_PIN                      PC7
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+#ifndef FAN_PIN
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+  #define FAN_PIN                           PA1
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+#endif
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+#define FAN1_PIN                            PC8
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+
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+//
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+// Temperature Sensors
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+//
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+#define TEMP_BED_PIN                        PC5   // Analog Input
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+#define TEMP_0_PIN                          PC4   // Analog Input
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+
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+//
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+// Misc. Functions
128
+//
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+#define SDSS                                PA4
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+#define SD_DETECT_PIN                       PC3
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+
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+#ifndef RGB_LED_R_PIN
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+  #define RGB_LED_R_PIN                     PB0
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+#endif
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+#ifndef RGB_LED_G_PIN
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+  #define RGB_LED_G_PIN                     PB7
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+#endif
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+#ifndef RGB_LED_B_PIN
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+  #define RGB_LED_B_PIN                     PB6
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+#endif
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+
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+/**
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+ *                _____                                              _____
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+ *            5V | 1 2 | GND                                     5V | 1 2 | GND
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+ *         RESET | 3 4 | PC3  (SD_DETECT)             (LCD_D7)  PB7 | 3 4 | PB6  (LCD_D6)
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+ * (SD_MOSI) PA7   5 6 | PC11 (BTN_EN2)               (LCD_D5) PB14   5 6 | PB13 (LCD_D4)
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+ *   (SD_SS) PA4 | 7 8 | PC10 (BTN_EN1)               (LCD_RS) PB12 | 7 8 | PB15 (LCD_EN)
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+ *  (SD_SCK) PA5 | 9 10| PA6  (SD_MISO)              (BTN_ENC) PC12 | 9 10| PC9  (BEEPER)
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+ *                -----                                              -----
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+ *                EXP2                                               EXP1
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+ */
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+
153
+/**
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+*                 _____
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+*  (BEEPER) PC9  | 1 2 | PC12 (BTN_ENC)
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+* (BTN_EN1) PC10 | 3 4 | PB14 (LCD_D5/MISO)
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+* (BTN_EN2) PC11   5 6 | PB13 (LCD_D4/SCK)
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+*  (LCD_RS) PB12 | 7 8 | PB15 (LCD_EN/MOSI)
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+*            GND | 9 10| 5V
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+*                 -----
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+*                 EXP3
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+*/
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+
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+#define EXPA1_03_PIN                        PB7
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+#define EXPA1_04_PIN                        PB6
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+#define EXPA1_05_PIN                        PB14
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+#define EXPA1_06_PIN                        PB13
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+#define EXPA1_07_PIN                        PB12
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+#define EXPA1_08_PIN                        PB15
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+#define EXPA1_09_PIN                        PC12
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+#define EXPA1_10_PIN                        PC9
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+
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+#define EXPA2_03_PIN                        -1
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+#define EXPA2_04_PIN                        PC3
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+#define EXPA2_05_PIN                        PA7
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+#define EXPA2_06_PIN                        PC11
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+#define EXPA2_07_PIN                        PA4
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+#define EXPA2_08_PIN                        PC10
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+#define EXPA2_09_PIN                        PA5
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+#define EXPA2_10_PIN                        PA6
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+
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+#if HAS_WIRED_LCD
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+
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+  #define BEEPER_PIN                EXPA1_10_PIN
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+  #define BTN_ENC                   EXPA1_09_PIN
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+
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+  #if ENABLED(CR10_STOCKDISPLAY)
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+
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+    #define LCD_PINS_RS             EXPA1_07_PIN
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+
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+    #define BTN_EN1                 EXPA2_08_PIN
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+    #define BTN_EN2                 EXPA2_06_PIN
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+
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+    #define LCD_PINS_ENABLE         EXPA1_08_PIN
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+    #define LCD_PINS_D4             EXPA1_06_PIN
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+
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+    // CR10_STOCKDISPLAY default timing is too fast
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+    #undef BOARD_ST7920_DELAY_1
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+    #undef BOARD_ST7920_DELAY_2
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+    #undef BOARD_ST7920_DELAY_3
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+
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+  #elif ENABLED(MKS_MINI_12864)
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+
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+    #define DOGLCD_A0               EXPA1_04_PIN
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+    #define DOGLCD_CS               EXPA1_05_PIN
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+    #define BTN_EN1                 EXPA2_08_PIN
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+    #define BTN_EN2                 EXPA2_06_PIN
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+
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+  #else
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+
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+    #define LCD_PINS_RS             EXPA1_07_PIN
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+
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+    #define BTN_EN1                 EXPA2_06_PIN
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+    #define BTN_EN2                 EXPA2_08_PIN
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+
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+    #define LCD_PINS_ENABLE         EXPA1_08_PIN
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+    #define LCD_PINS_D4             EXPA1_06_PIN
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+
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+    #if ENABLED(FYSETC_MINI_12864)
220
+      #define DOGLCD_CS             EXPA1_08_PIN
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+      #define DOGLCD_A0             EXPA1_07_PIN
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+      //#define LCD_BACKLIGHT_PIN           -1
223
+      #define LCD_RESET_PIN         EXPA1_06_PIN  // Must be high or open for LCD to operate normally.
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+      #if EITHER(FYSETC_MINI_12864_1_2, FYSETC_MINI_12864_2_0)
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+        #ifndef RGB_LED_R_PIN
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+          #define RGB_LED_R_PIN     EXPA1_05_PIN
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+        #endif
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+        #ifndef RGB_LED_G_PIN
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+          #define RGB_LED_G_PIN     EXPA1_04_PIN
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+        #endif
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+        #ifndef RGB_LED_B_PIN
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+          #define RGB_LED_B_PIN     EXPA1_03_PIN
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+        #endif
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+      #elif ENABLED(FYSETC_MINI_12864_2_1)
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+        #define NEOPIXEL_PIN        EXPA1_05_PIN
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+      #endif
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+    #endif // !FYSETC_MINI_12864
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+
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+    #if IS_ULTIPANEL
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+      #define LCD_PINS_D5           EXPA1_05_PIN
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+      #define LCD_PINS_D6           EXPA1_04_PIN
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+      #define LCD_PINS_D7           EXPA1_03_PIN
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+
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+      #if ENABLED(REPRAP_DISCOUNT_FULL_GRAPHIC_SMART_CONTROLLER)
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+        #define BTN_ENC_EN           LCD_PINS_D7  // Detect the presence of the encoder
246
+      #endif
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+
248
+    #endif
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+
250
+  #endif
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+
252
+#endif // HAS_WIRED_LCD
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+
254
+// Alter timing for graphical display
255
+#if HAS_MARLINUI_U8GLIB
256
+  #ifndef BOARD_ST7920_DELAY_1
257
+    #define BOARD_ST7920_DELAY_1    DELAY_NS(96)
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+  #endif
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+  #ifndef BOARD_ST7920_DELAY_2
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+    #define BOARD_ST7920_DELAY_2    DELAY_NS(48)
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+  #endif
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+  #ifndef BOARD_ST7920_DELAY_3
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+    #define BOARD_ST7920_DELAY_3    DELAY_NS(600)
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+  #endif
265
+#endif
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+
267
+#if ENABLED(TOUCH_UI_FTDI_EVE)
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+  #define BEEPER_PIN                EXPA1_10_PIN
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+  #define CLCD_MOD_RESET            EXPA2_08_PIN
270
+  #define CLCD_SPI_CS               EXPA2_06_PIN
271
+#endif

+ 66
- 0
buildroot/share/PlatformIO/boards/FYSETC_CHEETAH_V20.json View File

@@ -0,0 +1,66 @@
1
+{
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+  "build": {
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+    "core": "stm32",
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+    "cpu": "cortex-m4",
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+    "extra_flags": "-DSTM32F401xx",
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+    "f_cpu": "84000000L",
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+    "hwids": [
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+      [
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+        "0x1EAF",
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+        "0x0003"
11
+      ],
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+      [
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+        "0x0483",
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+        "0x3748"
15
+      ]
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+    ],
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+    "ldscript": "stm32f401rc.ld",
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+    "mcu": "stm32f401rct6",
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+    "variant": "FYSETC_CHEETAH_V20"
20
+  },
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+  "debug": {
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+    "jlink_device": "STM32F401RC",
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+    "openocd_target": "stm32f4x",
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+    "svd_path": "STM32F40x.svd",
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+    "tools": {
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+      "stlink": {
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+        "server": {
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+          "arguments": [
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+            "-f",
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+            "scripts/interface/stlink.cfg",
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+            "-c",
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+            "transport select hla_swd",
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+            "-f",
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+            "scripts/target/stm32f4x.cfg",
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+            "-c",
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+            "reset_config none"
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+          ],
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+          "executable": "bin/openocd",
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+          "package": "tool-openocd"
40
+        }
41
+      }
42
+    }
43
+  },
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+  "frameworks": [
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+    "arduino",
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+    "stm32cube"
47
+  ],
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+  "name": "STM32F401RC (64k RAM. 256k Flash)",
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+  "upload": {
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+    "disable_flushing": false,
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+    "maximum_ram_size": 65536,
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+    "maximum_size": 262144,
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+    "protocol": "stlink",
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+    "protocols": [
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+      "stlink",
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+      "dfu",
57
+      "jlink"
58
+    ],
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+	"offset_address": "0x800C000",
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+    "require_upload_port": true,
61
+    "use_1200bps_touch": false,
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+    "wait_for_upload_port": false
63
+  },
64
+  "url": "https://www.fysetc.com",
65
+  "vendor": "Generic"
66
+}

+ 9
- 0
buildroot/share/PlatformIO/scripts/fysetc_cheetah_v20.py View File

@@ -0,0 +1,9 @@
1
+import os
2
+Import("env")
3
+
4
+custom_ld_script = os.path.abspath("buildroot/share/PlatformIO/variants/FYSETC_CHEETAH_V20/ldscript.ld")
5
+for i, flag in enumerate(env["LINKFLAGS"]):
6
+    if "-Wl,-T" in flag:
7
+        env["LINKFLAGS"][i] = "-Wl,-T" + custom_ld_script
8
+    elif flag == "-T":
9
+        env["LINKFLAGS"][i + 1] = custom_ld_script

+ 266
- 0
buildroot/share/PlatformIO/variants/FYSETC_CHEETAH_V20/PeripheralPins.c View File

@@ -0,0 +1,266 @@
1
+/*
2
+ *******************************************************************************
3
+ * Copyright (c) 2019, STMicroelectronics
4
+ * All rights reserved.
5
+ *
6
+ * Redistribution and use in source and binary forms, with or without
7
+ * modification, are permitted provided that the following conditions are met:
8
+ *
9
+ * 1. Redistributions of source code must retain the above copyright notice,
10
+ *    this list of conditions and the following disclaimer.
11
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12
+ *    this list of conditions and the following disclaimer in the documentation
13
+ *    and/or other materials provided with the distribution.
14
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
15
+ *    may be used to endorse or promote products derived from this software
16
+ *    without specific prior written permission.
17
+ *
18
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28
+ *******************************************************************************
29
+ * Automatically generated from STM32F401R[(B-C)|(D-E)]Tx.xml
30
+ */
31
+#include "Arduino.h"
32
+#include "PeripheralPins.h"
33
+
34
+/* =====
35
+ * Note: Commented lines are alternative possibilities which are not used per default.
36
+ *       If you change them, you will have to know what you do
37
+ * =====
38
+ */
39
+
40
+//*** ADC ***
41
+
42
+#ifdef HAL_ADC_MODULE_ENABLED
43
+WEAK const PinMap PinMap_ADC[] = {
44
+  {PA_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
45
+  {PA_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
46
+  {PA_2,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
47
+  {PA_3,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
48
+  {PA_4,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
49
+  {PA_5,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
50
+  {PA_6,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
51
+  {PA_7,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
52
+  {PB_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
53
+  {PB_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
54
+  {PC_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
55
+  {PC_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
56
+  {PC_2,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
57
+  {PC_3,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
58
+  {PC_4,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
59
+  {PC_5,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
60
+  {NC,    NP,    0}
61
+};
62
+#endif
63
+
64
+//*** No DAC ***
65
+
66
+//*** I2C ***
67
+
68
+#ifdef HAL_I2C_MODULE_ENABLED
69
+WEAK const PinMap PinMap_I2C_SDA[] = {
70
+  {PB_3,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
71
+  {PB_4,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
72
+  {PB_7,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
73
+  {PB_9,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
74
+  {PC_9,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
75
+  {NC,    NP,    0}
76
+};
77
+#endif
78
+
79
+#ifdef HAL_I2C_MODULE_ENABLED
80
+WEAK const PinMap PinMap_I2C_SCL[] = {
81
+  {PA_8,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
82
+  {PB_6,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
83
+  {PB_8,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
84
+  {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
85
+  {NC,    NP,    0}
86
+};
87
+#endif
88
+
89
+//*** PWM ***
90
+
91
+#ifdef HAL_TIM_MODULE_ENABLED
92
+WEAK const PinMap PinMap_PWM[] = {
93
+  //  {PA_0,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
94
+  {PA_0,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
95
+  //  {PA_1,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
96
+  {PA_1,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
97
+  //  {PA_2,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
98
+  {PA_2,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
99
+  //  {PA_2,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
100
+  //  {PA_3,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
101
+  {PA_3,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
102
+  //  {PA_3,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
103
+  {PA_5,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
104
+  {PA_6,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
105
+  //  {PA_7,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
106
+  {PA_7,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
107
+  {PA_8,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
108
+  {PA_9,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
109
+  {PA_10, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
110
+  {PA_11, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
111
+  {PA_15, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
112
+  //  {PB_0,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
113
+  {PB_0,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
114
+  //  {PB_1,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
115
+  {PB_1,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
116
+  {PB_3,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
117
+  {PB_4,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
118
+  {PB_5,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
119
+  {PB_6,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
120
+  {PB_7,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
121
+  {PB_8,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
122
+  //  {PB_8,  TIM10,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
123
+  {PB_9,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
124
+  //  {PB_9,  TIM11,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
125
+  {PB_10, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
126
+  {PB_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
127
+  {PB_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
128
+  {PB_15, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
129
+  {PC_6,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
130
+  {PC_7,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
131
+  {PC_8,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
132
+  {PC_9,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
133
+  {NC,    NP,    0}
134
+};
135
+#endif
136
+
137
+//*** SERIAL ***
138
+
139
+#ifdef HAL_UART_MODULE_ENABLED
140
+WEAK const PinMap PinMap_UART_TX[] = {
141
+  {PA_2,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
142
+  {PA_9,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
143
+  {PA_11, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
144
+  {PB_6,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
145
+  {PC_6,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
146
+  {NC,    NP,    0}
147
+};
148
+#endif
149
+
150
+#ifdef HAL_UART_MODULE_ENABLED
151
+WEAK const PinMap PinMap_UART_RX[] = {
152
+  {PA_3,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
153
+  {PA_10, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
154
+  {PA_12, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
155
+  {PB_7,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
156
+  {PC_7,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
157
+  {NC,    NP,    0}
158
+};
159
+#endif
160
+
161
+#ifdef HAL_UART_MODULE_ENABLED
162
+WEAK const PinMap PinMap_UART_RTS[] = {
163
+  {PA_1,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
164
+  {PA_12, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
165
+  {NC,    NP,    0}
166
+};
167
+#endif
168
+
169
+#ifdef HAL_UART_MODULE_ENABLED
170
+WEAK const PinMap PinMap_UART_CTS[] = {
171
+  {PA_0,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
172
+  {PA_11, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
173
+  {NC,    NP,    0}
174
+};
175
+#endif
176
+
177
+//*** SPI ***
178
+
179
+#ifdef HAL_SPI_MODULE_ENABLED
180
+WEAK const PinMap PinMap_SPI_MOSI[] = {
181
+  {PA_7,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
182
+  //  {PB_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
183
+  {PB_5,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
184
+  {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
185
+  {PC_3,  SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
186
+  {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
187
+  {NC,    NP,    0}
188
+};
189
+#endif
190
+
191
+#ifdef HAL_SPI_MODULE_ENABLED
192
+WEAK const PinMap PinMap_SPI_MISO[] = {
193
+  {PA_6,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
194
+  //  {PB_4,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
195
+  {PB_4,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
196
+  {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
197
+  {PC_2,  SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
198
+  {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
199
+  {NC,    NP,    0}
200
+};
201
+#endif
202
+
203
+#ifdef HAL_SPI_MODULE_ENABLED
204
+WEAK const PinMap PinMap_SPI_SCLK[] = {
205
+  {PA_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
206
+  //  {PB_3,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
207
+  {PB_3,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
208
+  {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
209
+  {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
210
+  {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
211
+  {NC,    NP,    0}
212
+};
213
+#endif
214
+
215
+#ifdef HAL_SPI_MODULE_ENABLED
216
+WEAK const PinMap PinMap_SPI_SSEL[] = {
217
+  {PA_4,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
218
+  //  {PA_4,  SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
219
+  //  {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
220
+  {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
221
+  {PB_9,  SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
222
+  {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
223
+  {NC,    NP,    0}
224
+};
225
+#endif
226
+
227
+//*** No CAN ***
228
+
229
+//*** No ETHERNET ***
230
+
231
+//*** No QUADSPI ***
232
+
233
+//*** USB ***
234
+
235
+#ifdef HAL_PCD_MODULE_ENABLED
236
+WEAK const PinMap PinMap_USB_OTG_FS[] = {
237
+#ifndef ARDUINO_CoreBoard_F401RC
238
+  {PA_8,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF
239
+  {PA_9,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS
240
+  {PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID
241
+#endif
242
+  {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM
243
+  {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP
244
+  {NC,    NP,    0}
245
+};
246
+#endif
247
+
248
+//*** No USB_OTG_HS ***
249
+
250
+//*** SD ***
251
+
252
+#ifdef HAL_SD_MODULE_ENABLED
253
+WEAK const PinMap PinMap_SD[] = {
254
+  {PB_8,  SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D4
255
+  {PB_9,  SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D5
256
+  {PC_6,  SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D6
257
+  {PC_7,  SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D7
258
+  {PC_8,  SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D0
259
+  {PC_9,  SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D1
260
+  {PC_10, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D2
261
+  {PC_11, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_SDIO)}, // SDIO_D3
262
+  {PC_12, SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO)}, // SDIO_CK
263
+  {PD_2,  SDIO, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_SDIO)}, // SDIO_CMD
264
+  {NC,    NP,    0}
265
+};
266
+#endif

+ 33
- 0
buildroot/share/PlatformIO/variants/FYSETC_CHEETAH_V20/PinNamesVar.h View File

@@ -0,0 +1,33 @@
1
+/* SYS_WKUP */
2
+#ifdef PWR_WAKEUP_PIN1
3
+  SYS_WKUP1 = PA_0,
4
+#endif
5
+#ifdef PWR_WAKEUP_PIN2
6
+  SYS_WKUP2 = NC,
7
+#endif
8
+#ifdef PWR_WAKEUP_PIN3
9
+  SYS_WKUP3 = NC,
10
+#endif
11
+#ifdef PWR_WAKEUP_PIN4
12
+  SYS_WKUP4 = NC,
13
+#endif
14
+#ifdef PWR_WAKEUP_PIN5
15
+  SYS_WKUP5 = NC,
16
+#endif
17
+#ifdef PWR_WAKEUP_PIN6
18
+  SYS_WKUP6 = NC,
19
+#endif
20
+#ifdef PWR_WAKEUP_PIN7
21
+  SYS_WKUP7 = NC,
22
+#endif
23
+#ifdef PWR_WAKEUP_PIN8
24
+  SYS_WKUP8 = NC,
25
+#endif
26
+/* USB */
27
+#ifdef USBCON
28
+  USB_OTG_FS_SOF = PA_8,
29
+  USB_OTG_FS_VBUS = PA_9,
30
+  USB_OTG_FS_ID = PA_10,
31
+  USB_OTG_FS_DM = PA_11,
32
+  USB_OTG_FS_DP = PA_12,
33
+#endif

+ 496
- 0
buildroot/share/PlatformIO/variants/FYSETC_CHEETAH_V20/hal_conf_custom.h View File

@@ -0,0 +1,496 @@
1
+/**
2
+  ******************************************************************************
3
+  * @file    stm32f4xx_hal_conf.h
4
+  * @brief   HAL configuration file.
5
+  ******************************************************************************
6
+  * @attention
7
+  *
8
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
9
+  * All rights reserved.</center></h2>
10
+  *
11
+  * This software component is licensed by ST under BSD 3-Clause license,
12
+  * the "License"; You may not use this file except in compliance with the
13
+  * License. You may obtain a copy of the License at:
14
+  *                        opensource.org/licenses/BSD-3-Clause
15
+  *
16
+  ******************************************************************************
17
+  */
18
+
19
+/* Define to prevent recursive inclusion -------------------------------------*/
20
+#ifndef __STM32F4xx_HAL_CONF_CUSTOM
21
+#define __STM32F4xx_HAL_CONF_CUSTOM
22
+
23
+#ifdef __cplusplus
24
+extern "C" {
25
+#endif
26
+
27
+/* Exported types ------------------------------------------------------------*/
28
+/* Exported constants --------------------------------------------------------*/
29
+
30
+/* ########################## Module Selection ############################## */
31
+ /**
32
+  * @brief This is the list of modules to be used in the HAL driver
33
+  */
34
+#define HAL_MODULE_ENABLED
35
+#define HAL_ADC_MODULE_ENABLED
36
+/* #define HAL_CAN_MODULE_ENABLED   */
37
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
38
+#define HAL_CRC_MODULE_ENABLED
39
+/* #define HAL_CEC_MODULE_ENABLED   */
40
+/* #define HAL_CRYP_MODULE_ENABLED   */
41
+//#define HAL_DAC_MODULE_ENABLED
42
+/* #define HAL_DCMI_MODULE_ENABLED   */
43
+#define HAL_DMA_MODULE_ENABLED
44
+/* #define HAL_DMA2D_MODULE_ENABLED   */
45
+/* #define HAL_ETH_MODULE_ENABLED   */
46
+#define HAL_FLASH_MODULE_ENABLED
47
+/* #define HAL_NAND_MODULE_ENABLED   */
48
+/* #define HAL_NOR_MODULE_ENABLED   */
49
+/* #define HAL_PCCARD_MODULE_ENABLED   */
50
+/* #define HAL_SRAM_MODULE_ENABLED   */
51
+/* #define HAL_SDRAM_MODULE_ENABLED   */
52
+/* #define HAL_HASH_MODULE_ENABLED   */
53
+#define HAL_GPIO_MODULE_ENABLED
54
+/* #define HAL_EXTI_MODULE_ENABLED   */
55
+#define HAL_I2C_MODULE_ENABLED
56
+/* #define HAL_SMBUS_MODULE_ENABLED   */
57
+/* #define HAL_I2S_MODULE_ENABLED   */
58
+#define HAL_IWDG_MODULE_ENABLED
59
+/* #define HAL_LTDC_MODULE_ENABLED   */
60
+/* #define HAL_DSI_MODULE_ENABLED   */
61
+#define HAL_PWR_MODULE_ENABLED
62
+/* #define HAL_QSPI_MODULE_ENABLED   */
63
+#define HAL_RCC_MODULE_ENABLED
64
+/* #define HAL_RNG_MODULE_ENABLED   */
65
+#define HAL_RTC_MODULE_ENABLED
66
+/* #define HAL_SAI_MODULE_ENABLED   */
67
+//#define HAL_SD_MODULE_ENABLED
68
+#define HAL_SPI_MODULE_ENABLED
69
+#define HAL_TIM_MODULE_ENABLED
70
+/* #define HAL_UART_MODULE_ENABLED   */
71
+/* #define HAL_USART_MODULE_ENABLED   */
72
+/* #define HAL_IRDA_MODULE_ENABLED   */
73
+/* #define HAL_SMARTCARD_MODULE_ENABLED   */
74
+/* #define HAL_WWDG_MODULE_ENABLED   */
75
+#define HAL_CORTEX_MODULE_ENABLED
76
+#ifndef HAL_PCD_MODULE_ENABLED
77
+  #define HAL_PCD_MODULE_ENABLED //Since STM32 v3.10700.191028 this is automatically added if any type of USB is enabled (as in Arduino IDE)
78
+#endif
79
+/* #define HAL_HCD_MODULE_ENABLED   */
80
+/* #define HAL_FMPI2C_MODULE_ENABLED   */
81
+/* #define HAL_SPDIFRX_MODULE_ENABLED   */
82
+/* #define HAL_DFSDM_MODULE_ENABLED   */
83
+/* #define HAL_LPTIM_MODULE_ENABLED   */
84
+/* #define HAL_MMC_MODULE_ENABLED   */
85
+
86
+/* ########################## HSE/HSI Values adaptation ##################### */
87
+/**
88
+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
89
+  *        This value is used by the RCC HAL module to compute the system frequency
90
+  *        (when HSE is used as system clock source, directly or through the PLL).
91
+  */
92
+#ifndef HSE_VALUE
93
+#define HSE_VALUE              8000000U /*!< Value of the External oscillator in Hz */
94
+#endif /* HSE_VALUE */
95
+
96
+#ifndef HSE_STARTUP_TIMEOUT
97
+#define HSE_STARTUP_TIMEOUT    100U      /*!< Time out for HSE start up, in ms */
98
+#endif /* HSE_STARTUP_TIMEOUT */
99
+
100
+/**
101
+  * @brief Internal High Speed oscillator (HSI) value.
102
+  *        This value is used by the RCC HAL module to compute the system frequency
103
+  *        (when HSI is used as system clock source, directly or through the PLL).
104
+  */
105
+#ifndef HSI_VALUE
106
+#define HSI_VALUE              16000000U /*!< Value of the Internal oscillator in Hz */
107
+#endif /* HSI_VALUE */
108
+
109
+/**
110
+  * @brief Internal Low Speed oscillator (LSI) value.
111
+  */
112
+#ifndef LSI_VALUE
113
+#define LSI_VALUE               32000U    /*!< LSI Typical Value in Hz */
114
+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz
115
+The real value may vary depending on the variations
116
+in voltage and temperature. */
117
+/**
118
+  * @brief External Low Speed oscillator (LSE) value.
119
+  */
120
+#ifndef LSE_VALUE
121
+#define LSE_VALUE               32768U    /*!< Value of the External Low Speed oscillator in Hz */
122
+#endif /* LSE_VALUE */
123
+
124
+#ifndef LSE_STARTUP_TIMEOUT
125
+#define LSE_STARTUP_TIMEOUT    5000U     /*!< Time out for LSE start up, in ms */
126
+#endif /* LSE_STARTUP_TIMEOUT */
127
+
128
+/**
129
+  * @brief External clock source for I2S peripheral
130
+  *        This value is used by the I2S HAL module to compute the I2S clock source
131
+  *        frequency, this source is inserted directly through I2S_CKIN pad.
132
+  */
133
+#ifndef EXTERNAL_CLOCK_VALUE
134
+#define EXTERNAL_CLOCK_VALUE     12288000U /*!< Value of the External oscillator in Hz*/
135
+#endif /* EXTERNAL_CLOCK_VALUE */
136
+
137
+/* Tip: To avoid modifying this file each time you need to use different HSE,
138
+   ===  you can define the HSE value in your toolchain compiler preprocessor. */
139
+
140
+/* ########################### System Configuration ######################### */
141
+/**
142
+  * @brief This is the HAL system configuration section
143
+  */
144
+#if !defined (VDD_VALUE)
145
+#define  VDD_VALUE                    3300U /*!< Value of VDD in mv */
146
+#endif
147
+#if !defined (TICK_INT_PRIORITY)
148
+#define  TICK_INT_PRIORITY            0x00U /*!< tick interrupt priority */
149
+#endif
150
+#if !defined (USE_RTOS)
151
+#define  USE_RTOS                     0U
152
+#endif
153
+#if !defined (PREFETCH_ENABLE)
154
+#define  PREFETCH_ENABLE              1U
155
+#endif
156
+#if !defined (INSTRUCTION_CACHE_ENABLE)
157
+#define  INSTRUCTION_CACHE_ENABLE     1U
158
+#endif
159
+#if !defined (DATA_CACHE_ENABLE)
160
+#define  DATA_CACHE_ENABLE            1U
161
+#endif
162
+
163
+#define  USE_HAL_ADC_REGISTER_CALLBACKS         0U /* ADC register callback disabled       */
164
+#define  USE_HAL_CAN_REGISTER_CALLBACKS         0U /* CAN register callback disabled       */
165
+#define  USE_HAL_CEC_REGISTER_CALLBACKS         0U /* CEC register callback disabled       */
166
+#define  USE_HAL_CRYP_REGISTER_CALLBACKS        0U /* CRYP register callback disabled      */
167
+#define  USE_HAL_DAC_REGISTER_CALLBACKS         0U /* DAC register callback disabled       */
168
+#define  USE_HAL_DCMI_REGISTER_CALLBACKS        0U /* DCMI register callback disabled      */
169
+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS       0U /* DFSDM register callback disabled     */
170
+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS       0U /* DMA2D register callback disabled     */
171
+#define  USE_HAL_DSI_REGISTER_CALLBACKS         0U /* DSI register callback disabled       */
172
+#define  USE_HAL_ETH_REGISTER_CALLBACKS         0U /* ETH register callback disabled       */
173
+#define  USE_HAL_HASH_REGISTER_CALLBACKS        0U /* HASH register callback disabled      */
174
+#define  USE_HAL_HCD_REGISTER_CALLBACKS         0U /* HCD register callback disabled       */
175
+#define  USE_HAL_I2C_REGISTER_CALLBACKS         0U /* I2C register callback disabled       */
176
+#define  USE_HAL_FMPI2C_REGISTER_CALLBACKS      0U /* FMPI2C register callback disabled    */
177
+#define  USE_HAL_I2S_REGISTER_CALLBACKS         0U /* I2S register callback disabled       */
178
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS        0U /* IRDA register callback disabled      */
179
+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS       0U /* LPTIM register callback disabled     */
180
+#define  USE_HAL_LTDC_REGISTER_CALLBACKS        0U /* LTDC register callback disabled      */
181
+#define  USE_HAL_MMC_REGISTER_CALLBACKS         0U /* MMC register callback disabled       */
182
+#define  USE_HAL_NAND_REGISTER_CALLBACKS        0U /* NAND register callback disabled      */
183
+#define  USE_HAL_NOR_REGISTER_CALLBACKS         0U /* NOR register callback disabled       */
184
+#define  USE_HAL_PCCARD_REGISTER_CALLBACKS      0U /* PCCARD register callback disabled    */
185
+#define  USE_HAL_PCD_REGISTER_CALLBACKS         0U /* PCD register callback disabled       */
186
+#define  USE_HAL_QSPI_REGISTER_CALLBACKS        0U /* QSPI register callback disabled      */
187
+#define  USE_HAL_RNG_REGISTER_CALLBACKS         0U /* RNG register callback disabled       */
188
+#define  USE_HAL_RTC_REGISTER_CALLBACKS         0U /* RTC register callback disabled       */
189
+#define  USE_HAL_SAI_REGISTER_CALLBACKS         0U /* SAI register callback disabled       */
190
+#define  USE_HAL_SD_REGISTER_CALLBACKS          0U /* SD register callback disabled        */
191
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS   0U /* SMARTCARD register callback disabled */
192
+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS       0U /* SDRAM register callback disabled     */
193
+#define  USE_HAL_SRAM_REGISTER_CALLBACKS        0U /* SRAM register callback disabled      */
194
+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS     0U /* SPDIFRX register callback disabled   */
195
+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS       0U /* SMBUS register callback disabled     */
196
+#define  USE_HAL_SPI_REGISTER_CALLBACKS         0U /* SPI register callback disabled       */
197
+#define  USE_HAL_TIM_REGISTER_CALLBACKS         0U /* TIM register callback disabled       */
198
+#define  USE_HAL_UART_REGISTER_CALLBACKS        0U /* UART register callback disabled      */
199
+#define  USE_HAL_USART_REGISTER_CALLBACKS       0U /* USART register callback disabled     */
200
+#define  USE_HAL_WWDG_REGISTER_CALLBACKS        0U /* WWDG register callback disabled      */
201
+
202
+/* ########################## Assert Selection ############################## */
203
+/**
204
+  * @brief Uncomment the line below to expanse the "assert_param" macro in the
205
+  *        HAL drivers code
206
+  */
207
+/* #define USE_FULL_ASSERT    1U */
208
+
209
+/* ################## Ethernet peripheral configuration ##################### */
210
+
211
+/* Section 1 : Ethernet peripheral configuration */
212
+
213
+/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */
214
+#define MAC_ADDR0   2U
215
+#define MAC_ADDR1   0U
216
+#define MAC_ADDR2   0U
217
+#define MAC_ADDR3   0U
218
+#define MAC_ADDR4   0U
219
+#define MAC_ADDR5   0U
220
+
221
+/* Definition of the Ethernet driver buffers size and count */
222
+#define ETH_RX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for receive               */
223
+#define ETH_TX_BUF_SIZE                ETH_MAX_PACKET_SIZE /* buffer size for transmit              */
224
+#define ETH_RXBUFNB                    ((uint32_t)4U)       /* 4 Rx buffers of size ETH_RX_BUF_SIZE  */
225
+#define ETH_TXBUFNB                    ((uint32_t)4U)       /* 4 Tx buffers of size ETH_TX_BUF_SIZE  */
226
+
227
+/* Section 2: PHY configuration section */
228
+
229
+/* DP83848_PHY_ADDRESS Address*/
230
+#define DP83848_PHY_ADDRESS           0x01U
231
+/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/
232
+#define PHY_RESET_DELAY                 0x000000FFU
233
+/* PHY Configuration delay */
234
+#define PHY_CONFIG_DELAY                0x00000FFFU
235
+
236
+#define PHY_READ_TO                     0x0000FFFFU
237
+#define PHY_WRITE_TO                    0x0000FFFFU
238
+
239
+/* Section 3: Common PHY Registers */
240
+
241
+#define PHY_BCR                         ((uint16_t)0x0000)  /*!< Transceiver Basic Control Register   */
242
+#define PHY_BSR                         ((uint16_t)0x0001)  /*!< Transceiver Basic Status Register    */
243
+
244
+#define PHY_RESET                       ((uint16_t)0x8000)  /*!< PHY Reset */
245
+#define PHY_LOOPBACK                    ((uint16_t)0x4000)  /*!< Select loop-back mode */
246
+#define PHY_FULLDUPLEX_100M             ((uint16_t)0x2100)  /*!< Set the full-duplex mode at 100 Mb/s */
247
+#define PHY_HALFDUPLEX_100M             ((uint16_t)0x2000)  /*!< Set the half-duplex mode at 100 Mb/s */
248
+#define PHY_FULLDUPLEX_10M              ((uint16_t)0x0100)  /*!< Set the full-duplex mode at 10 Mb/s  */
249
+#define PHY_HALFDUPLEX_10M              ((uint16_t)0x0000)  /*!< Set the half-duplex mode at 10 Mb/s  */
250
+#define PHY_AUTONEGOTIATION             ((uint16_t)0x1000)  /*!< Enable auto-negotiation function     */
251
+#define PHY_RESTART_AUTONEGOTIATION     ((uint16_t)0x0200)  /*!< Restart auto-negotiation function    */
252
+#define PHY_POWERDOWN                   ((uint16_t)0x0800)  /*!< Select the power down mode           */
253
+#define PHY_ISOLATE                     ((uint16_t)0x0400)  /*!< Isolate PHY from MII                 */
254
+
255
+#define PHY_AUTONEGO_COMPLETE           ((uint16_t)0x0020)  /*!< Auto-Negotiation process completed   */
256
+#define PHY_LINKED_STATUS               ((uint16_t)0x0004)  /*!< Valid link established               */
257
+#define PHY_JABBER_DETECTION            ((uint16_t)0x0002)  /*!< Jabber condition detected            */
258
+
259
+/* Section 4: Extended PHY Registers */
260
+#define PHY_SR                          ((uint16_t)0x10U)    /*!< PHY status register Offset                      */
261
+
262
+#define PHY_SPEED_STATUS                ((uint16_t)0x0002U)  /*!< PHY Speed mask                                  */
263
+#define PHY_DUPLEX_STATUS               ((uint16_t)0x0004U)  /*!< PHY Duplex mask                                 */
264
+
265
+/* ################## SPI peripheral configuration ########################## */
266
+
267
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
268
+ * Activated: CRC code is present inside driver
269
+ * Deactivated: CRC code cleaned from driver
270
+ */
271
+#ifndef USE_SPI_CRC
272
+#define USE_SPI_CRC                     0U
273
+#endif
274
+
275
+/* Includes ------------------------------------------------------------------*/
276
+/**
277
+  * @brief Include module's header file
278
+  */
279
+
280
+#ifdef HAL_RCC_MODULE_ENABLED
281
+#include "stm32f4xx_hal_rcc.h"
282
+#endif /* HAL_RCC_MODULE_ENABLED */
283
+
284
+#ifdef HAL_GPIO_MODULE_ENABLED
285
+#include "stm32f4xx_hal_gpio.h"
286
+#endif /* HAL_GPIO_MODULE_ENABLED */
287
+
288
+#ifdef HAL_EXTI_MODULE_ENABLED
289
+#include "stm32f4xx_hal_exti.h"
290
+#endif /* HAL_EXTI_MODULE_ENABLED */
291
+
292
+#ifdef HAL_DMA_MODULE_ENABLED
293
+#include "stm32f4xx_hal_dma.h"
294
+#endif /* HAL_DMA_MODULE_ENABLED */
295
+
296
+#ifdef HAL_CORTEX_MODULE_ENABLED
297
+#include "stm32f4xx_hal_cortex.h"
298
+#endif /* HAL_CORTEX_MODULE_ENABLED */
299
+
300
+#ifdef HAL_ADC_MODULE_ENABLED
301
+#include "stm32f4xx_hal_adc.h"
302
+#endif /* HAL_ADC_MODULE_ENABLED */
303
+
304
+#ifdef HAL_CAN_MODULE_ENABLED
305
+#include "stm32f4xx_hal_can.h"
306
+#endif /* HAL_CAN_MODULE_ENABLED */
307
+
308
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
309
+#include "stm32f4xx_hal_can_legacy.h"
310
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
311
+
312
+#ifdef HAL_CRC_MODULE_ENABLED
313
+#include "stm32f4xx_hal_crc.h"
314
+#endif /* HAL_CRC_MODULE_ENABLED */
315
+
316
+#ifdef HAL_CRYP_MODULE_ENABLED
317
+#include "stm32f4xx_hal_cryp.h"
318
+#endif /* HAL_CRYP_MODULE_ENABLED */
319
+
320
+#ifdef HAL_DMA2D_MODULE_ENABLED
321
+#include "stm32f4xx_hal_dma2d.h"
322
+#endif /* HAL_DMA2D_MODULE_ENABLED */
323
+
324
+#ifdef HAL_DAC_MODULE_ENABLED
325
+#include "stm32f4xx_hal_dac.h"
326
+#endif /* HAL_DAC_MODULE_ENABLED */
327
+
328
+#ifdef HAL_DCMI_MODULE_ENABLED
329
+#include "stm32f4xx_hal_dcmi.h"
330
+#endif /* HAL_DCMI_MODULE_ENABLED */
331
+
332
+#ifdef HAL_ETH_MODULE_ENABLED
333
+#include "stm32f4xx_hal_eth.h"
334
+#endif /* HAL_ETH_MODULE_ENABLED */
335
+
336
+#ifdef HAL_FLASH_MODULE_ENABLED
337
+#include "stm32f4xx_hal_flash.h"
338
+#endif /* HAL_FLASH_MODULE_ENABLED */
339
+
340
+#ifdef HAL_SRAM_MODULE_ENABLED
341
+#include "stm32f4xx_hal_sram.h"
342
+#endif /* HAL_SRAM_MODULE_ENABLED */
343
+
344
+#ifdef HAL_NOR_MODULE_ENABLED
345
+#include "stm32f4xx_hal_nor.h"
346
+#endif /* HAL_NOR_MODULE_ENABLED */
347
+
348
+#ifdef HAL_NAND_MODULE_ENABLED
349
+#include "stm32f4xx_hal_nand.h"
350
+#endif /* HAL_NAND_MODULE_ENABLED */
351
+
352
+#ifdef HAL_PCCARD_MODULE_ENABLED
353
+#include "stm32f4xx_hal_pccard.h"
354
+#endif /* HAL_PCCARD_MODULE_ENABLED */
355
+
356
+#ifdef HAL_SDRAM_MODULE_ENABLED
357
+#include "stm32f4xx_hal_sdram.h"
358
+#endif /* HAL_SDRAM_MODULE_ENABLED */
359
+
360
+#ifdef HAL_HASH_MODULE_ENABLED
361
+#include "stm32f4xx_hal_hash.h"
362
+#endif /* HAL_HASH_MODULE_ENABLED */
363
+
364
+#ifdef HAL_I2C_MODULE_ENABLED
365
+#include "stm32f4xx_hal_i2c.h"
366
+#endif /* HAL_I2C_MODULE_ENABLED */
367
+
368
+#ifdef HAL_SMBUS_MODULE_ENABLED
369
+#include "stm32f4xx_hal_smbus.h"
370
+#endif /* HAL_SMBUS_MODULE_ENABLED */
371
+
372
+#ifdef HAL_I2S_MODULE_ENABLED
373
+#include "stm32f4xx_hal_i2s.h"
374
+#endif /* HAL_I2S_MODULE_ENABLED */
375
+
376
+#ifdef HAL_IWDG_MODULE_ENABLED
377
+#include "stm32f4xx_hal_iwdg.h"
378
+#endif /* HAL_IWDG_MODULE_ENABLED */
379
+
380
+#ifdef HAL_LTDC_MODULE_ENABLED
381
+#include "stm32f4xx_hal_ltdc.h"
382
+#endif /* HAL_LTDC_MODULE_ENABLED */
383
+
384
+#ifdef HAL_PWR_MODULE_ENABLED
385
+#include "stm32f4xx_hal_pwr.h"
386
+#endif /* HAL_PWR_MODULE_ENABLED */
387
+
388
+#ifdef HAL_RNG_MODULE_ENABLED
389
+#include "stm32f4xx_hal_rng.h"
390
+#endif /* HAL_RNG_MODULE_ENABLED */
391
+
392
+#ifdef HAL_RTC_MODULE_ENABLED
393
+#include "stm32f4xx_hal_rtc.h"
394
+#endif /* HAL_RTC_MODULE_ENABLED */
395
+
396
+#ifdef HAL_SAI_MODULE_ENABLED
397
+#include "stm32f4xx_hal_sai.h"
398
+#endif /* HAL_SAI_MODULE_ENABLED */
399
+
400
+#ifdef HAL_SD_MODULE_ENABLED
401
+#include "stm32f4xx_hal_sd.h"
402
+#endif /* HAL_SD_MODULE_ENABLED */
403
+
404
+#ifdef HAL_SPI_MODULE_ENABLED
405
+#include "stm32f4xx_hal_spi.h"
406
+#endif /* HAL_SPI_MODULE_ENABLED */
407
+
408
+#ifdef HAL_TIM_MODULE_ENABLED
409
+#include "stm32f4xx_hal_tim.h"
410
+#endif /* HAL_TIM_MODULE_ENABLED */
411
+
412
+#ifdef HAL_UART_MODULE_ENABLED
413
+#include "stm32f4xx_hal_uart.h"
414
+#endif /* HAL_UART_MODULE_ENABLED */
415
+
416
+#ifdef HAL_USART_MODULE_ENABLED
417
+#include "stm32f4xx_hal_usart.h"
418
+#endif /* HAL_USART_MODULE_ENABLED */
419
+
420
+#ifdef HAL_IRDA_MODULE_ENABLED
421
+#include "stm32f4xx_hal_irda.h"
422
+#endif /* HAL_IRDA_MODULE_ENABLED */
423
+
424
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
425
+#include "stm32f4xx_hal_smartcard.h"
426
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
427
+
428
+#ifdef HAL_WWDG_MODULE_ENABLED
429
+#include "stm32f4xx_hal_wwdg.h"
430
+#endif /* HAL_WWDG_MODULE_ENABLED */
431
+
432
+#ifdef HAL_PCD_MODULE_ENABLED
433
+#include "stm32f4xx_hal_pcd.h"
434
+#endif /* HAL_PCD_MODULE_ENABLED */
435
+
436
+#ifdef HAL_HCD_MODULE_ENABLED
437
+#include "stm32f4xx_hal_hcd.h"
438
+#endif /* HAL_HCD_MODULE_ENABLED */
439
+
440
+#ifdef HAL_DSI_MODULE_ENABLED
441
+#include "stm32f4xx_hal_dsi.h"
442
+#endif /* HAL_DSI_MODULE_ENABLED */
443
+
444
+#ifdef HAL_QSPI_MODULE_ENABLED
445
+#include "stm32f4xx_hal_qspi.h"
446
+#endif /* HAL_QSPI_MODULE_ENABLED */
447
+
448
+#ifdef HAL_CEC_MODULE_ENABLED
449
+#include "stm32f4xx_hal_cec.h"
450
+#endif /* HAL_CEC_MODULE_ENABLED */
451
+
452
+#ifdef HAL_FMPI2C_MODULE_ENABLED
453
+#include "stm32f4xx_hal_fmpi2c.h"
454
+#endif /* HAL_FMPI2C_MODULE_ENABLED */
455
+
456
+#ifdef HAL_SPDIFRX_MODULE_ENABLED
457
+#include "stm32f4xx_hal_spdifrx.h"
458
+#endif /* HAL_SPDIFRX_MODULE_ENABLED */
459
+
460
+#ifdef HAL_DFSDM_MODULE_ENABLED
461
+#include "stm32f4xx_hal_dfsdm.h"
462
+#endif /* HAL_DFSDM_MODULE_ENABLED */
463
+
464
+#ifdef HAL_LPTIM_MODULE_ENABLED
465
+#include "stm32f4xx_hal_lptim.h"
466
+#endif /* HAL_LPTIM_MODULE_ENABLED */
467
+
468
+#ifdef HAL_MMC_MODULE_ENABLED
469
+#include "stm32f4xx_hal_mmc.h"
470
+#endif /* HAL_MMC_MODULE_ENABLED */
471
+
472
+/* Exported macro ------------------------------------------------------------*/
473
+#ifdef USE_FULL_ASSERT
474
+/**
475
+  * @brief  The assert_param macro is used for function's parameters check.
476
+  * @param  expr If expr is false, it calls assert_failed function
477
+  *         which reports the name of the source file and the source
478
+  *         line number of the call that failed.
479
+  *         If expr is true, it returns no value.
480
+  * @retval None
481
+  */
482
+#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))
483
+/* Exported functions ------------------------------------------------------- */
484
+void assert_failed(uint8_t *file, uint32_t line);
485
+#else
486
+#define assert_param(expr) ((void)0U)
487
+#endif /* USE_FULL_ASSERT */
488
+
489
+#ifdef __cplusplus
490
+}
491
+#endif
492
+
493
+#endif /* __STM32F4xx_HAL_CONF_CUSTOM_H */
494
+
495
+
496
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+ 187
- 0
buildroot/share/PlatformIO/variants/FYSETC_CHEETAH_V20/ldscript.ld View File

@@ -0,0 +1,187 @@
1
+/*
2
+*****************************************************************************
3
+**
4
+
5
+**  File        : LinkerScript.ld
6
+**
7
+**  Abstract    : Linker script for STM32F401RETx Device with
8
+**                512KByte FLASH, 96KByte RAM
9
+**
10
+**                Set heap size, stack size and stack location according
11
+**                to application requirements.
12
+**
13
+**                Set memory bank area and size if external memory is used.
14
+**
15
+**  Target      : STMicroelectronics STM32
16
+**
17
+**
18
+**  Distribution: The file is distributed as is, without any warranty
19
+**                of any kind.
20
+**
21
+*****************************************************************************
22
+** @attention
23
+**
24
+** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
25
+**
26
+** Redistribution and use in source and binary forms, with or without modification,
27
+** are permitted provided that the following conditions are met:
28
+**   1. Redistributions of source code must retain the above copyright notice,
29
+**      this list of conditions and the following disclaimer.
30
+**   2. Redistributions in binary form must reproduce the above copyright notice,
31
+**      this list of conditions and the following disclaimer in the documentation
32
+**      and/or other materials provided with the distribution.
33
+**   3. Neither the name of Ac6 nor the names of its contributors
34
+**      may be used to endorse or promote products derived from this software
35
+**      without specific prior written permission.
36
+**
37
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
38
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
40
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
41
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
42
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
43
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
44
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
45
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47
+**
48
+*****************************************************************************
49
+*/
50
+
51
+/* Entry Point */
52
+ENTRY(Reset_Handler)
53
+
54
+/* Highest address of the user mode stack */
55
+_estack = 0x20010000;    /* end of RAM */
56
+
57
+/* Generate a link error if heap and stack don't fit into RAM */
58
+_Min_Heap_Size = 0x200;;      /* required amount of heap  */
59
+_Min_Stack_Size = 0x400;; /* required amount of stack */
60
+
61
+/* Specify the memory areas */
62
+MEMORY
63
+{
64
+FLASH (rx)      : ORIGIN = 0x800C000, LENGTH = 256K
65
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 64K
66
+}
67
+
68
+/* Define output sections */
69
+SECTIONS
70
+{
71
+  /* The startup code goes first into FLASH */
72
+  .isr_vector :
73
+  {
74
+    . = ALIGN(4);
75
+    KEEP(*(.isr_vector)) /* Startup code */
76
+    . = ALIGN(4);
77
+  } >FLASH
78
+
79
+  /* The program code and other data goes into FLASH */
80
+  .text ALIGN(4):
81
+  {
82
+    . = ALIGN(4);
83
+    *(.text)           /* .text sections (code) */
84
+    *(.text*)          /* .text* sections (code) */
85
+    *(.glue_7)         /* glue arm to thumb code */
86
+    *(.glue_7t)        /* glue thumb to arm code */
87
+    *(.eh_frame)
88
+
89
+    KEEP (*(.init))
90
+    KEEP (*(.fini))
91
+
92
+    . = ALIGN(4);
93
+    _etext = .;        /* define a global symbols at end of code */
94
+  } >FLASH
95
+
96
+  /* Constant data goes into FLASH */
97
+  .rodata :
98
+  {
99
+    . = ALIGN(4);
100
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
101
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
102
+    . = ALIGN(4);
103
+  } >FLASH
104
+
105
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
106
+  .ARM : {
107
+    __exidx_start = .;
108
+    *(.ARM.exidx*)
109
+    __exidx_end = .;
110
+  } >FLASH
111
+
112
+  .preinit_array     :
113
+  {
114
+    PROVIDE_HIDDEN (__preinit_array_start = .);
115
+    KEEP (*(.preinit_array*))
116
+    PROVIDE_HIDDEN (__preinit_array_end = .);
117
+  } >FLASH
118
+  .init_array :
119
+  {
120
+    PROVIDE_HIDDEN (__init_array_start = .);
121
+    KEEP (*(SORT(.init_array.*)))
122
+    KEEP (*(.init_array*))
123
+    PROVIDE_HIDDEN (__init_array_end = .);
124
+  } >FLASH
125
+  .fini_array :
126
+  {
127
+    PROVIDE_HIDDEN (__fini_array_start = .);
128
+    KEEP (*(SORT(.fini_array.*)))
129
+    KEEP (*(.fini_array*))
130
+    PROVIDE_HIDDEN (__fini_array_end = .);
131
+  } >FLASH
132
+
133
+  /* used by the startup to initialize data */
134
+  _sidata = LOADADDR(.data);
135
+
136
+  /* Initialized data sections goes into RAM, load LMA copy after code */
137
+  .data :
138
+  {
139
+    . = ALIGN(4);
140
+    _sdata = .;        /* create a global symbol at data start */
141
+    *(.data)           /* .data sections */
142
+    *(.data*)          /* .data* sections */
143
+
144
+    . = ALIGN(4);
145
+    _edata = .;        /* define a global symbol at data end */
146
+  } >RAM AT> FLASH
147
+
148
+
149
+  /* Uninitialized data section */
150
+  . = ALIGN(4);
151
+  .bss :
152
+  {
153
+    /* This is used by the startup in order to initialize the .bss secion */
154
+    _sbss = .;         /* define a global symbol at bss start */
155
+    __bss_start__ = _sbss;
156
+    *(.bss)
157
+    *(.bss*)
158
+    *(COMMON)
159
+
160
+    . = ALIGN(4);
161
+    _ebss = .;         /* define a global symbol at bss end */
162
+    __bss_end__ = _ebss;
163
+  } >RAM
164
+
165
+  /* User_heap_stack section, used to check that there is enough RAM left */
166
+  ._user_heap_stack :
167
+  {
168
+    . = ALIGN(8);
169
+    PROVIDE ( end = . );
170
+    PROVIDE ( _end = . );
171
+    . = . + _Min_Heap_Size;
172
+    . = . + _Min_Stack_Size;
173
+    . = ALIGN(8);
174
+  } >RAM
175
+
176
+
177
+
178
+  /* Remove information from the standard libraries */
179
+  /DISCARD/ :
180
+  {
181
+    libc.a ( * )
182
+    libm.a ( * )
183
+    libgcc.a ( * )
184
+  }
185
+
186
+  .ARM.attributes 0 : { *(.ARM.attributes) }
187
+}

+ 238
- 0
buildroot/share/PlatformIO/variants/FYSETC_CHEETAH_V20/variant.cpp View File

@@ -0,0 +1,238 @@
1
+/*
2
+  Copyright (c) 2011 Arduino.  All right reserved.
3
+
4
+  This library is free software; you can redistribute it and/or
5
+  modify it under the terms of the GNU Lesser General Public
6
+  License as published by the Free Software Foundation; either
7
+  version 2.1 of the License, or (at your option) any later version.
8
+
9
+  This library is distributed in the hope that it will be useful,
10
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
11
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12
+  See the GNU Lesser General Public License for more details.
13
+
14
+  You should have received a copy of the GNU Lesser General Public
15
+  License along with this library; if not, write to the Free Software
16
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
17
+*/
18
+
19
+#include "pins_arduino.h"
20
+
21
+#ifdef __cplusplus
22
+extern "C" {
23
+#endif
24
+
25
+// Digital PinName array
26
+const PinName digitalPin[] = {
27
+  PA_0,  // Digital pin 0
28
+  PA_1,  // Digital pin 1
29
+  PA_2,  // Digital pin 2
30
+  PA_3,  // Digital pin 3
31
+  PA_4,  // Digital pin 4
32
+  PA_5,  // Digital pin 5
33
+  PA_6,  // Digital pin 6
34
+  PA_7,  // Digital pin 7
35
+  PA_8,  // Digital pin 8
36
+  PA_9,  // Digital pin 9
37
+  PA_10, // Digital pin 10
38
+  PA_11, // Digital pin 11
39
+  PA_12, // Digital pin 12
40
+  PA_13, // Digital pin 13
41
+  PA_14, // Digital pin 14
42
+  PA_15, // Digital pin 15
43
+
44
+  PB_0,  // Digital pin 16
45
+  PB_1,  // Digital pin 17
46
+  PB_2,  // Digital pin 18
47
+  PB_3,  // Digital pin 19
48
+  PB_4,  // Digital pin 20
49
+  PB_5,  // Digital pin 21
50
+  PB_6,  // Digital pin 22
51
+  PB_7,  // Digital pin 23
52
+  PB_8,  // Digital pin 24
53
+  PB_9,  // Digital pin 25
54
+  PB_10, // Digital pin 26
55
+  PB_12, // Digital pin 27
56
+  PB_13, // Digital pin 28
57
+  PB_14, // Digital pin 29
58
+  PB_15, // Digital pin 30
59
+
60
+  PC_0,  // Digital pin 31
61
+  PC_1,  // Digital pin 32
62
+  PC_2,  // Digital pin 33
63
+  PC_3,  // Digital pin 34
64
+  PC_4,  // Digital pin 35
65
+  PC_5,  // Digital pin 36
66
+  PC_6,  // Digital pin 37
67
+  PC_7,  // Digital pin 38
68
+  PC_8,  // Digital pin 39
69
+  PC_9,  // Digital pin 40
70
+  PC_10, // Digital pin 41
71
+  PC_11, // Digital pin 42
72
+  PC_12, // Digital pin 43
73
+  PC_13, // Digital pin 44
74
+  PC_14, // Digital pin 45
75
+  PC_15, // Digital pin 46
76
+
77
+  PD_2,  // Digital pin 47
78
+
79
+  PH_0,  // Digital pin 48, used by the external oscillator
80
+  PH_1   // Digital pin 49, used by the external oscillator
81
+};
82
+
83
+// Analog (Ax) pin number array
84
+const uint32_t analogInputPin[] = {
85
+  0,  // A0,  PA0
86
+  1,  // A1,  PA1
87
+  2,  // A2,  PA2
88
+  3,  // A3,  PA3
89
+  4,  // A4,  PA4
90
+  5,  // A5,  PA5
91
+  6,  // A6,  PA6
92
+  7,  // A7,  PA7
93
+  16, // A8,  PB0
94
+  17, // A9,  PB1
95
+  31, // A10, PC0
96
+  32, // A11, PC1
97
+  33, // A12, PC2
98
+  34, // A13, PC3
99
+  35, // A14, PC4
100
+  36  // A15, PC5
101
+};
102
+
103
+#ifdef __cplusplus
104
+}
105
+#endif
106
+
107
+// ----------------------------------------------------------------------------
108
+
109
+#ifdef __cplusplus
110
+extern "C" {
111
+#endif
112
+
113
+/*
114
+ * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
115
+ *               AHB/APBx prescalers and Flash settings
116
+ * @note   This function should be called only once the RCC clock configuration
117
+ *         is reset to the default reset state (done in SystemInit() function).
118
+ * @param  None
119
+ * @retval None
120
+ */
121
+
122
+/******************************************************************************/
123
+/*            PLL (clocked by HSE) used as System clock source                */
124
+/******************************************************************************/
125
+static uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
126
+{
127
+  RCC_OscInitTypeDef RCC_OscInitStruct;
128
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
129
+
130
+  /* The voltage scaling allows optimizing the power consumption when the device is
131
+  clocked below the maximum system frequency, to update the voltage scaling value
132
+  regarding system frequency refer to product datasheet. */
133
+  __HAL_RCC_PWR_CLK_ENABLE();
134
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
135
+
136
+  // Enable HSE oscillator and activate PLL with HSE as source
137
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE;
138
+  if (bypass == 0) {
139
+    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
140
+  } else {
141
+    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
142
+  }
143
+
144
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
145
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
146
+  RCC_OscInitStruct.PLL.PLLM            = HSE_VALUE / 1000000L; // Expects an 8 MHz external clock by default. Redefine HSE_VALUE if not
147
+  RCC_OscInitStruct.PLL.PLLN            = 336;           // VCO output clock = 336 MHz (1 MHz * 336)
148
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
149
+  RCC_OscInitStruct.PLL.PLLQ            = 7;             // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
150
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
151
+    return 0; // FAIL
152
+  }
153
+
154
+  // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
155
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
156
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
157
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 84 MHz
158
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 42 MHz
159
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 84 MHz
160
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
161
+    return 0; // FAIL
162
+  }
163
+
164
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
165
+  /*
166
+  if (bypass == 0)
167
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
168
+  else
169
+    HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
170
+  */
171
+
172
+  return 1; // OK
173
+}
174
+
175
+/******************************************************************************/
176
+/*            PLL (clocked by HSI) used as System clock source                */
177
+/******************************************************************************/
178
+uint8_t SetSysClock_PLL_HSI(void)
179
+{
180
+  RCC_OscInitTypeDef RCC_OscInitStruct;
181
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
182
+
183
+  /* The voltage scaling allows optimizing the power consumption when the device is
184
+    clocked below the maximum system frequency, to update the voltage scaling value
185
+    regarding system frequency refer to product datasheet. */
186
+  __HAL_RCC_PWR_CLK_ENABLE();
187
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
188
+
189
+  // Enable HSI oscillator and activate PLL with HSI as source
190
+  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
191
+  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
192
+  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
193
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
194
+  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
195
+  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
196
+  RCC_OscInitStruct.PLL.PLLM            = 16;            // VCO input clock = 1 MHz (16 MHz / 16)
197
+  RCC_OscInitStruct.PLL.PLLN            = 336;           // VCO output clock = 336 MHz (1 MHz * 336)
198
+  RCC_OscInitStruct.PLL.PLLP            = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
199
+  RCC_OscInitStruct.PLL.PLLQ            = 7;             // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
200
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
201
+    return 0; // FAIL
202
+  }
203
+
204
+  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
205
+  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
206
+  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
207
+  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 84 MHz
208
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;           // 42 MHz
209
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 84 MHz
210
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
211
+    return 0; // FAIL
212
+  }
213
+
214
+  /* Output clock on MCO1 pin(PA8) for debugging purpose */
215
+  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
216
+
217
+  return 1; // OK
218
+}
219
+
220
+WEAK void SystemClock_Config(void)
221
+{
222
+  /* 1- If fail try to start with HSE and external xtal */
223
+  if (SetSysClock_PLL_HSE(0) == 0) {
224
+    /* 2- Try to start with HSE and external clock */
225
+    if (SetSysClock_PLL_HSE(1) == 0) {
226
+      /* 3- If fail start with HSI clock */
227
+      if (SetSysClock_PLL_HSI() == 0) {
228
+        Error_Handler();
229
+      }
230
+    }
231
+  }
232
+  /* Output clock on MCO2 pin(PC9) for debugging purpose */
233
+  //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
234
+}
235
+
236
+#ifdef __cplusplus
237
+}
238
+#endif

+ 151
- 0
buildroot/share/PlatformIO/variants/FYSETC_CHEETAH_V20/variant.h View File

@@ -0,0 +1,151 @@
1
+/*
2
+  Copyright (c) 2011 Arduino.  All right reserved.
3
+
4
+  This library is free software; you can redistribute it and/or
5
+  modify it under the terms of the GNU Lesser General Public
6
+  License as published by the Free Software Foundation; either
7
+  version 2.1 of the License, or (at your option) any later version.
8
+
9
+  This library is distributed in the hope that it will be useful,
10
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
11
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12
+  See the GNU Lesser General Public License for more details.
13
+
14
+  You should have received a copy of the GNU Lesser General Public
15
+  License along with this library; if not, write to the Free Software
16
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
17
+*/
18
+
19
+#ifndef _VARIANT_ARDUINO_STM32_
20
+#define _VARIANT_ARDUINO_STM32_
21
+
22
+#ifdef __cplusplus
23
+extern "C" {
24
+#endif // __cplusplus
25
+
26
+
27
+//                  | DIGITAL | ANALOG | USART     | TWI      | SPI                    | SPECIAL   |
28
+//                  |---------|--------|-----------|----------|------------------------|-----------|
29
+#define PA0  A0  // | 0       | A0     |           |          |                        |           |
30
+#define PA1  A1  // | 1       | A1     |           |          |                        |           |
31
+#define PA2  A2  // | 2       | A2     | USART2_TX |          |                        |           |
32
+#define PA3  A3  // | 3       | A3     | USART2_RX |          |                        |           |
33
+#define PA4  A4  // | 4       | A4     |           |          | SPI1_SS, (SPI3_SS)     |           |
34
+#define PA5  A5  // | 5       | A5     |           |          | SPI1_SCK               |           |
35
+#define PA6  A6  // | 6       | A6     |           |          | SPI1_MISO              |           |
36
+#define PA7  A7  // | 7       | A7     |           |          | SPI1_MOSI              |           |
37
+#define PA8  8   // | 8       |        |           | TWI3_SCL |                        |           |
38
+#define PA9  9   // | 9       |        | USART1_TX |          |                        |           |
39
+#define PA10 10  // | 10      |        | USART1_RX |          |                        |           |
40
+#define PA11 11  // | 11      |        | USART6_TX |          |                        |           |
41
+#define PA12 12  // | 12      |        | USART6_RX |          |                        |           |
42
+#define PA13 13  // | 13      |        |           |          |                        | SWD_SWDIO |
43
+#define PA14 14  // | 14      |        |           |          |                        | SWD_SWCLK |
44
+#define PA15 15  // | 15      |        |           |          | SPI3_SS, (SPI1_SS)     |           |
45
+//                  |---------|--------|-----------|----------|------------------------|-----------|
46
+#define PB0  A8  // | 16      | A8     |           |          |                        |           |
47
+#define PB1  A9  // | 17      | A9     |           |          |                        |           |
48
+#define PB2  18  // | 18      |        |           |          |                        | BOOT1     |
49
+#define PB3  19  // | 19      |        |           | TWI2_SDA | SPI3_SCK,  (SPI1_SCK)  |           |
50
+#define PB4  20  // | 20      |        |           | TWI3_SDA | SPI3_MISO, (SPI1_MISO) |           |
51
+#define PB5  21  // | 21      |        |           |          | SPI3_MOSI, (SPI1_MOSI) |           |
52
+#define PB6  22  // | 22      |        | USART1_TX | TWI1_SCL |                        |           |
53
+#define PB7  23  // | 23      |        | USART1_RX | TWI1_SDA |                        |           |
54
+#define PB8  24  // | 24      |        |           | TWI1_SCL |                        |           |
55
+#define PB9  25  // | 25      |        |           | TWI1_SDA | SPI2_SS                |           |
56
+#define PB10 26  // | 26      |        |           | TWI2_SCL | SPI2_SCK               |           |
57
+#define PB12 27  // | 27      |        |           |          | SPI2_SS                |           |
58
+#define PB13 28  // | 28      |        |           |          | SPI2_SCK               |           |
59
+#define PB14 29  // | 29      |        |           |          | SPI2_MISO              |           |
60
+#define PB15 30  // | 30      |        |           |          | SPI2_MOSI              |           |
61
+//                  |---------|--------|-----------|----------|------------------------|-----------|
62
+#define PC0  A10 // | 31      | A10    |           |          |                        |           |
63
+#define PC1  A11 // | 32      | A11    |           |          |                        |           |
64
+#define PC2  A12 // | 33      | A12    |           |          | SPI2_MISO              |           |
65
+#define PC3  A13 // | 34      | A13    |           |          | SPI2_MOSI              |           |
66
+#define PC4  A14 // | 35      | A14    |           |          |                        |           |
67
+#define PC5  A15 // | 36      | A15    |           |          |                        |           |
68
+#define PC6  37  // | 37      |        | USART6_TX |          |                        |           |
69
+#define PC7  38  // | 38      |        | USART6_RX |          |                        |           |
70
+#define PC8  39  // | 39      |        |           |          |                        |           |
71
+#define PC9  40  // | 40      |        |           | TWI3_SDA |                        |           |
72
+#define PC10 41  // | 41      |        |           |          | SPI3_SCK               |           |
73
+#define PC11 42  // | 42      |        |           |          | SPI3_MISO              |           |
74
+#define PC12 43  // | 43      |        |           |          | SPI3_MOSI              |           |
75
+#define PC13 44  // | 44      |        |           |          |                        |           |
76
+#define PC14 45  // | 45      |        |           |          |                        | OSC32_IN  |
77
+#define PC15 46  // | 46      |        |           |          |                        | OSC32_OUT |
78
+//                  |---------|--------|-----------|----------|------------------------|-----------|
79
+#define PD2  47  // | 47      |        |           |          |                        |           |
80
+//                  |---------|--------|-----------|----------|------------------------|-----------|
81
+#define PH0  48  // | 48      |        |           |          |                        | OSC_IN    |
82
+#define PH1  49  // | 49      |        |           |          |                        | OSC_OUT   |
83
+//                  |---------|--------|-----------|----------|------------------------|-----------|
84
+
85
+// This must be a literal
86
+#define NUM_DIGITAL_PINS        50
87
+#define NUM_ANALOG_INPUTS       16
88
+
89
+// SPI definitions
90
+#define PIN_SPI_SS              PA4
91
+#define PIN_SPI_SS1             PA4
92
+#define PIN_SPI_MOSI            PA7
93
+#define PIN_SPI_MISO            PA6
94
+#define PIN_SPI_SCK             PA5
95
+
96
+
97
+// Timer Definitions
98
+#define TIMER_TONE              TIM2
99
+#define TIMER_SERVO             TIM5
100
+#define TIMER_SERIAL            TIM11
101
+
102
+// UART Definitions
103
+//#define ENABLE_HWSERIAL1        done automatically by the #define SERIAL_UART_INSTANCE below
104
+#define ENABLE_HWSERIAL2
105
+
106
+
107
+// Define here Serial instance number to map on Serial generic name (if not already used by SerialUSB)
108
+#define SERIAL_UART_INSTANCE    1 //1 for Serial = Serial1 (USART1)
109
+
110
+// Default pin used for 'Serial' instance
111
+// Mandatory for Firmata
112
+#define PIN_SERIAL_RX           PA10
113
+#define PIN_SERIAL_TX           PA9
114
+
115
+// Used when user instanciate a hardware Serial using its peripheral name.
116
+// Example: HardwareSerial mySerial(USART3);
117
+// will use PIN_SERIAL3_RX and PIN_SERIAL3_TX if defined.
118
+#define PIN_SERIAL1_RX          PA10
119
+#define PIN_SERIAL1_TX          PA9
120
+#define PIN_SERIAL2_RX          PA3
121
+#define PIN_SERIAL2_TX          PA2
122
+
123
+#ifdef __cplusplus
124
+} // extern "C"
125
+#endif
126
+/*----------------------------------------------------------------------------
127
+ *        Arduino objects - C++ only
128
+ *----------------------------------------------------------------------------*/
129
+
130
+#ifdef __cplusplus
131
+  // These serial port names are intended to allow libraries and architecture-neutral
132
+  // sketches to automatically default to the correct port name for a particular type
133
+  // of use.  For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
134
+  // the first hardware serial port whose RX/TX pins are not dedicated to another use.
135
+  //
136
+  // SERIAL_PORT_MONITOR        Port which normally prints to the Arduino Serial Monitor
137
+  //
138
+  // SERIAL_PORT_USBVIRTUAL     Port which is USB virtual serial
139
+  //
140
+  // SERIAL_PORT_LINUXBRIDGE    Port which connects to a Linux system via Bridge library
141
+  //
142
+  // SERIAL_PORT_HARDWARE       Hardware serial port, physical RX & TX pins.
143
+  //
144
+  // SERIAL_PORT_HARDWARE_OPEN  Hardware serial ports which are open for use.  Their RX & TX
145
+  //                            pins are NOT connected to anything by default.
146
+  #define SERIAL_PORT_MONITOR         Serial
147
+  #define SERIAL_PORT_HARDWARE        Serial1
148
+  #define SERIAL_PORT_HARDWARE_OPEN   Serial2
149
+#endif
150
+
151
+#endif /* _VARIANT_ARDUINO_STM32_ */

+ 12
- 0
platformio.ini View File

@@ -1199,6 +1199,18 @@ extra_scripts     = ${common.extra_scripts}
1199 1199
   buildroot/share/PlatformIO/scripts/STEVAL__F401XX.py
1200 1200
 
1201 1201
 #
1202
+# STM32F401RC
1203
+#
1204
+[env:FYSETC_CHEETAH_V20]
1205
+platform          = ${common_stm32.platform}
1206
+extends           = common_stm32
1207
+board             = FYSETC_CHEETAH_V20
1208
+build_flags       = ${common_stm32.build_flags} -DSTM32F401xC -DVECT_TAB_OFFSET=0xC000
1209
+extra_scripts     = ${common.extra_scripts}
1210
+  pre:buildroot/share/PlatformIO/scripts/generic_create_variant.py
1211
+  buildroot/share/PlatformIO/scripts/FYSETC_CHEETAH_V20.py
1212
+
1213
+#
1202 1214
 # FLYF407ZG
1203 1215
 #
1204 1216
 [env:FLYF407ZG]

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