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+/**
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+ * Marlin 3D Printer Firmware
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+ * Copyright (C) 2016 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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+ *
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+ * Based on Sprinter and grbl.
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+ * Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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+ *
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+ * This program is free software: you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation, either version 3 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ *
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+ */
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+#ifdef ARDUINO_ARCH_ESP32
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+
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+#include <Arduino.h> // replace that with the proper imports
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+#include "i2s.h"
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+#include "../../core/macros.h"
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+#include "driver/periph_ctrl.h"
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+#include "rom/lldesc.h"
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+#include "soc/i2s_struct.h"
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+#include "freertos/queue.h"
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+#include "../../module/stepper.h"
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+
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+#define DMA_BUF_COUNT 8 // number of DMA buffers to store data
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+#define DMA_BUF_LEN 4092 // maximum size in bytes
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+#define I2S_SAMPLE_SIZE 4 // 4 bytes, 32 bits per sample
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+#define DMA_SAMPLE_COUNT DMA_BUF_LEN / I2S_SAMPLE_SIZE // number of samples per buffer
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+
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+typedef enum {
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+ I2S_NUM_0 = 0x0, /*!< I2S 0*/
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+ I2S_NUM_1 = 0x1, /*!< I2S 1*/
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+ I2S_NUM_MAX,
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+} i2s_port_t;
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+
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+typedef struct {
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+ uint32_t **buffers;
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+ uint32_t *current;
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+ uint32_t rw_pos;
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+ lldesc_t **desc;
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+ xQueueHandle queue;
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+} i2s_dma_t;
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+
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+static portMUX_TYPE i2s_spinlock[I2S_NUM_MAX] = {portMUX_INITIALIZER_UNLOCKED, portMUX_INITIALIZER_UNLOCKED};
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+static i2s_dev_t* I2S[I2S_NUM_MAX] = {&I2S0, &I2S1};
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+static i2s_dma_t dma;
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+
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+// output value
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+uint32_t i2s_port_data;
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+
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+#define I2S_ENTER_CRITICAL() portENTER_CRITICAL(&i2s_spinlock[i2s_num])
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+#define I2S_EXIT_CRITICAL() portEXIT_CRITICAL(&i2s_spinlock[i2s_num])
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+
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+static inline void gpio_matrix_out_check(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv) {
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+ //if pin = -1, do not need to configure
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+ if (gpio != -1) {
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+ PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[gpio], PIN_FUNC_GPIO);
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+ gpio_set_direction((gpio_num_t)gpio, (gpio_mode_t)GPIO_MODE_DEF_OUTPUT);
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+ gpio_matrix_out(gpio, signal_idx, out_inv, oen_inv);
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+ }
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+}
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+
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+static esp_err_t i2s_reset_fifo(i2s_port_t i2s_num) {
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+ I2S_ENTER_CRITICAL();
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+ I2S[i2s_num]->conf.rx_fifo_reset = 1;
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+ I2S[i2s_num]->conf.rx_fifo_reset = 0;
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+ I2S[i2s_num]->conf.tx_fifo_reset = 1;
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+ I2S[i2s_num]->conf.tx_fifo_reset = 0;
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+ I2S_EXIT_CRITICAL();
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+
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+ return ESP_OK;
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+}
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+
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+esp_err_t i2s_start(i2s_port_t i2s_num) {
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+ //start DMA link
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+ I2S_ENTER_CRITICAL();
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+ i2s_reset_fifo(i2s_num);
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+
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+ //reset dma
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+ I2S[i2s_num]->lc_conf.in_rst = 1;
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+ I2S[i2s_num]->lc_conf.in_rst = 0;
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+ I2S[i2s_num]->lc_conf.out_rst = 1;
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+ I2S[i2s_num]->lc_conf.out_rst = 0;
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+
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+ I2S[i2s_num]->conf.tx_reset = 1;
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+ I2S[i2s_num]->conf.tx_reset = 0;
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+ I2S[i2s_num]->conf.rx_reset = 1;
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+ I2S[i2s_num]->conf.rx_reset = 0;
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+
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+ I2S[i2s_num]->int_clr.val = 0xFFFFFFFF;
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+ I2S[i2s_num]->out_link.start = 1;
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+ I2S[i2s_num]->conf.tx_start = 1;
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+ I2S_EXIT_CRITICAL();
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+
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+ return ESP_OK;
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+}
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+
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+esp_err_t i2s_stop(i2s_port_t i2s_num) {
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+ I2S_ENTER_CRITICAL();
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+ I2S[i2s_num]->out_link.stop = 1;
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+ I2S[i2s_num]->conf.tx_start = 0;
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+
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+ I2S[i2s_num]->int_clr.val = I2S[i2s_num]->int_st.val; //clear pending interrupt
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+ I2S_EXIT_CRITICAL();
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+
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+ return ESP_OK;
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+}
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+
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+static void IRAM_ATTR i2s_intr_handler_default(void *arg) {
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+ int dummy;
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+ lldesc_t *finish_desc;
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+ portBASE_TYPE high_priority_task_awoken = pdFALSE;
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+
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+ if (I2S0.int_st.out_eof) {
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+ // Get the descriptor of the last item in the linkedlist
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+ finish_desc = (lldesc_t*) I2S0.out_eof_des_addr;
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+
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+ // If the queue is full it's because we have an underflow,
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+ // more than buf_count isr without new data, remove the front buffer
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+ if (xQueueIsQueueFullFromISR(dma.queue))
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+ xQueueReceiveFromISR(dma.queue, &dummy, &high_priority_task_awoken);
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+
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+ xQueueSendFromISR(dma.queue, (void *)(&finish_desc->buf), &high_priority_task_awoken);
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+ }
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+
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+ if (high_priority_task_awoken == pdTRUE) portYIELD_FROM_ISR();
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+
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+ // clear interrupt
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+ I2S0.int_clr.val = I2S0.int_st.val; //clear pending interrupt
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+}
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+
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+void stepperTask(void* parameter) {
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+ uint32_t i, remaining = 0;
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+
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+ while (1) {
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+ xQueueReceive(dma.queue, &dma.current, portMAX_DELAY);
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+ dma.rw_pos = 0;
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+
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+ for (i = 0; i < DMA_SAMPLE_COUNT; i++) {
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+ // Fill with the port data post pulse_phase until the next step
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+ if (remaining) {
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+ i2s_push_sample();
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+ remaining--;
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+ }
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+ else {
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+ Stepper::stepper_pulse_phase_isr();
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+ remaining = Stepper::stepper_block_phase_isr();
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+ }
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+ }
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+ }
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+}
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+
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+int i2s_init() {
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+ periph_module_enable(PERIPH_I2S0_MODULE);
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+
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+ /**
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+ * Each i2s transfer will take
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+ * fpll = PLL_D2_CLK -- clka_en = 0
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+ *
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+ * fi2s = fpll / N + b/a -- N = clkm_div_num
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+ * fi2s = 160MHz / 2
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+ * fi2s = 80MHz
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+ *
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+ * fbclk = fi2s / M -- M = tx_bck_div_num
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+ * fbclk = 80MHz / 2
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+ * fbclk = 40MHz
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+ *
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+ * fwclk = fbclk / 32
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+ *
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+ * for fwclk = 250kHz (4uS pulse time)
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+ * N = 10
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+ * M = 20
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+ */
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+
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+ // Allocate the array of pointers to the buffers
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+ dma.buffers = (uint32_t **)malloc(sizeof(uint32_t*) * DMA_BUF_COUNT);
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+ if (dma.buffers == NULL) return -1;
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+
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+ // Allocate each buffer that can be used by the DMA controller
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+ for (int buf_idx = 0; buf_idx < DMA_BUF_COUNT; buf_idx++) {
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+ dma.buffers[buf_idx] = (uint32_t*) heap_caps_calloc(1, DMA_BUF_LEN, MALLOC_CAP_DMA);
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+ if (dma.buffers[buf_idx] == NULL) return -1;
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+ }
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+
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+ // Allocate the array of DMA descriptors
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+ dma.desc = (lldesc_t**) malloc(sizeof(lldesc_t*) * DMA_BUF_COUNT);
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+ if (dma.desc == NULL) return -1;
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+
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+ // Allocate each DMA descriptor that will be used by the DMA controller
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+ for (int buf_idx = 0; buf_idx < DMA_BUF_COUNT; buf_idx++) {
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+ dma.desc[buf_idx] = (lldesc_t*) heap_caps_malloc(sizeof(lldesc_t), MALLOC_CAP_DMA);
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+ if (dma.desc[buf_idx] == NULL) return -1;
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+ }
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+
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+ // Initialize
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+ for (int buf_idx = 0; buf_idx < DMA_BUF_COUNT; buf_idx++) {
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+ dma.desc[buf_idx]->owner = 1;
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+ dma.desc[buf_idx]->eof = 1; // set to 1 will trigger the interrupt
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+ dma.desc[buf_idx]->sosf = 0;
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+ dma.desc[buf_idx]->length = DMA_BUF_LEN;
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+ dma.desc[buf_idx]->size = DMA_BUF_LEN;
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+ dma.desc[buf_idx]->buf = (uint8_t *) dma.buffers[buf_idx];
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+ dma.desc[buf_idx]->offset = 0;
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+ dma.desc[buf_idx]->empty = (uint32_t)((buf_idx < (DMA_BUF_COUNT - 1)) ? (dma.desc[buf_idx + 1]) : dma.desc[0]);
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+ }
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+
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+ dma.queue = xQueueCreate(DMA_BUF_COUNT, sizeof(uint32_t *));
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+
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+ // Set the first DMA descriptor
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+ I2S0.out_link.addr = (uint32_t)dma.desc[0];
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+
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+ // stop i2s
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+ i2s_stop(I2S_NUM_0);
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+
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+ // configure I2S data port interface.
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+ i2s_reset_fifo(I2S_NUM_0);
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+
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+ //reset i2s
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+ I2S0.conf.tx_reset = 1;
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+ I2S0.conf.tx_reset = 0;
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+ I2S0.conf.rx_reset = 1;
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+ I2S0.conf.rx_reset = 0;
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+
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+ //reset dma
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+ I2S0.lc_conf.in_rst = 1;
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+ I2S0.lc_conf.in_rst = 0;
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+ I2S0.lc_conf.out_rst = 1;
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+ I2S0.lc_conf.out_rst = 0;
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+
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+ //Enable and configure DMA
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+ I2S0.lc_conf.check_owner = 0;
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+ I2S0.lc_conf.out_loop_test = 0;
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+ I2S0.lc_conf.out_auto_wrback = 0;
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+ I2S0.lc_conf.out_data_burst_en = 0;
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+ I2S0.lc_conf.outdscr_burst_en = 0;
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+ I2S0.lc_conf.out_no_restart_clr = 0;
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+ I2S0.lc_conf.indscr_burst_en = 0;
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+ I2S0.lc_conf.out_eof_mode = 1;
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+
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+ I2S0.conf2.lcd_en = 0;
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+ I2S0.conf2.camera_en = 0;
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+ I2S0.pdm_conf.pcm2pdm_conv_en = 0;
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+ I2S0.pdm_conf.pdm2pcm_conv_en = 0;
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+
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+ I2S0.fifo_conf.dscr_en = 0;
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+
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+ I2S0.conf_chan.tx_chan_mod = 0;
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+ I2S0.fifo_conf.tx_fifo_mod = 0;
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+ I2S0.conf.tx_mono = 0;
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+
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+ I2S0.conf_chan.rx_chan_mod = 0;
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+ I2S0.fifo_conf.rx_fifo_mod = 0;
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+ I2S0.conf.rx_mono = 0;
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+
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+ I2S0.fifo_conf.dscr_en = 1; //connect dma to fifo
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+
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+ I2S0.conf.tx_start = 0;
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+ I2S0.conf.rx_start = 0;
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+
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+ I2S0.conf.tx_msb_right = 1;
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+ I2S0.conf.tx_right_first = 1;
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+
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+ I2S0.conf.tx_slave_mod = 0; // Master
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+ I2S0.fifo_conf.tx_fifo_mod_force_en = 1;
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+
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+ I2S0.pdm_conf.rx_pdm_en = 0;
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+ I2S0.pdm_conf.tx_pdm_en = 0;
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+
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+ I2S0.conf.tx_short_sync = 0;
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+ I2S0.conf.rx_short_sync = 0;
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+ I2S0.conf.tx_msb_shift = 0;
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+ I2S0.conf.rx_msb_shift = 0;
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+
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+ // set clock
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+ I2S0.clkm_conf.clka_en = 0; // Use PLL/2 as reference
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+ I2S0.clkm_conf.clkm_div_num = 10; // minimum value of 2, reset value of 4, max 256
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+ I2S0.clkm_conf.clkm_div_a = 0; // 0 at reset, what about divide by 0? (not an issue)
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+ I2S0.clkm_conf.clkm_div_b = 0; // 0 at reset
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+
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+ // fbck = fi2s / tx_bck_div_num
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+ I2S0.sample_rate_conf.tx_bck_div_num = 2; // minimum value of 2 defaults to 6
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+
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+ // Enable TX interrupts
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+ I2S0.int_ena.out_eof = 1;
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+ I2S0.int_ena.out_dscr_err = 0;
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+ I2S0.int_ena.out_total_eof = 0;
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+ I2S0.int_ena.out_done = 0;
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+
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+ // Allocate and Enable the I2S interrupt
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+ intr_handle_t i2s_isr_handle;
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+ esp_intr_alloc(ETS_I2S0_INTR_SOURCE, 0, i2s_intr_handler_default, NULL, &i2s_isr_handle);
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+ esp_intr_enable(i2s_isr_handle);
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+
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+ // Create the task that will feed the buffer
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+ xTaskCreate(stepperTask, "StepperTask", 10000, NULL, 1, NULL);
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+
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+ // Route the i2s pins to the appropriate GPIO
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+ gpio_matrix_out_check(22, I2S0O_DATA_OUT23_IDX, 0, 0);
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307
|
+ gpio_matrix_out_check(25, I2S0O_WS_OUT_IDX, 0, 0);
|
|
308
|
+ gpio_matrix_out_check(26, I2S0O_BCK_OUT_IDX, 0, 0);
|
|
309
|
+
|
|
310
|
+ // Start the I2S peripheral
|
|
311
|
+ return i2s_start(I2S_NUM_0);
|
|
312
|
+}
|
|
313
|
+
|
|
314
|
+void i2s_write(uint8_t pin, uint8_t val) {
|
|
315
|
+ SET_BIT_TO(i2s_port_data, pin, val);
|
|
316
|
+}
|
|
317
|
+
|
|
318
|
+void i2s_push_sample() {
|
|
319
|
+ dma.current[dma.rw_pos++] = i2s_port_data;
|
|
320
|
+}
|
|
321
|
+
|
|
322
|
+#endif // ARDUINO_ARCH_ESP32
|