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Add macros for ST7565 commands

Scott Lahteine 6年前
コミット
61181b7f24
1個のファイルの変更66行の追加54行の削除
  1. 66
    54
      Marlin/src/lcd/dogm/u8g_dev_st7565_64128n_HAL.cpp

+ 66
- 54
Marlin/src/lcd/dogm/u8g_dev_st7565_64128n_HAL.cpp ファイルの表示

@@ -65,77 +65,90 @@
65 65
 #define HEIGHT 64
66 66
 #define PAGE_HEIGHT 8
67 67
 
68
+#define ST7565_ADC_REVERSE(N)    (0xA0 | ((N) & 0x1))
69
+#define ST7565_BIAS_MODE(N)      (0xA2 | ((N) & 0x1))
70
+#define ST7565_ALL_PIX(N)        (0xA4 | ((N) & 0x1))
71
+#define ST7565_INVERTED(N)       (0xA6 | ((N) & 0x1))
72
+#define ST7565_ON(N)             (0xAE | ((N) & 0x1))
73
+#define ST7565_OUT_MODE(N)       (0xC0 | ((N) & 0x1) << 3)
74
+#define ST7565_POWER_CONTROL(N)  (0x28 | (N))
75
+#define ST7565_V0_RATIO(N)       (0x20 | ((N) & 0x7))
76
+#define ST7565_CONTRAST(N)       (0x81), (N)
77
+
78
+#define ST7565_COLUMN_ADR(N)     (0x10 | ((N) >> 4) & 0xF), (0x00 | ((N) & 0xF))
79
+#define ST7565_PAGE_ADR(N)       (0xB0 | (N))
80
+#define ST7565_START_LINE(N)     (0x40 | (N))
81
+#define ST7565_SLEEP_MODE()      (0xAC)
82
+#define ST7565_NOOP()            (0xE3)
83
+
68 84
 /* init sequence from https://github.com/adafruit/ST7565-LCD/blob/master/ST7565/ST7565.cpp */
69 85
 static const uint8_t u8g_dev_st7565_64128n_HAL_init_seq[] PROGMEM = {
70
-  U8G_ESC_CS(0),       // disable chip
71
-  U8G_ESC_ADR(0),     // instruction mode
72
-  U8G_ESC_CS(1),      // enable chip
73
-  U8G_ESC_RST(15),    // do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
74
-
75
-  0x0A2,              // 0x0A2: LCD bias 1/9 (according to Displaytech 64128N datasheet)
76
-  0x0A0,              // Normal ADC Select (according to Displaytech 64128N datasheet)
86
+  U8G_ESC_CS(0),              // disable chip
87
+  U8G_ESC_ADR(0),             // instruction mode
88
+  U8G_ESC_CS(1),              // enable chip
89
+  U8G_ESC_RST(15),            // do reset low pulse with (15*16)+2 milliseconds (=maximum delay)*/
77 90
 
78
-  0x0C8,              // common output mode: set scan direction normal operation/SHL Select, 0x0C0 --> SHL = 0, normal, 0x0C8 --> SHL = 1
79
-  0x040,              // Display start line for Displaytech 64128N
91
+  ST7565_BIAS_MODE(0),        // 0xA2: LCD bias 1/9 (according to Displaytech 64128N datasheet)
92
+  ST7565_ADC_REVERSE(0),      // Normal ADC Select (according to Displaytech 64128N datasheet)
80 93
 
81
-  0x028 | 0x04,       // power control: turn on voltage converter
82
-  U8G_ESC_DLY(50),    // delay 50 ms
94
+  ST7565_OUT_MODE(1),         // common output mode: set scan direction normal operation/SHL Select, 0x0C0 --> SHL = 0, normal, 0x0C8 --> SHL = 1
95
+  ST7565_START_LINE(0),       // Display start line for Displaytech 64128N
83 96
 
84
-  0x028 | 0x06,       // power control: turn on voltage regulator
85
-  U8G_ESC_DLY(50),    // delay 50 ms
97
+  //0x028 | 0x04,             // power control: turn on voltage converter
98
+  //U8G_ESC_DLY(50),          // delay 50 ms
86 99
 
87
-  0x028 | 0x07,       // power control: turn on voltage follower
88
-  U8G_ESC_DLY(50),    // delay 50 ms
100
+  //0x028 | 0x06,             // power control: turn on voltage regulator
101
+  //U8G_ESC_DLY(50),          // delay 50 ms
89 102
 
90
-  0x010,              // Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N
103
+  ST7565_POWER_CONTROL(0x7),  // power control: turn on voltage follower
104
+  U8G_ESC_DLY(50),            // delay 50 ms
91 105
 
92
-  0x0A6,              // display normal, bit val 0: LCD pixel off.
106
+  ST7565_V0_RATIO(0),         // Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N
93 107
 
94
-  0x081,              // set contrast
95
-  0x01E,              // Contrast value. Setting for controlling brightness of Displaytech 64128N
108
+  ST7565_INVERTED(0),         // display normal, bit val 0: LCD pixel off.
96 109
 
110
+  ST7565_CONTRAST(0x1E),      // Contrast value. Setting for controlling brightness of Displaytech 64128N
97 111
 
98
-  0x0AF,              // display on
112
+  ST7565_ON(1),               // display on
99 113
 
100
-  U8G_ESC_DLY(100),   // delay 100 ms
101
-  0x0A5,              // display all points, ST7565
102
-  U8G_ESC_DLY(100),   // delay 100 ms
103
-  U8G_ESC_DLY(100),   // delay 100 ms
104
-  0x0A4,              // normal display
105
-  U8G_ESC_CS(0),      // disable chip
106
-  U8G_ESC_END         // end of sequence
114
+  U8G_ESC_DLY(100),           // delay 100 ms
115
+  ST7565_ALL_PIX(1),          // display all points, ST7565
116
+  U8G_ESC_DLY(100),           // delay 100 ms
117
+  U8G_ESC_DLY(100),           // delay 100 ms
118
+  ST7565_ALL_PIX(0),          // normal display
119
+  U8G_ESC_CS(0),              // disable chip
120
+  U8G_ESC_END                 // end of sequence
107 121
 };
108 122
 
109 123
 static const uint8_t u8g_dev_st7565_64128n_HAL_data_start[] PROGMEM = {
110
-  U8G_ESC_ADR(0),       // instruction mode
111
-  U8G_ESC_CS(1),        // enable chip
112
-  0x010,                // set upper 4 bit of the col adr to 0x10
113
-  0x000,                // set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N
114
-  U8G_ESC_END           // end of sequence
124
+  U8G_ESC_ADR(0),             // instruction mode
125
+  U8G_ESC_CS(1),              // enable chip
126
+  ST7565_COLUMN_ADR(0x00),    // high 4 bits to 0, low 4 bits to 0. Changed for DisplayTech 64128N
127
+  U8G_ESC_END                 // end of sequence
115 128
 };
116 129
 
117 130
 static const uint8_t u8g_dev_st7565_64128n_HAL_sleep_on[] PROGMEM = {
118
-  U8G_ESC_ADR(0),       // instruction mode
119
-  U8G_ESC_CS(1),        // enable chip
120
-  0x0AC,                // static indicator off
121
-  0x000,                // indicator register set (not sure if this is required)
122
-  0x0AE,                // display off
123
-  0x0A5,                // all points on
124
-  U8G_ESC_CS(0),        // disable chip, bugfix 12 nov 2014
125
-  U8G_ESC_END           // end of sequence
131
+  U8G_ESC_ADR(0),             // instruction mode
132
+  U8G_ESC_CS(1),              // enable chip
133
+  ST7565_SLEEP_MODE(),        // static indicator off
134
+  //0x000,                    // indicator register set (not sure if this is required)
135
+  ST7565_ON(0),               // display off
136
+  ST7565_ALL_PIX(1),          // all points on
137
+  U8G_ESC_CS(0),              // disable chip, bugfix 12 nov 2014
138
+  U8G_ESC_END                 // end of sequence
126 139
   };
127 140
 
128 141
 static const uint8_t u8g_dev_st7565_64128n_HAL_sleep_off[] PROGMEM = {
129
-  U8G_ESC_ADR(0),       // instruction mode
130
-  U8G_ESC_CS(1),        // enable chip
131
-  0x0A4,                // all points off
132
-  0x0AF,                // display on
133
-  U8G_ESC_DLY(50),      // delay 50 ms
134
-  U8G_ESC_CS(0),        // disable chip, bugfix 12 nov 2014
135
-  U8G_ESC_END           // end of sequence
142
+  U8G_ESC_ADR(0),             // instruction mode
143
+  U8G_ESC_CS(1),              // enable chip
144
+  ST7565_ALL_PIX(0),          // all points off
145
+  ST7565_ON(1),               // display on
146
+  U8G_ESC_DLY(50),            // delay 50 ms
147
+  U8G_ESC_CS(0),              // disable chip, bugfix 12 nov 2014
148
+  U8G_ESC_END                 // end of sequence
136 149
 };
137 150
 
138
-uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
151
+uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, const uint8_t msg, void *arg) {
139 152
   switch(msg) {
140 153
     case U8G_DEV_MSG_INIT:
141 154
       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
@@ -146,10 +159,9 @@ uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, vo
146 159
     case U8G_DEV_MSG_PAGE_NEXT: {
147 160
         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
148 161
         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_data_start);
149
-        u8g_WriteByte(u8g, dev, 0x0B0 | pb->p.page); /* select current page (ST7565R) */
162
+        u8g_WriteByte(u8g, dev, ST7565_PAGE_ADR(pb->p.page)); /* select current page (ST7565R) */
150 163
         u8g_SetAddress(u8g, dev, 1);           /* data mode */
151
-        if ( u8g_pb_WriteBuffer(pb, u8g, dev) == 0 )
152
-          return 0;
164
+        if (!u8g_pb_WriteBuffer(pb, u8g, dev)) return 0;
153 165
         u8g_SetChipSelect(u8g, dev, 0);
154 166
       }
155 167
       break;
@@ -170,7 +182,7 @@ uint8_t u8g_dev_st7565_64128n_HAL_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, vo
170 182
   return u8g_dev_pb8v1_base_fn(u8g, dev, msg, arg);
171 183
 }
172 184
 
173
-uint8_t u8g_dev_st7565_64128n_HAL_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
185
+uint8_t u8g_dev_st7565_64128n_HAL_2x_fn(u8g_t *u8g, u8g_dev_t *dev, const uint8_t msg, void *arg) {
174 186
   switch(msg) {
175 187
     case U8G_DEV_MSG_INIT:
176 188
       u8g_InitCom(u8g, dev, U8G_SPI_CLK_CYCLE_400NS);
@@ -182,13 +194,13 @@ uint8_t u8g_dev_st7565_64128n_HAL_2x_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg,
182 194
         u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
183 195
 
184 196
         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_data_start);
185
-        u8g_WriteByte(u8g, dev, 0x0B0 | (2*pb->p.page)); /* select current page (ST7565R) */
197
+        u8g_WriteByte(u8g, dev, ST7565_PAGE_ADR(2 * pb->p.page)); /* select current page (ST7565R) */
186 198
         u8g_SetAddress(u8g, dev, 1);           /* data mode */
187 199
         u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)pb->buf);
188 200
         u8g_SetChipSelect(u8g, dev, 0);
189 201
 
190 202
         u8g_WriteEscSeqP(u8g, dev, u8g_dev_st7565_64128n_HAL_data_start);
191
-        u8g_WriteByte(u8g, dev, 0x0B0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
203
+        u8g_WriteByte(u8g, dev, ST7565_PAGE_ADR(2 * pb->p.page + 1)); /* select current page (ST7565R) */
192 204
         u8g_SetAddress(u8g, dev, 1);           /* data mode */
193 205
         u8g_WriteSequence(u8g, dev, pb->width, (uint8_t *)(pb->buf)+pb->width);
194 206
         u8g_SetChipSelect(u8g, dev, 0);

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