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+/**
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+ * Marlin 3D Printer Firmware
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+ * Copyright (C) 2016, 2017 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
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+ *
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+ * Based on Sprinter and grbl.
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+ * Copyright (C) 2011 Camiel Gubbels / Erik van der Zalm
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+ *
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+ * This program is free software: you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation, either version 3 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
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+ *
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+ */
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+
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+#ifndef ULCDST7565_H
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+#define ULCDST7565_H
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+
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+#include "Marlin.h"
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+
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+#if ENABLED(U8GLIB_ST7565_64128N)
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+
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+
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+#define ST7565_CLK_PIN DOGLCD_SCK
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+#define ST7565_DAT_PIN DOGLCD_MOSI
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+#define ST7565_CS_PIN DOGLCD_CS
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+#define ST7565_A0_PIN DOGLCD_A0
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+
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+
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+
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+
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+
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+
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+#include <U8glib.h>
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+
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+#define WIDTH 128
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+#define HEIGHT 64
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+#define PAGE_HEIGHT 8
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+
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+//set optimization so ARDUINO optimizes this file
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+#pragma GCC optimize (3)
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+
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+// If you want you can define your own set of delays in Configuration.h
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+//#define ST7565_DELAY_1 DELAY_0_NOP
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+//#define ST7565_DELAY_2 DELAY_0_NOP
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+//#define ST7565_DELAY_3 DELAY_0_NOP
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+
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+/*
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+#define ST7565_DELAY_1 u8g_10MicroDelay()
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+#define ST7565_DELAY_2 u8g_10MicroDelay()
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+#define ST7565_DELAY_3 u8g_10MicroDelay()
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+*/
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+
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+#if F_CPU >= 20000000
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+ #define CPU_ST7565_DELAY_1 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_2 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_3 DELAY_1_NOP
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+#elif (MOTHERBOARD == BOARD_3DRAG) || (MOTHERBOARD == BOARD_K8200) || (MOTHERBOARD == BOARD_K8400)
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+ #define CPU_ST7565_DELAY_1 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_2 DELAY_3_NOP
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+ #define CPU_ST7565_DELAY_3 DELAY_0_NOP
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+#elif (MOTHERBOARD == BOARD_MINIRAMBO)
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+ #define CPU_ST7565_DELAY_1 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_2 DELAY_4_NOP
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+ #define CPU_ST7565_DELAY_3 DELAY_0_NOP
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+#elif (MOTHERBOARD == BOARD_RAMBO)
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+ #define CPU_ST7565_DELAY_1 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_2 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_3 DELAY_0_NOP
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+#elif F_CPU == 16000000
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+ #define CPU_ST7565_DELAY_1 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_2 DELAY_0_NOP
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+ #define CPU_ST7565_DELAY_3 DELAY_1_NOP
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+#else
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+ #error "No valid condition for delays in 'ultralcd_st7565_u8glib_VIKI.h'"
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+#endif
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+
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+#ifndef ST7565_DELAY_1
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+ #define ST7565_DELAY_1 CPU_ST7565_DELAY_1
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+#endif
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+#ifndef ST7565_DELAY_2
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+ #define ST7565_DELAY_2 CPU_ST7565_DELAY_2
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+#endif
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+#ifndef ST7565_DELAY_3
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+ #define ST7565_DELAY_3 CPU_ST7565_DELAY_3
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+#endif
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+
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+#define ST7565_SND_BIT \
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+ WRITE(ST7565_CLK_PIN, LOW); ST7565_DELAY_1; \
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+ WRITE(ST7565_DAT_PIN, val & 0x80); ST7565_DELAY_2; \
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+ WRITE(ST7565_CLK_PIN, HIGH); ST7565_DELAY_3; \
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+ WRITE(ST7565_CLK_PIN, LOW);\
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+ val <<= 1
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+
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+static void ST7565_SWSPI_SND_8BIT(uint8_t val) {
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+ ST7565_SND_BIT; // 1
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+ ST7565_SND_BIT; // 2
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+ ST7565_SND_BIT; // 3
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+ ST7565_SND_BIT; // 4
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+ ST7565_SND_BIT; // 5
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+ ST7565_SND_BIT; // 6
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+ ST7565_SND_BIT; // 7
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+ ST7565_SND_BIT; // 8
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+}
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+
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+#if defined(DOGM_SPI_DELAY_US) && DOGM_SPI_DELAY_US > 0
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+ #define U8G_DELAY delayMicroseconds(DOGM_SPI_DELAY_US)
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+#else
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+ #define U8G_DELAY u8g_10MicroDelay()
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+#endif
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+
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+#define ST7565_CS() { WRITE(ST7565_CS_PIN,1); U8G_DELAY; }
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+#define ST7565_NCS() { WRITE(ST7565_CS_PIN,0); }
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+#define ST7565_A0() { WRITE(ST7565_A0_PIN,1); U8G_DELAY; }
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+#define ST7565_NA0() { WRITE(ST7565_A0_PIN,0); }
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+#define ST7565_WRITE_BYTE(a) { ST7565_SWSPI_SND_8BIT((uint8_t)a); U8G_DELAY; }
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+#define ST7560_WriteSequence(count, pointer) { uint8_t *ptr = pointer; for (uint8_t i = 0; i < count; i++) {ST7565_SWSPI_SND_8BIT( *ptr++);} DELAY_10US; }
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+
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+
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+uint8_t u8g_dev_st7565_64128n_2x_VIKI_fn(u8g_t *u8g, u8g_dev_t *dev, uint8_t msg, void *arg) {
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+ switch (msg) {
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+ case U8G_DEV_MSG_INIT:
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+ { OUT_WRITE(ST7565_CS_PIN, LOW);
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+ OUT_WRITE(ST7565_DAT_PIN, LOW);
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+ OUT_WRITE(ST7565_CLK_PIN, LOW);
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+ OUT_WRITE(ST7565_A0_PIN, LOW);
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+
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+ ST7565_CS(); /* disable chip */
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+ ST7565_NA0(); /* instruction mode */
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+ ST7565_NCS(); /* enable chip */
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+
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+
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+ ST7565_WRITE_BYTE(0x0A2); /* 0x0a2: LCD bias 1/9 (according to Displaytech 64128N datasheet) */
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+ ST7565_WRITE_BYTE(0x0A0); /* Normal ADC Select (according to Displaytech 64128N datasheet) */
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+
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+ ST7565_WRITE_BYTE(0x0c8); /* common output mode: set scan direction normal operation/SHL Select; 0x0c0 --> SHL = 0; normal; 0x0c8 --> SHL = 1 */
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+ ST7565_WRITE_BYTE(0x040); /* Display start line for Displaytech 64128N */
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+
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+ ST7565_WRITE_BYTE(0x028 | 0x04); /* power control: turn on voltage converter */
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+// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
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+
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+ ST7565_WRITE_BYTE(0x028 | 0x06); /* power control: turn on voltage regulator */
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+// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
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+
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+ ST7565_WRITE_BYTE(0x028 | 0x07); /* power control: turn on voltage follower */
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+// U8G_ESC_DLY(50); /* delay 50 ms - hangs after a reset if used */
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+
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+ ST7565_WRITE_BYTE(0x010); /* Set V0 voltage resistor ratio. Setting for controlling brightness of Displaytech 64128N */
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+
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+ ST7565_WRITE_BYTE(0x0a6); /* display normal, bit val 0: LCD pixel off. */
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+
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+ ST7565_WRITE_BYTE(0x081); /* set contrast */
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+ ST7565_WRITE_BYTE(0x01e); /* Contrast value. Setting for controlling brightness of Displaytech 64128N */
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+
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+
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+ ST7565_WRITE_BYTE(0x0af); /* display on */
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+
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+ U8G_ESC_DLY(100); /* delay 100 ms */
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+ ST7565_WRITE_BYTE(0x0a5); /* display all points; ST7565 */
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+ U8G_ESC_DLY(100); /* delay 100 ms */
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+ U8G_ESC_DLY(100); /* delay 100 ms */
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+ ST7565_WRITE_BYTE(0x0a4); /* normal display */
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+ ST7565_CS(); /* disable chip */
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+ } /* end of sequence */
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+ break;
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+ case U8G_DEV_MSG_STOP:
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+ break;
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+ case U8G_DEV_MSG_PAGE_NEXT:
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+ { u8g_pb_t *pb = (u8g_pb_t *)(dev->dev_mem);
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+ ST7565_CS(); /* disable chip */
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+ ST7565_NA0(); /* instruction mode */
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+ ST7565_NCS(); /* enable chip */
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+ ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */
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+ ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
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+ /* end of sequence */
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+ ST7565_WRITE_BYTE(0x0b0 | (2*pb->p.page));; /* select current page (ST7565R) */
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+ ST7565_A0(); /* data mode */
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+ ST7560_WriteSequence( (uint8_t) pb->width, (uint8_t *)pb->buf);
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+ ST7565_CS(); /* disable chip */
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+ ST7565_NA0(); /* instruction mode */
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+ ST7565_NCS(); /* enable chip */
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+ ST7565_WRITE_BYTE(0x010); /* set upper 4 bit of the col adr to 0x10 */
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+ ST7565_WRITE_BYTE(0x000); /* set lower 4 bit of the col adr to 0x00. Changed for DisplayTech 64128N */
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+ /* end of sequence */
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+ ST7565_WRITE_BYTE(0x0b0 | (2*pb->p.page+1)); /* select current page (ST7565R) */
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+ ST7565_A0(); /* data mode */
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+ ST7560_WriteSequence( (uint8_t) pb->width, (uint8_t *)(pb->buf)+pb->width);
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+ ST7565_CS(); /* disable chip */
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+ }
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+ break;
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+ case U8G_DEV_MSG_CONTRAST:
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+ ST7565_NCS();
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+ ST7565_NA0(); /* instruction mode */
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+ ST7565_WRITE_BYTE(0x081);
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+ ST7565_WRITE_BYTE((*(uint8_t *)arg) >> 2);
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+ ST7565_CS(); /* disable chip */
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+ return 1;
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+ case U8G_DEV_MSG_SLEEP_ON:
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+ ST7565_NA0(); /* instruction mode */
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+ ST7565_NCS(); /* enable chip */
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+ ST7565_WRITE_BYTE(0x0ac); /* static indicator off */
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+ ST7565_WRITE_BYTE(0x000); /* indicator register set (not sure if this is required) */
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+ ST7565_WRITE_BYTE(0x0ae); /* display off */
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+ ST7565_WRITE_BYTE(0x0a5); /* all points on */
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+ ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */
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+ /* end of sequence */
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+ return 1;
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+ case U8G_DEV_MSG_SLEEP_OFF:
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+ ST7565_NA0(); /* instruction mode */
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+ ST7565_NCS(); /* enable chip */
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+ ST7565_WRITE_BYTE(0x0a4); /* all points off */
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+ ST7565_WRITE_BYTE(0x0af); /* display on */
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+ U8G_ESC_DLY(50); /* delay 50 ms */
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+ ST7565_CS(); /* disable chip , bugfix 12 nov 2014 */
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+ /* end of sequence */
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+ return 1;
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+ }
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+ return u8g_dev_pb16v1_base_fn(u8g, dev, msg, arg);
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+}
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+
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+uint8_t u8g_dev_st7565_64128n_2x_VIKI_buf[WIDTH*2] U8G_NOCOMMON ;
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+u8g_pb_t u8g_dev_st7565_64128n_2x_VIKI_pb = { {16, HEIGHT, 0, 0, 0}, WIDTH, u8g_dev_st7565_64128n_2x_VIKI_buf};
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+u8g_dev_t u8g_dev_st7565_64128n_2x_VIKI_sw_spi = { u8g_dev_st7565_64128n_2x_VIKI_fn, &u8g_dev_st7565_64128n_2x_VIKI_pb, &u8g_com_null_fn};
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+
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+
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+class U8GLIB_ST7565_64128n_2x_VIKI : public U8GLIB {
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+ public:
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+ U8GLIB_ST7565_64128n_2x_VIKI(uint8_t dummy)
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+ : U8GLIB(&u8g_dev_st7565_64128n_2x_VIKI_sw_spi)
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+ { }
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+ U8GLIB_ST7565_64128n_2x_VIKI(uint8_t sck, uint8_t mosi, uint8_t cs, uint8_t a0, uint8_t reset = U8G_PIN_NONE)
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+ : U8GLIB(&u8g_dev_st7565_64128n_2x_VIKI_sw_spi)
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+ { }
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+};
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+
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+
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+
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+#pragma GCC reset_options
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+
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+#endif // U8GLIB_ST7565
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+#endif // ULCDST7565_H
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Bob-the-Kuhn
6 years ago