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@@ -486,7 +486,7 @@
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486
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486
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487
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487
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static void spiRxBlockX(uint8_t* buf, uint32_t todo) {
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488
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488
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do {
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489
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- *buf++ = spiTransferRx(0xff);
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489
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+ *buf++ = spiTransferRx(0xFF);
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490
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490
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} while (--todo);
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491
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491
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}
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492
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492
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@@ -629,7 +629,7 @@
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629
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629
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bool spiInitMaded = false;
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630
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630
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631
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631
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void spiBegin() {
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632
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- if(spiInitMaded == false) {
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632
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+ if (spiInitMaded == false) {
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633
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633
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// Configure SPI pins
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634
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634
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PIO_Configure(
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635
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635
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g_APinDescription[SCK_PIN].pPort,
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@@ -681,8 +681,8 @@
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681
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681
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}
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682
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682
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683
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683
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void spiInit(uint8_t spiRate) {
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684
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- if(spiInitMaded == false) {
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685
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- if(spiRate > 6) spiRate = 1;
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684
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+ if (spiInitMaded == false) {
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685
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+ if (spiRate > 6) spiRate = 1;
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686
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686
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687
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687
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#if MB(ALLIGATOR)
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688
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688
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// Set SPI mode 1, clock, select not active after transfer, with delay between transfers
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@@ -789,7 +789,7 @@
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789
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789
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}
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790
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790
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791
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791
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// Read from SPI into buffer
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792
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- void spiRead(uint8_t*buf, uint16_t nbyte) {
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792
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+ void spiRead(uint8_t* buf, uint16_t nbyte) {
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793
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793
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if (nbyte-- == 0) return;
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794
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794
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795
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795
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for (int i = 0; i < nbyte; i++) {
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@@ -830,38 +830,37 @@
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830
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830
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#define SPI_MODE_2_DUE_HW 0
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831
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831
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#define SPI_MODE_3_DUE_HW 1
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832
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832
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833
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- void spiInit(uint8_t spiRate = 6 ) { // default to slowest rate if not specified)
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833
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+ void spiInit(uint8_t spiRate=6) { // Default to slowest rate if not specified)
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834
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834
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// 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
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835
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835
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int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
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836
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- if(spiRate > 6) spiRate = 1;
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836
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+ if (spiRate > 6) spiRate = 1;
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837
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837
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838
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- /* enable PIOA and SPI0 */
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838
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+ // Enable PIOA and SPI0
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839
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839
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REG_PMC_PCER0 = (1UL << ID_PIOA) | (1UL << ID_SPI0);
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840
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840
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841
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- /* disable PIO on A26 and A27 */
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841
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+ // Disable PIO on A26 and A27
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842
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842
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REG_PIOA_PDR = 0x0c000000;
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843
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843
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OUT_WRITE(SDSS, 1);
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844
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844
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845
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- /* reset SPI0 (from sam lib) */
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845
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+ // Reset SPI0 (from sam lib)
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846
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846
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SPI0->SPI_CR = SPI_CR_SPIDIS;
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847
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847
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SPI0->SPI_CR = SPI_CR_SWRST;
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848
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848
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SPI0->SPI_CR = SPI_CR_SWRST;
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849
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849
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SPI0->SPI_CR = SPI_CR_SPIEN;
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850
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850
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851
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-
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852
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- /* master mode, no fault detection, chip select 0 */
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853
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- SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PCSDEC | SPI_MR_MODFDIS;
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854
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-
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855
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- /* SPI mode 0, 8 Bit data transfer, baud rate */
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856
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- SPI0->SPI_CSR[0] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | SPI_MODE_0_DUE_HW;
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851
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+ // TMC2103 compatible setup
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852
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+ // Master mode, no fault detection, PCS bits in data written to TDR select CSR register
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853
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+ SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PS | SPI_MR_MODFDIS;
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854
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+ // SPI mode 0, 8 Bit data transfer, baud rate
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855
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+ SPI0->SPI_CSR[3] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | SPI_CSR_CSAAT | SPI_MODE_0_DUE_HW; // use same CSR as TMC2130
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857
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856
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}
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858
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857
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859
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858
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static uint8_t spiTransfer(uint8_t data) {
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860
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859
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861
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- /* wait until tx register is empty */
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860
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+ // Wait until tx register is empty
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862
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861
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while( (SPI0->SPI_SR & SPI_SR_TDRE) == 0 );
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863
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- /* send data */
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864
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- SPI0->SPI_TDR = (uint32_t)data; // | SPI_PCS(0xF);
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862
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+ // Send data
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863
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+ SPI0->SPI_TDR = (uint32_t)data | 0x00070000UL; // Add TMC2130 PCS bits to every byte
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865
|
864
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866
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865
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// wait for transmit register empty
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867
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866
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while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
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@@ -877,15 +876,14 @@
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877
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876
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}
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878
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877
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879
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878
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uint8_t spiRec() {
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880
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- uint8_t data = spiTransfer(0xff);
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879
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+ uint8_t data = spiTransfer(0xFF);
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881
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880
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return data;
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882
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881
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}
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883
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882
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|
884
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- void spiRead(uint8_t*buf, uint16_t nbyte) {
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|
883
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+ void spiRead(uint8_t* buf, uint16_t nbyte) {
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885
|
884
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if (nbyte == 0) return;
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886
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- for (int i = 0; i < nbyte; i++) {
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887
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- buf[i] = spiTransfer(0xff);
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888
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- }
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|
885
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+ for (int i = 0; i < nbyte; i++)
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|
886
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+ buf[i] = spiTransfer(0xFF);
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889
|
887
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}
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890
|
888
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|
891
|
889
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void spiSend(uint8_t data) {
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