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@@ -53,6 +53,7 @@
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53
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53
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// --------------------------------------------------------------------------
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54
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54
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55
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55
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#if ENABLED(SOFTWARE_SPI)
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56
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+
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56
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57
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// --------------------------------------------------------------------------
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57
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58
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// software SPI
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58
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59
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// --------------------------------------------------------------------------
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@@ -493,44 +494,77 @@
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493
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494
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static pfnSpiTxBlock spiTxBlock = spiTxBlockX;
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494
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495
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static pfnSpiRxBlock spiRxBlock = spiRxBlockX;
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495
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496
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496
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- void spiBegin() {
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497
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- SET_OUTPUT(SS_PIN);
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498
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- WRITE(SS_PIN, HIGH);
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499
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- SET_OUTPUT(SCK_PIN);
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500
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- SET_INPUT(MISO_PIN);
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501
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- SET_OUTPUT(MOSI_PIN);
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502
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- }
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497
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+ #if MB(ALLIGATOR) // control SDSS pin
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498
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+ void spiBegin() {
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499
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+ SET_OUTPUT(SS_PIN);
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500
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+ WRITE(SS_PIN, HIGH);
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501
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+ SET_OUTPUT(SCK_PIN);
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502
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+ SET_INPUT(MISO_PIN);
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503
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+ SET_OUTPUT(MOSI_PIN);
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504
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+ }
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503
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505
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504
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- uint8_t spiRec() {
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505
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- WRITE(SS_PIN, LOW);
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506
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- WRITE(MOSI_PIN, 1); /* Output 1s 1*/
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507
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- uint8_t b = spiTransferRx(0xFF);
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508
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- WRITE(SS_PIN, HIGH);
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509
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- return b;
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510
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- }
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506
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+ uint8_t spiRec() {
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507
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+ WRITE(SS_PIN, LOW);
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508
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+ WRITE(MOSI_PIN, 1); /* Output 1s 1*/
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509
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+ uint8_t b = spiTransferRx(0xFF);
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510
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+ WRITE(SS_PIN, HIGH);
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511
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+ return b;
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512
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+ }
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511
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513
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512
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- void spiRead(uint8_t* buf, uint16_t nbyte) {
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513
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- uint32_t todo = nbyte;
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514
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- if (todo == 0) return;
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514
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+ void spiRead(uint8_t* buf, uint16_t nbyte) {
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515
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+ uint32_t todo = nbyte;
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516
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+ if (todo == 0) return;
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515
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517
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516
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- WRITE(SS_PIN, LOW);
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517
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- WRITE(MOSI_PIN, 1); /* Output 1s 1*/
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518
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- spiRxBlock(buf,nbyte);
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519
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- WRITE(SS_PIN, HIGH);
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520
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- }
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518
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+ WRITE(SS_PIN, LOW);
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519
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+ WRITE(MOSI_PIN, 1); /* Output 1s 1*/
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520
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+ spiRxBlock(buf,nbyte);
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521
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+ WRITE(SS_PIN, HIGH);
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522
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+ }
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521
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523
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522
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- void spiSend(uint8_t b) {
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523
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- WRITE(SS_PIN, LOW);
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524
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- (void) spiTransferTx(b);
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525
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- WRITE(SS_PIN, HIGH);
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526
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- }
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524
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+ void spiSend(uint8_t b) {
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525
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+ WRITE(SS_PIN, LOW);
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526
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+ (void) spiTransferTx(b);
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|
527
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+ WRITE(SS_PIN, HIGH);
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528
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+ }
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527
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529
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|
528
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- void spiSendBlock(uint8_t token, const uint8_t* buf) {
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530
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+ void spiSendBlock(uint8_t token, const uint8_t* buf) {
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531
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+ WRITE(SS_PIN, LOW);
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532
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+ (void) spiTransferTx(token);
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533
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+ spiTxBlock(buf,512);
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534
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+ WRITE(SS_PIN, HIGH);
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535
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+
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536
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+ #else // let calling routine control SDSS
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537
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+ void spiBegin() {
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|
538
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+ SET_OUTPUT(SS_PIN);
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539
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+ SET_OUTPUT(SCK_PIN);
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540
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+ SET_INPUT(MISO_PIN);
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|
541
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+ SET_OUTPUT(MOSI_PIN);
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542
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+ }
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529
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543
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|
530
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- WRITE(SS_PIN, LOW);
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531
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- (void) spiTransferTx(token);
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532
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- spiTxBlock(buf,512);
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533
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- WRITE(SS_PIN, HIGH);
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544
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+ uint8_t spiRec() {
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|
545
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+ WRITE(MOSI_PIN, 1); /* Output 1s 1*/
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546
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+ uint8_t b = spiTransferRx(0xFF);
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|
547
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+ return b;
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|
548
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+ }
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|
549
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+
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|
550
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+ void spiRead(uint8_t* buf, uint16_t nbyte) {
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551
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+ uint32_t todo = nbyte;
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552
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+ if (todo == 0) return;
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553
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+
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|
554
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+ WRITE(MOSI_PIN, 1); /* Output 1s 1*/
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|
555
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+ spiRxBlock(buf,nbyte);
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|
556
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+ }
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|
557
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+
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|
558
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+ void spiSend(uint8_t b) {
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559
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+ (void) spiTransferTx(b);
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560
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+ }
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|
561
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+
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562
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+ void spiSendBlock(uint8_t token, const uint8_t* buf) {
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563
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+ (void) spiTransferTx(token);
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564
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+ spiTxBlock(buf,512);
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565
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+
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566
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+ #endif
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567
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+
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534
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568
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}
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535
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569
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536
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570
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/**
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@@ -566,7 +600,9 @@
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566
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600
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break;
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567
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601
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}
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568
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602
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|
569
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- WRITE(SS_PIN, HIGH);
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603
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+ #if MB(ALLIGATOR)
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604
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+ WRITE(SS_PIN, HIGH);
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605
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+ #endif
|
570
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606
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WRITE(MOSI_PIN, HIGH);
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571
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607
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WRITE(SCK_PIN, LOW);
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572
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608
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}
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@@ -574,211 +610,296 @@
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574
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610
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/** Begin SPI transaction, set clock, bit order, data mode */
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575
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611
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void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
|
576
|
612
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// TODO: to be implemented
|
577
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-
|
578
|
613
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}
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579
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614
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|
580
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615
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#pragma GCC reset_options
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581
|
616
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|
582
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617
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#else
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583
|
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- // --------------------------------------------------------------------------
|
584
|
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- // hardware SPI
|
585
|
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- // --------------------------------------------------------------------------
|
586
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- // 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
587
|
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- int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
|
588
|
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- bool spiInitMaded = false;
|
589
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-
|
590
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- void spiBegin() {
|
591
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- if(spiInitMaded == false) {
|
592
|
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- // Configure SPI pins
|
593
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- PIO_Configure(
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594
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- g_APinDescription[SCK_PIN].pPort,
|
595
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- g_APinDescription[SCK_PIN].ulPinType,
|
596
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- g_APinDescription[SCK_PIN].ulPin,
|
597
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- g_APinDescription[SCK_PIN].ulPinConfiguration);
|
598
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- PIO_Configure(
|
599
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- g_APinDescription[MOSI_PIN].pPort,
|
600
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- g_APinDescription[MOSI_PIN].ulPinType,
|
601
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- g_APinDescription[MOSI_PIN].ulPin,
|
602
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- g_APinDescription[MOSI_PIN].ulPinConfiguration);
|
603
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- PIO_Configure(
|
604
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- g_APinDescription[MISO_PIN].pPort,
|
605
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- g_APinDescription[MISO_PIN].ulPinType,
|
606
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- g_APinDescription[MISO_PIN].ulPin,
|
607
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- g_APinDescription[MISO_PIN].ulPinConfiguration);
|
608
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-
|
609
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- // set master mode, peripheral select, fault detection
|
610
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- SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
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611
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- SPI_Enable(SPI0);
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612
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-
|
613
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- #if MB(ALLIGATOR)
|
614
|
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- SET_OUTPUT(DAC0_SYNC);
|
615
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- #if EXTRUDERS > 1
|
616
|
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- SET_OUTPUT(DAC1_SYNC);
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617
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- WRITE(DAC1_SYNC, HIGH);
|
618
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- #endif
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619
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- SET_OUTPUT(SPI_EEPROM1_CS);
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620
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- SET_OUTPUT(SPI_EEPROM2_CS);
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621
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- SET_OUTPUT(SPI_FLASH_CS);
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622
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- WRITE(DAC0_SYNC, HIGH);
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623
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- WRITE(SPI_EEPROM1_CS, HIGH );
|
624
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- WRITE(SPI_EEPROM2_CS, HIGH );
|
625
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- WRITE(SPI_FLASH_CS, HIGH );
|
626
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- WRITE(SS_PIN, HIGH );
|
627
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- #endif // MB(ALLIGATOR)
|
628
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-
|
629
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- PIO_Configure(
|
630
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- g_APinDescription[SPI_PIN].pPort,
|
631
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- g_APinDescription[SPI_PIN].ulPinType,
|
632
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- g_APinDescription[SPI_PIN].ulPin,
|
633
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- g_APinDescription[SPI_PIN].ulPinConfiguration);
|
634
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- spiInit(1);
|
635
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- spiInitMaded = true;
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|
618
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+
|
|
619
|
+ #if MB(ALLIGATOR)
|
|
620
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+
|
|
621
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+ // slave selects controlled by SPI controller
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|
622
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+ // doesn't support changing SPI speeds for SD card
|
|
623
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+
|
|
624
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+ // --------------------------------------------------------------------------
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|
625
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+ // hardware SPI
|
|
626
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+ // --------------------------------------------------------------------------
|
|
627
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+ // 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
|
628
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+ int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
|
|
629
|
+ bool spiInitMaded = false;
|
|
630
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+
|
|
631
|
+ void spiBegin() {
|
|
632
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+ if(spiInitMaded == false) {
|
|
633
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+ // Configure SPI pins
|
|
634
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+ PIO_Configure(
|
|
635
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+ g_APinDescription[SCK_PIN].pPort,
|
|
636
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+ g_APinDescription[SCK_PIN].ulPinType,
|
|
637
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+ g_APinDescription[SCK_PIN].ulPin,
|
|
638
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+ g_APinDescription[SCK_PIN].ulPinConfiguration);
|
|
639
|
+ PIO_Configure(
|
|
640
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+ g_APinDescription[MOSI_PIN].pPort,
|
|
641
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+ g_APinDescription[MOSI_PIN].ulPinType,
|
|
642
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+ g_APinDescription[MOSI_PIN].ulPin,
|
|
643
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+ g_APinDescription[MOSI_PIN].ulPinConfiguration);
|
|
644
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+ PIO_Configure(
|
|
645
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+ g_APinDescription[MISO_PIN].pPort,
|
|
646
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+ g_APinDescription[MISO_PIN].ulPinType,
|
|
647
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+ g_APinDescription[MISO_PIN].ulPin,
|
|
648
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+ g_APinDescription[MISO_PIN].ulPinConfiguration);
|
|
649
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+
|
|
650
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+ // set master mode, peripheral select, fault detection
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|
651
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+ SPI_Configure(SPI0, ID_SPI0, SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_MR_PS);
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|
652
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+ SPI_Enable(SPI0);
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|
653
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+
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|
654
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+ #if MB(ALLIGATOR)
|
|
655
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+ SET_OUTPUT(DAC0_SYNC);
|
|
656
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+ #if EXTRUDERS > 1
|
|
657
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+ SET_OUTPUT(DAC1_SYNC);
|
|
658
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+ WRITE(DAC1_SYNC, HIGH);
|
|
659
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+ #endif
|
|
660
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+ SET_OUTPUT(SPI_EEPROM1_CS);
|
|
661
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+ SET_OUTPUT(SPI_EEPROM2_CS);
|
|
662
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+ SET_OUTPUT(SPI_FLASH_CS);
|
|
663
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+ WRITE(DAC0_SYNC, HIGH);
|
|
664
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+ WRITE(SPI_EEPROM1_CS, HIGH );
|
|
665
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+ WRITE(SPI_EEPROM2_CS, HIGH );
|
|
666
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+ WRITE(SPI_FLASH_CS, HIGH );
|
|
667
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+ WRITE(SS_PIN, HIGH );
|
|
668
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+ #endif // MB(ALLIGATOR)
|
|
669
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+
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|
670
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+ OUT_WRITE(SDSS,0);
|
|
671
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+
|
|
672
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+ PIO_Configure(
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|
673
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+ g_APinDescription[SPI_PIN].pPort,
|
|
674
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+ g_APinDescription[SPI_PIN].ulPinType,
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|
675
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+ g_APinDescription[SPI_PIN].ulPin,
|
|
676
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+ g_APinDescription[SPI_PIN].ulPinConfiguration);
|
|
677
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+
|
|
678
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+ spiInit(1);
|
|
679
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+ spiInitMaded = true;
|
|
680
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+ }
|
636
|
681
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}
|
637
|
|
- }
|
638
|
682
|
|
639
|
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- void spiInit(uint8_t spiRate) {
|
640
|
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- if(spiInitMaded == false) {
|
641
|
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- if(spiRate > 6) spiRate = 1;
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|
683
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+ void spiInit(uint8_t spiRate) {
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|
684
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+ if(spiInitMaded == false) {
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|
685
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+ if(spiRate > 6) spiRate = 1;
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|
686
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+
|
|
687
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+ #if MB(ALLIGATOR)
|
|
688
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+ // Set SPI mode 1, clock, select not active after transfer, with delay between transfers
|
|
689
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+ SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
|
|
690
|
+ SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
|
691
|
+ SPI_CSR_DLYBCT(1));
|
|
692
|
+ // Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
|
693
|
+ SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
|
|
694
|
+ SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
|
695
|
+ SPI_CSR_DLYBCT(1));
|
|
696
|
+ #endif//MB(ALLIGATOR)
|
642
|
697
|
|
643
|
|
- #if MB(ALLIGATOR)
|
644
|
|
- // Set SPI mode 1, clock, select not active after transfer, with delay between transfers
|
645
|
|
- SPI_ConfigureNPCS(SPI0, SPI_CHAN_DAC,
|
646
|
|
- SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
647
|
|
- SPI_CSR_DLYBCT(1));
|
648
|
698
|
// Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
649
|
|
- SPI_ConfigureNPCS(SPI0, SPI_CHAN_EEPROM1, SPI_CSR_NCPHA |
|
|
699
|
+ SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
|
650
|
700
|
SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
651
|
701
|
SPI_CSR_DLYBCT(1));
|
652
|
|
- #endif//MB(ALLIGATOR)
|
653
|
|
-
|
654
|
|
- // Set SPI mode 0, clock, select not active after transfer, with delay between transfers
|
655
|
|
- SPI_ConfigureNPCS(SPI0, SPI_CHAN, SPI_CSR_NCPHA |
|
656
|
|
- SPI_CSR_CSAAT | SPI_CSR_SCBR(spiDueDividors[spiRate]) |
|
657
|
|
- SPI_CSR_DLYBCT(1));
|
658
|
|
- SPI_Enable(SPI0);
|
659
|
|
- spiInitMaded = true;
|
|
702
|
+ SPI_Enable(SPI0);
|
|
703
|
+ spiInitMaded = true;
|
|
704
|
+ }
|
660
|
705
|
}
|
661
|
|
- }
|
662
|
706
|
|
663
|
|
- // Write single byte to SPI
|
664
|
|
- void spiSend(byte b) {
|
665
|
|
- // write byte with address and end transmission flag
|
666
|
|
- SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
667
|
|
- // wait for transmit register empty
|
668
|
|
- while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
669
|
|
- // wait for receive register
|
670
|
|
- while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
671
|
|
- // clear status
|
672
|
|
- SPI0->SPI_RDR;
|
673
|
|
- //delayMicroseconds(1U);
|
674
|
|
- }
|
675
|
|
-
|
676
|
|
- void spiSend(const uint8_t* buf, size_t n) {
|
677
|
|
- if (n == 0) return;
|
678
|
|
- for (size_t i = 0; i < n - 1; i++) {
|
679
|
|
- SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
707
|
+ // Write single byte to SPI
|
|
708
|
+ void spiSend(byte b) {
|
|
709
|
+ // write byte with address and end transmission flag
|
|
710
|
+ SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
|
711
|
+ // wait for transmit register empty
|
680
|
712
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
713
|
+ // wait for receive register
|
681
|
714
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
715
|
+ // clear status
|
682
|
716
|
SPI0->SPI_RDR;
|
683
|
717
|
//delayMicroseconds(1U);
|
684
|
718
|
}
|
685
|
|
- spiSend(buf[n - 1]);
|
686
|
|
- }
|
687
|
719
|
|
688
|
|
- void spiSend(uint32_t chan, byte b) {
|
689
|
|
- uint8_t dummy_read = 0;
|
690
|
|
- // wait for transmit register empty
|
691
|
|
- while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
692
|
|
- // write byte with address and end transmission flag
|
693
|
|
- SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
694
|
|
- // wait for receive register
|
695
|
|
- while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
696
|
|
- // clear status
|
697
|
|
- while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
698
|
|
- dummy_read = SPI0->SPI_RDR;
|
699
|
|
- UNUSED(dummy_read);
|
700
|
|
- }
|
|
720
|
+ void spiSend(const uint8_t* buf, size_t n) {
|
|
721
|
+ if (n == 0) return;
|
|
722
|
+ for (size_t i = 0; i < n - 1; i++) {
|
|
723
|
+ SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
724
|
+ while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
725
|
+ while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
726
|
+ SPI0->SPI_RDR;
|
|
727
|
+ //delayMicroseconds(1U);
|
|
728
|
+ }
|
|
729
|
+ spiSend(buf[n - 1]);
|
|
730
|
+ }
|
701
|
731
|
|
702
|
|
- void spiSend(uint32_t chan, const uint8_t* buf, size_t n) {
|
703
|
|
- uint8_t dummy_read = 0;
|
704
|
|
- if (n == 0) return;
|
705
|
|
- for (int i = 0; i < (int)n - 1; i++) {
|
|
732
|
+ void spiSend(uint32_t chan, byte b) {
|
|
733
|
+ uint8_t dummy_read = 0;
|
|
734
|
+ // wait for transmit register empty
|
706
|
735
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
707
|
|
- SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(chan);
|
|
736
|
+ // write byte with address and end transmission flag
|
|
737
|
+ SPI0->SPI_TDR = (uint32_t)b | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
|
738
|
+ // wait for receive register
|
708
|
739
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
740
|
+ // clear status
|
709
|
741
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
710
|
742
|
dummy_read = SPI0->SPI_RDR;
|
711
|
743
|
UNUSED(dummy_read);
|
712
|
744
|
}
|
713
|
|
- spiSend(chan, buf[n - 1]);
|
714
|
|
- }
|
715
|
|
-
|
716
|
|
- // Read single byte from SPI
|
717
|
|
- uint8_t spiRec() {
|
718
|
|
- // write dummy byte with address and end transmission flag
|
719
|
|
- SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
720
|
|
- // wait for transmit register empty
|
721
|
|
- while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
722
|
|
-
|
723
|
|
- // wait for receive register
|
724
|
|
- while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
725
|
|
- // get byte from receive register
|
726
|
|
- //delayMicroseconds(1U);
|
727
|
|
- return SPI0->SPI_RDR;
|
728
|
|
- }
|
729
|
745
|
|
730
|
|
- uint8_t spiRec(uint32_t chan) {
|
731
|
|
- uint8_t spirec_tmp;
|
732
|
|
- // wait for transmit register empty
|
733
|
|
- while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
734
|
|
- while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
735
|
|
- spirec_tmp = SPI0->SPI_RDR;
|
736
|
|
- UNUSED(spirec_tmp);
|
737
|
|
-
|
738
|
|
- // write dummy byte with address and end transmission flag
|
739
|
|
- SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
740
|
|
-
|
741
|
|
- // wait for receive register
|
742
|
|
- while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
743
|
|
- // get byte from receive register
|
744
|
|
- return SPI0->SPI_RDR;
|
745
|
|
- }
|
|
746
|
+ void spiSend(uint32_t chan, const uint8_t* buf, size_t n) {
|
|
747
|
+ uint8_t dummy_read = 0;
|
|
748
|
+ if (n == 0) return;
|
|
749
|
+ for (int i = 0; i < (int)n - 1; i++) {
|
|
750
|
+ while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
751
|
+ SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(chan);
|
|
752
|
+ while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
753
|
+ while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
|
754
|
+ dummy_read = SPI0->SPI_RDR;
|
|
755
|
+ UNUSED(dummy_read);
|
|
756
|
+ }
|
|
757
|
+ spiSend(chan, buf[n - 1]);
|
|
758
|
+ }
|
746
|
759
|
|
747
|
|
- // Read from SPI into buffer
|
748
|
|
- void spiRead(uint8_t*buf, uint16_t nbyte) {
|
749
|
|
- if (nbyte-- == 0) return;
|
|
760
|
+ // Read single byte from SPI
|
|
761
|
+ uint8_t spiRec() {
|
|
762
|
+ // write dummy byte with address and end transmission flag
|
|
763
|
+ SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN) | SPI_TDR_LASTXFER;
|
|
764
|
+ // wait for transmit register empty
|
|
765
|
+ while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
750
|
766
|
|
751
|
|
- for (int i = 0; i < nbyte; i++) {
|
752
|
|
- //while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
753
|
|
- SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
|
|
767
|
+ // wait for receive register
|
754
|
768
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
755
|
|
- buf[i] = SPI0->SPI_RDR;
|
|
769
|
+ // get byte from receive register
|
756
|
770
|
//delayMicroseconds(1U);
|
|
771
|
+ return SPI0->SPI_RDR;
|
757
|
772
|
}
|
758
|
|
- buf[nbyte] = spiRec();
|
759
|
|
- }
|
760
|
773
|
|
761
|
|
- // Write from buffer to SPI
|
762
|
|
- void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
763
|
|
- SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
|
764
|
|
- while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
765
|
|
- //while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
766
|
|
- //SPI0->SPI_RDR;
|
767
|
|
- for (int i = 0; i < 511; i++) {
|
768
|
|
- SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
774
|
+ uint8_t spiRec(uint32_t chan) {
|
|
775
|
+ uint8_t spirec_tmp;
|
|
776
|
+ // wait for transmit register empty
|
769
|
777
|
while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
778
|
+ while ((SPI0->SPI_SR & SPI_SR_RDRF) == 1)
|
|
779
|
+ spirec_tmp = SPI0->SPI_RDR;
|
|
780
|
+ UNUSED(spirec_tmp);
|
|
781
|
+
|
|
782
|
+ // write dummy byte with address and end transmission flag
|
|
783
|
+ SPI0->SPI_TDR = 0x000000FF | SPI_PCS(chan) | SPI_TDR_LASTXFER;
|
|
784
|
+
|
|
785
|
+ // wait for receive register
|
770
|
786
|
while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
771
|
|
- SPI0->SPI_RDR;
|
772
|
|
- //delayMicroseconds(1U);
|
|
787
|
+ // get byte from receive register
|
|
788
|
+ return SPI0->SPI_RDR;
|
773
|
789
|
}
|
774
|
|
- spiSend(buf[511]);
|
775
|
|
- }
|
776
|
790
|
|
777
|
|
- /** Begin SPI transaction, set clock, bit order, data mode */
|
778
|
|
- void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
|
779
|
|
- // TODO: to be implemented
|
780
|
|
- }
|
|
791
|
+ // Read from SPI into buffer
|
|
792
|
+ void spiRead(uint8_t*buf, uint16_t nbyte) {
|
|
793
|
+ if (nbyte-- == 0) return;
|
|
794
|
+
|
|
795
|
+ for (int i = 0; i < nbyte; i++) {
|
|
796
|
+ //while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
797
|
+ SPI0->SPI_TDR = 0x000000FF | SPI_PCS(SPI_CHAN);
|
|
798
|
+ while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
799
|
+ buf[i] = SPI0->SPI_RDR;
|
|
800
|
+ //delayMicroseconds(1U);
|
|
801
|
+ }
|
|
802
|
+ buf[nbyte] = spiRec();
|
|
803
|
+ }
|
|
804
|
+
|
|
805
|
+ // Write from buffer to SPI
|
|
806
|
+ void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
807
|
+ SPI0->SPI_TDR = (uint32_t)token | SPI_PCS(SPI_CHAN);
|
|
808
|
+ while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
809
|
+ //while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
810
|
+ //SPI0->SPI_RDR;
|
|
811
|
+ for (int i = 0; i < 511; i++) {
|
|
812
|
+ SPI0->SPI_TDR = (uint32_t)buf[i] | SPI_PCS(SPI_CHAN);
|
|
813
|
+ while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
814
|
+ while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
815
|
+ SPI0->SPI_RDR;
|
|
816
|
+ //delayMicroseconds(1U);
|
|
817
|
+ }
|
|
818
|
+ spiSend(buf[511]);
|
|
819
|
+ }
|
|
820
|
+
|
|
821
|
+ /** Begin SPI transaction, set clock, bit order, data mode */
|
|
822
|
+ void spiBeginTransaction(uint32_t spiClock, uint8_t bitOrder, uint8_t dataMode) {
|
|
823
|
+ // TODO: to be implemented
|
|
824
|
+ }
|
|
825
|
+
|
|
826
|
+ #else // U8G compatible hardware SPI
|
|
827
|
+
|
|
828
|
+ void spiInit(uint8_t spiRate = 6 ) { // default to slowest rate if not specified)
|
|
829
|
+ // 8.4 MHz, 4 MHz, 2 MHz, 1 MHz, 0.5 MHz, 0.329 MHz, 0.329 MHz
|
|
830
|
+ int spiDueDividors[] = { 10, 21, 42, 84, 168, 255, 255 };
|
|
831
|
+ if(spiRate > 6) spiRate = 1;
|
|
832
|
+
|
|
833
|
+ /* enable PIOA and SPI0 */
|
|
834
|
+ REG_PMC_PCER0 = (1UL << ID_PIOA) | (1UL << ID_SPI0);
|
|
835
|
+
|
|
836
|
+ /* disable PIO on A26 and A27 */
|
|
837
|
+ REG_PIOA_PDR = 0x0c000000;
|
|
838
|
+ OUT_WRITE(SDSS, 1);
|
|
839
|
+
|
|
840
|
+ /* reset SPI0 (from sam lib) */
|
|
841
|
+ SPI0->SPI_CR = SPI_CR_SPIDIS;
|
|
842
|
+ SPI0->SPI_CR = SPI_CR_SWRST;
|
|
843
|
+ SPI0->SPI_CR = SPI_CR_SWRST;
|
|
844
|
+ SPI0->SPI_CR = SPI_CR_SPIEN;
|
|
845
|
+
|
|
846
|
+
|
|
847
|
+ /* master mode, no fault detection, chip select 0 */
|
|
848
|
+ SPI0->SPI_MR = SPI_MR_MSTR | SPI_MR_PCSDEC | SPI_MR_MODFDIS;
|
|
849
|
+
|
|
850
|
+ /* SPI mode 0, 8 Bit data transfer, baud rate */
|
|
851
|
+ SPI0->SPI_CSR[0] = SPI_CSR_SCBR(spiDueDividors[spiRate]) | 1;
|
|
852
|
+ }
|
|
853
|
+
|
|
854
|
+ static uint8_t spiTransfer(uint8_t data) {
|
|
855
|
+
|
|
856
|
+ /* wait until tx register is empty */
|
|
857
|
+ while( (SPI0->SPI_SR & SPI_SR_TDRE) == 0 );
|
|
858
|
+ /* send data */
|
|
859
|
+ SPI0->SPI_TDR = (uint32_t)data; // | SPI_PCS(0xF);
|
|
860
|
+
|
|
861
|
+ // wait for transmit register empty
|
|
862
|
+ while ((SPI0->SPI_SR & SPI_SR_TDRE) == 0);
|
|
863
|
+
|
|
864
|
+ // wait for receive register
|
|
865
|
+ while ((SPI0->SPI_SR & SPI_SR_RDRF) == 0);
|
|
866
|
+ // get byte from receive register
|
|
867
|
+ return SPI0->SPI_RDR;
|
|
868
|
+ }
|
|
869
|
+
|
|
870
|
+ void spiBegin() {
|
|
871
|
+ spiInit();
|
|
872
|
+ }
|
|
873
|
+
|
|
874
|
+ uint8_t spiRec() {
|
|
875
|
+ uint8_t data = spiTransfer(0xff);
|
|
876
|
+ return data;
|
|
877
|
+ }
|
|
878
|
+
|
|
879
|
+ void spiRead(uint8_t*buf, uint16_t nbyte) {
|
|
880
|
+ if (nbyte == 0) return;
|
|
881
|
+ for (int i = 0; i < nbyte; i++) {
|
|
882
|
+ buf[i] = spiTransfer(0xff);
|
|
883
|
+ }
|
|
884
|
+ }
|
|
885
|
+
|
|
886
|
+ void spiSend(uint8_t data) {
|
|
887
|
+ spiTransfer(data);
|
|
888
|
+ }
|
|
889
|
+
|
|
890
|
+ void spiSend(const uint8_t* buf, size_t n) {
|
|
891
|
+ if (n == 0) return;
|
|
892
|
+ for (uint16_t i = 0; i < n; i++)
|
|
893
|
+ spiTransfer(buf[i]);
|
|
894
|
+ }
|
781
|
895
|
|
|
896
|
+ void spiSendBlock(uint8_t token, const uint8_t* buf) {
|
|
897
|
+ spiTransfer(token);
|
|
898
|
+ for (uint16_t i = 0; i < 512; i++)
|
|
899
|
+ spiTransfer(buf[i]);
|
|
900
|
+ }
|
|
901
|
+
|
|
902
|
+ #endif //MB(ALLIGATOR)
|
782
|
903
|
#endif // ENABLED(SOFTWARE_SPI)
|
783
|
904
|
|
784
|
905
|
#endif // ARDUINO_ARCH_SAM
|