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Fix SKR/GTR PeripheralPins.c (#17937) 

* Add a separate GTR board/variant.
* Revert SKR Pro MOSI (before 248b7dfa59).
Scott Lahteine vor 4 Jahren
Ursprung
98fdc67f1d
Commit
a06a0c5b88
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9 geänderte Dateien mit 1320 neuen und 14 gelöschten Zeilen
Geteilte Ansicht Diff-Statistik anzeigen
  1. 46
    0
      buildroot/share/PlatformIO/boards/BigTree_GTR_v1.json
  2. 373
    0
      buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/PeripheralPins.c
  3. 50
    0
      buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/PinNamesVar.h
  4. 52
    0
      buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/hal_conf_extra.h
  5. 204
    0
      buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/ldscript.ld
  6. 260
    0
      buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/variant.cpp
  7. 322
    0
      buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/variant.h
  8. 12
    13
      buildroot/share/PlatformIO/variants/BIGTREE_SKR_PRO_1v1/PeripheralPins.c
  9. 1
    1
      platformio.ini

+ 46
- 0
buildroot/share/PlatformIO/boards/BigTree_GTR_v1.json Datei anzeigen 

@@ -0,0 +1,46 @@
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+{
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+  "build": {
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+    "core": "stm32",
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+    "cpu": "cortex-m4",
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+    "extra_flags": "-DSTM32F4 -DSTM32F407xx -DSTM32F40_41xxx",
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+    "f_cpu": "168000000L",
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+    "hwids": [
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+      [
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+        "0x1EAF",
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+        "0x0003"
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+      ],
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+      [
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+        "0x0483",
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+        "0x3748"
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+      ]
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+    ],
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+    "mcu": "stm32f407zgt6",
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+    "variant": "BIGTREE_GTR_V1"
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+  },
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+  "debug": {
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+    "jlink_device": "STM32F407ZG",
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+    "openocd_target": "stm32f4x",
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+    "svd_path": "STM32F40x.svd"
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+  },
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+  "frameworks": [
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+    "arduino"
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+  ],
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+  "name": "STM32F407ZG (192k RAM. 1024k Flash)",
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+  "upload": {
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+    "disable_flushing": false,
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+    "maximum_ram_size": 196608,
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+    "maximum_size": 1048576,
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+    "protocol": "stlink",
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+    "protocols": [
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+      "stlink",
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+      "dfu",
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+      "jlink"
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+    ],
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+    "offset_address": "0x8008000",
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+    "require_upload_port": true,
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+    "use_1200bps_touch": false,
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+    "wait_for_upload_port": false
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+  },
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+  "url": "http://www.st.com/en/microcontrollers/stm32f407zg.html",
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+  "vendor": "Generic"
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+}

+ 373
- 0
buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/PeripheralPins.c Datei anzeigen 

@@ -0,0 +1,373 @@
1 
+/*
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+ *******************************************************************************
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+ * Copyright (c) 2019, STMicroelectronics
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ *
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+ * 1. Redistributions of source code must retain the above copyright notice,
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+ *    this list of conditions and the following disclaimer.
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+ * 2. Redistributions in binary form must reproduce the above copyright notice,
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+ *    this list of conditions and the following disclaimer in the documentation
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+ *    and/or other materials provided with the distribution.
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+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
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+ *    may be used to endorse or promote products derived from this software
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+ *    without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ *******************************************************************************
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+ * Automatically generated from STM32F407Z(E-G)Tx.xml
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+ */
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+#include <Arduino.h>
32 
+#include <PeripheralPins.h>
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+
34 
+/* =====
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+ * Note: Commented lines are alternative possibilities which are not used by default.
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+ *       If you change them, you should know what you're doing first.
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+ * =====
38 
+ */
39 
+
40 
+//*** ADC ***
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+
42 
+#ifdef HAL_ADC_MODULE_ENABLED
43 
+const PinMap PinMap_ADC[] = {
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+  {PA_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0      E0_DIR
45 
+  {PA_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1      BLTOUCH_2
46 
+  {PA_2,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2      BLTOUCH_4
47 
+  {PA_3,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3      E1_EN
48 
+  {PA_4,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4      TF_SS
49 
+  {PA_5,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5      TF_SCLK
50 
+  {PA_6,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6      TF_MISO
51 
+  {PA_7,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7      LED
52 
+  {PB_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8      HEATER2
53 
+  {PB_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9      HEATER0
54 
+  {PC_0,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10    Z_EN
55 
+  {PC_1,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11    EXP_14
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+  {PC_2,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12    Z_DIR
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+  {PC_3,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13    E0_EN
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+  {PC_4,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14    EXP_8
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+  {PC_5,  ADC1,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15    EXP_7
60 
+
61 
+  #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio, 24 ADC
62 
+    {PF_3,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_IN9    TH_0
63 
+    {PF_4,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_IN14  TH_1
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+    {PF_5,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_IN15  TH_2
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+    {PF_6,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_IN4    TH_3
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+    {PF_7,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_IN5    EXP_13
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+    {PF_8,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_IN6    EXP_3
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+    {PF_9,  ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_IN7    EXP_6
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+    {PF_10, ADC3,  STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_IN8    EXP_5
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+  #endif
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+  {NC,    NP,    0}
72 
+};
73 
+#endif
74 
+
75 
+//*** DAC ***
76 
+
77 
+#ifdef HAL_DAC_MODULE_ENABLED
78 
+const PinMap PinMap_DAC[] = {
79 
+  {PA_4,  DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
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+  {PA_5,  DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
81 
+  {NC,    NP,    0}
82 
+};
83 
+#endif
84 
+
85 
+//*** I2C ***
86 
+
87 
+#ifdef HAL_I2C_MODULE_ENABLED
88 
+const PinMap PinMap_I2C_SDA[] = {
89 
+  {PB_7,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
90 
+  {PB_9,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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+  {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
92 
+  {PC_9,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
93 
+  #if STM32F4X_PIN_NUM >= 144   // 144 pins mcu, 114 gpio
94 
+    #if STM32F4X_PIN_NUM >= 176
95 
+      {PH_5,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
96 
+      {PH_8,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
97 
+    #else
98 
+      {PF_0,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
99 
+    #endif
100 
+  #endif
101 
+  {NC,    NP,    0}
102 
+};
103 
+#endif
104 
+
105 
+#ifdef HAL_I2C_MODULE_ENABLED
106 
+const PinMap PinMap_I2C_SCL[] = {
107 
+  {PA_8,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
108 
+  {PB_6,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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+  {PB_8,  I2C1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
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+  {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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+  #if STM32F4X_PIN_NUM >= 144   // 144 pins mcu, 114 gpio
112 
+    #if STM32F4X_PIN_NUM >= 176
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+      //{PF_1,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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+      {PH_4,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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+      {PH_7,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
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+    #else
117 
+      {PF_1,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
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+    #endif
119 
+  #endif
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+  {NC,    NP,    0}
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+};
122 
+#endif
123 
+
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+//*** PWM ***
125 
+
126 
+#ifdef HAL_TIM_MODULE_ENABLED
127 
+const PinMap PinMap_PWM[] = {
128 
+  {PB_1,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4    HEATER0
129 
+  {PD_14, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3    HEATER1
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+  {PB_0,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3    HEATER2
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+  {PD_12, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1    BED
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+  {PC_8,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3    FAN0
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+  {PE_5,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1    FAN1
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+  {PE_6,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2    FAN2
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+  {PC_9,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4    EXTENSION1-4
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+  {PA_1,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2    BL-TOUCH-SERVO
137 
+
138 
+  // These pins have been defined for something else on the board but they MIGHT be
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+  // used by the user as PWM pins if they aren't used for their primary purpose.
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+  {PC_6,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1    ESP8266 connector. Available if 8266 isn't used
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+  {PC_7,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2    ESP8266 connector. Available if 8266 isn't used
142 
+  {PB_7,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2    I2C connector, SDA pin. Available if I2C isn't used.
143 
+                                                                                       // TIM5_CH1    is used by the Servo Library
144 
+  {PA_2,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3    BL-TOUCH port. Available if Z_MIN_PROBE_USES_Z_MIN_ENDSTOP_PIN
145 
+
146 
+  /**
147 
+   * Unused by specifications on SKR-Pro.
148 
+   * Uncomment the corresponding line if you want to have HardwarePWM on some pins.
149 
+   * WARNING: check timers' usage first to avoid conflicts.
150 
+   * If you don't know what you're doing leave things as they are or you WILL break something (including hardware)
151 
+   * If you alter this section DO NOT report bugs to Marlin team since they are most likely caused by you. Thank you.
152 
+   */
153 
+  //{PA_0,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
154 
+  //{PA_0,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
155 
+  {PA_1,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2  BLTOUCH is a "servo"
156 
+  {PA_2,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3  BLTOUCH is a "servo"
157 
+  //{PA_1,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
158 
+  //{PA_2,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
159 
+  //{PA_2,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
160 
+  //{PA_3,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
161 
+  //{PA_3,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4
162 
+  //{PA_3,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
163 
+  //{PA_5,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
164 
+  //{PA_5,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
165 
+  //{PA_6,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
166 
+  //{PA_6,  TIM13,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
167 
+  //{PA_7,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
168 
+  //{PA_7,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
169 
+  //{PA_7,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N
170 
+  //{PA_7,  TIM14,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
171 
+  //{PA_8,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
172 
+  //{PA_9,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
173 
+  //{PA_10, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
174 
+  //{PA_11, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
175 
+  //{PA_15, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
176 
+  //{PB_0,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
177 
+  //{PB_0,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
178 
+  //{PB_1,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
179 
+  //{PB_1,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
180 
+  //{PB_3,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
181 
+  //{PB_4,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
182 
+  //{PB_5,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
183 
+  //{PB_6,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
184 
+  //{PB_8,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
185 
+  //{PB_8,  TIM10,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
186 
+  //{PB_9,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
187 
+  //{PB_9,  TIM11,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
188 
+  //{PB_10, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
189 
+  {PB_11, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
190 
+  //{PB_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
191 
+  //{PB_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
192 
+  //{PB_14, TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
193 
+  //{PB_14, TIM12,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
194 
+  //{PB_15, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
195 
+  //{PB_15, TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N
196 
+  //{PB_15, TIM12,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2
197 
+  //{PC_6,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
198 
+  //{PC_7,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
199 
+  //{PC_7,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
200 
+  //{PC_8,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
201 
+  //{PC_9,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
202 
+  {PD_13, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
203 
+  {PD_15, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
204 
+  //{PE_8,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
205 
+  {PE_9,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
206 
+  //{PE_10, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
207 
+  {PE_11, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
208 
+  //{PE_12, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
209 
+  {PE_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
210 
+  {PE_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
211 
+  #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
212 
+    //{PF_6,  TIM10,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
213 
+    //{PF_7,  TIM11,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
214 
+    //{PF_8,  TIM13,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1
215 
+    //{PF_9,  TIM14,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1
216 
+  #endif
217 
+  #if STM32F4X_PIN_NUM >= 176  //176 pins mcu, 140 gpio
218 
+    {PH_10,  TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
219 
+    {PH_6,  TIM12,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1
220 
+    //{PH_11,  TIM5,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
221 
+    {PI_5,  TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1
222 
+    {PI_6,  TIM8,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
223 
+  #endif
224 
+  {NC,    NP,    0}
225 
+};
226 
+#endif
227 
+
228 
+//*** SERIAL ***
229 
+
230 
+#ifdef HAL_UART_MODULE_ENABLED
231 
+const PinMap PinMap_UART_TX[] = {
232 
+  {PA_9,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
233 
+  {PD_8,  USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
234 
+  {PC_6,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
235 
+  #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
236 
+    //{PG_14, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
237 
+  #endif
238 
+  //{PB_6,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
239 
+  //{PA_2,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
240 
+  //{PD_5,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
241 
+  //{PB_10, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
242 
+  //{PC_10, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
243 
+  //{PA_0,  UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
244 
+  //{PC_10, UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
245 
+  //{PC_12, UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
246 
+  {NC,    NP,    0}
247 
+};
248 
+
249 
+const PinMap PinMap_UART_RX[] = {
250 
+  {PA_10, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
251 
+  {PD_9,  USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
252 
+  {PC_7,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
253 
+  //{PA_1,  UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
254 
+  //{PA_3,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
255 
+  //{PB_7,  USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
256 
+  //{PB_11, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
257 
+  //{PC_11, UART4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
258 
+  //{PC_11, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
259 
+  //{PD_2,  UART5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
260 
+  //{PD_6,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
261 
+  #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
262 
+    //{PG_9,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
263 
+  #endif
264 
+  {NC,    NP,    0}
265 
+};
266 
+
267 
+const PinMap PinMap_UART_RTS[] = {
268 
+  //{PA_1,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
269 
+  //{PA_12, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
270 
+  //{PB_14, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
271 
+  //{PD_4,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
272 
+  //{PD_12, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
273 
+  #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
274 
+    //{PG_8,  USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
275 
+    //{PG_12, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
276 
+  #endif
277 
+  {NC,    NP,    0}
278 
+};
279 
+
280 
+const PinMap PinMap_UART_CTS[] = {
281 
+  //{PA_0,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
282 
+  //{PA_11, USART1,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
283 
+  //{PB_13, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
284 
+  //{PD_3,  USART2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
285 
+  //{PD_11, USART3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
286 
+  #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
287 
+    //{PG_13, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
288 
+    //{PG_15, USART6,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
289 
+  #endif
290 
+  {NC,    NP,    0}
291 
+};
292 
+#endif
293 
+
294 
+//*** SPI ***
295 
+
296 
+#ifdef HAL_SPI_MODULE_ENABLED
297 
+const PinMap PinMap_SPI_MOSI[] = {
298 
+  //{PB_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
299 
+  {PA_7,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
300 
+  {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
301 
+  {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
302 
+  {NC,    NP,    0}
303 
+};
304 
+
305 
+const PinMap PinMap_SPI_MISO[] = {
306 
+  {PA_6,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
307 
+  {PB_14, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
308 
+  {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
309 
+  {NC,    NP,    0}
310 
+};
311 
+
312 
+const PinMap PinMap_SPI_SCLK[] = {
313 
+  {PA_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
314 
+  {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
315 
+  {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
316 
+  {NC,    NP,    0}
317 
+};
318 
+
319 
+const PinMap PinMap_SPI_SSEL[] = {
320 
+  {PA_4,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
321 
+  {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
322 
+  {PA_15, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
323 
+  {NC,    NP,    0}
324 
+};
325 
+#endif
326 
+
327 
+//*** CAN ***
328 
+
329 
+#ifdef HAL_CAN_MODULE_ENABLED
330 
+#error "CAN bus isn't available on this board. Driver should be disabled."
331 
+#endif
332 
+
333 
+//*** ETHERNET ***
334 
+#ifdef HAL_ETH_MODULE_ENABLED
335 
+#error "Ethernet port isn't available on this board. Driver should be disabled."
336 
+#endif
337 
+
338 
+//*** No QUADSPI ***
339 
+
340 
+//*** USB ***
341 
+#ifdef HAL_PCD_MODULE_ENABLED
342 
+const PinMap PinMap_USB_OTG_FS[] = {
343 
+  //{PA_8,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF   used by LCD
344 
+  //{PA_9,  USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)},     // USB_OTG_FS_VBUS  available on wifi port, if empty
345 
+  //{PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID    available on UART1_RX if not used
346 
+  {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM
347 
+  {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP
348 
+  {NC,    NP,    0}
349 
+};
350 
+
351 
+const PinMap PinMap_USB_OTG_HS[] = { /*
352 
+  #ifdef USE_USB_HS_IN_FS
353 
+    {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID
354 
+    {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS
355 
+    {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM
356 
+    {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP
357 
+  #else
358 
+    #error "USB in HS mode isn't supported by the board"
359 
+    {PA_3,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0
360 
+    {PB_0,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1
361 
+    {PB_1,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2
362 
+    {PB_5,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7
363 
+    {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3
364 
+    {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5
365 
+    {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6
366 
+    {PC_0,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP
367 
+    {PC_2,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR
368 
+    {PC_3,  USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT
369 
+  #endif // USE_USB_HS_IN_FS
370 
+  */
371 
+  {NC,    NP,    0}
372 
+};
373 
+#endif

+ 50
- 0
buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/PinNamesVar.h Datei anzeigen 

@@ -0,0 +1,50 @@
1 
+/* SYS_WKUP */
2 
+#ifdef PWR_WAKEUP_PIN1
3 
+  SYS_WKUP1 = PA_0,
4 
+#endif
5 
+#ifdef PWR_WAKEUP_PIN2
6 
+  SYS_WKUP2 = NC,
7 
+#endif
8 
+#ifdef PWR_WAKEUP_PIN3
9 
+  SYS_WKUP3 = NC,
10 
+#endif
11 
+#ifdef PWR_WAKEUP_PIN4
12 
+  SYS_WKUP4 = NC,
13 
+#endif
14 
+#ifdef PWR_WAKEUP_PIN5
15 
+  SYS_WKUP5 = NC,
16 
+#endif
17 
+#ifdef PWR_WAKEUP_PIN6
18 
+  SYS_WKUP6 = NC,
19 
+#endif
20 
+#ifdef PWR_WAKEUP_PIN7
21 
+  SYS_WKUP7 = NC,
22 
+#endif
23 
+#ifdef PWR_WAKEUP_PIN8
24 
+  SYS_WKUP8 = NC,
25 
+#endif
26 
+/* USB */
27 
+#ifdef USBCON
28 
+  USB_OTG_FS_SOF      = PA_8,
29 
+  USB_OTG_FS_VBUS     = PA_9,
30 
+  USB_OTG_FS_ID       = PA_10,
31 
+  USB_OTG_FS_DM       = PA_11,
32 
+  USB_OTG_FS_DP       = PA_12,
33 
+  USB_OTG_HS_ULPI_D0  = PA_3,
34 
+  USB_OTG_HS_SOF      = PA_4,
35 
+  USB_OTG_HS_ULPI_CK  = PA_5,
36 
+  USB_OTG_HS_ULPI_D1  = PB_0,
37 
+  USB_OTG_HS_ULPI_D2  = PB_1,
38 
+  USB_OTG_HS_ULPI_D7  = PB_5,
39 
+  USB_OTG_HS_ULPI_D3  = PB_10,
40 
+  USB_OTG_HS_ULPI_D4  = PB_11,
41 
+  USB_OTG_HS_ID       = PB_12,
42 
+  USB_OTG_HS_ULPI_D5  = PB_12,
43 
+  USB_OTG_HS_ULPI_D6  = PB_13,
44 
+  USB_OTG_HS_VBUS     = PB_13,
45 
+  USB_OTG_HS_DM       = PB_14,
46 
+  USB_OTG_HS_DP       = PB_15,
47 
+  USB_OTG_HS_ULPI_STP = PC_0,
48 
+  USB_OTG_HS_ULPI_DIR = PC_2,
49 
+  USB_OTG_HS_ULPI_NXT = PC_3,
50 
+#endif

+ 52
- 0
buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/hal_conf_extra.h Datei anzeigen 

@@ -0,0 +1,52 @@
1 
+#pragma once
2 
+
3 
+#define HAL_MODULE_ENABLED
4 
+#define HAL_ADC_MODULE_ENABLED
5 
+#define HAL_CRC_MODULE_ENABLED
6 
+#define HAL_DMA_MODULE_ENABLED
7 
+#define HAL_GPIO_MODULE_ENABLED
8 
+#define HAL_I2C_MODULE_ENABLED
9 
+#define HAL_PWR_MODULE_ENABLED
10 
+#define HAL_RCC_MODULE_ENABLED
11 
+//#define HAL_RTC_MODULE_ENABLED Real Time Clock...do we use it?
12 
+#define HAL_SPI_MODULE_ENABLED
13 
+#define HAL_TIM_MODULE_ENABLED
14 
+#define HAL_USART_MODULE_ENABLED
15 
+#define HAL_CORTEX_MODULE_ENABLED
16 
+//#define HAL_UART_MODULE_ENABLED // by default
17 
+//#define HAL_PCD_MODULE_ENABLED  // Since STM32 v3.10700.191028 this is automatically added if any type of USB is enabled (as in Arduino IDE)
18 
+
19 
+#undef HAL_SD_MODULE_ENABLED
20 
+#undef HAL_DAC_MODULE_ENABLED
21 
+#undef HAL_FLASH_MODULE_ENABLED
22 
+#undef HAL_CAN_MODULE_ENABLED
23 
+#undef HAL_CAN_LEGACY_MODULE_ENABLED
24 
+#undef HAL_CEC_MODULE_ENABLED
25 
+#undef HAL_CRYP_MODULE_ENABLED
26 
+#undef HAL_DCMI_MODULE_ENABLED
27 
+#undef HAL_DMA2D_MODULE_ENABLED
28 
+#undef HAL_ETH_MODULE_ENABLED
29 
+#undef HAL_NAND_MODULE_ENABLED
30 
+#undef HAL_NOR_MODULE_ENABLED
31 
+#undef HAL_PCCARD_MODULE_ENABLED
32 
+#undef HAL_SRAM_MODULE_ENABLED
33 
+#undef HAL_SDRAM_MODULE_ENABLED
34 
+#undef HAL_HASH_MODULE_ENABLED
35 
+#undef HAL_EXTI_MODULE_ENABLED
36 
+#undef HAL_SMBUS_MODULE_ENABLED
37 
+#undef HAL_I2S_MODULE_ENABLED
38 
+#undef HAL_IWDG_MODULE_ENABLED
39 
+#undef HAL_LTDC_MODULE_ENABLED
40 
+#undef HAL_DSI_MODULE_ENABLED
41 
+#undef HAL_QSPI_MODULE_ENABLED
42 
+#undef HAL_RNG_MODULE_ENABLED
43 
+#undef HAL_SAI_MODULE_ENABLED
44 
+#undef HAL_IRDA_MODULE_ENABLED
45 
+#undef HAL_SMARTCARD_MODULE_ENABLED
46 
+#undef HAL_WWDG_MODULE_ENABLED
47 
+#undef HAL_HCD_MODULE_ENABLED
48 
+#undef HAL_FMPI2C_MODULE_ENABLED
49 
+#undef HAL_SPDIFRX_MODULE_ENABLED
50 
+#undef HAL_DFSDM_MODULE_ENABLED
51 
+#undef HAL_LPTIM_MODULE_ENABLED
52 
+#undef HAL_MMC_MODULE_ENABLED

+ 204
- 0
buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/ldscript.ld Datei anzeigen 

@@ -0,0 +1,204 @@
1 
+/*
2 
+*****************************************************************************
3 
+**
4 
+
5 
+**  File        : LinkerScript.ld
6 
+**
7 
+**  Abstract    : Linker script for STM32F407ZGTx Device with
8 
+**                1024KByte FLASH, 128KByte RAM
9 
+**
10 
+**                Set heap size, stack size and stack location according
11 
+**                to application requirements.
12 
+**
13 
+**                Set memory bank area and size if external memory is used.
14 
+**
15 
+**  Target      : STMicroelectronics STM32
16 
+**
17 
+**
18 
+**  Distribution: The file is distributed as is, without any warranty
19 
+**                of any kind.
20 
+**
21 
+*****************************************************************************
22 
+** @attention
23 
+**
24 
+** <h2><center>&copy; COPYRIGHT(c) 2014 Ac6</center></h2>
25 
+**
26 
+** Redistribution and use in source and binary forms, with or without modification,
27 
+** are permitted provided that the following conditions are met:
28 
+**   1. Redistributions of source code must retain the above copyright notice,
29 
+**      this list of conditions and the following disclaimer.
30 
+**   2. Redistributions in binary form must reproduce the above copyright notice,
31 
+**      this list of conditions and the following disclaimer in the documentation
32 
+**      and/or other materials provided with the distribution.
33 
+**   3. Neither the name of Ac6 nor the names of its contributors
34 
+**      may be used to endorse or promote products derived from this software
35 
+**      without specific prior written permission.
36 
+**
37 
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
38 
+** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
39 
+** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
40 
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
41 
+** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
42 
+** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
43 
+** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
44 
+** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
45 
+** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 
+** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 
+**
48 
+*****************************************************************************
49 
+*/
50 
+
51 
+/* Entry Point */
52 
+ENTRY(Reset_Handler)
53 
+
54 
+/* Highest address of the user mode stack */
55 
+_estack = 0x20020000;    /* end of RAM */
56 
+/* Generate a link error if heap and stack don't fit into RAM */
57 
+_Min_Heap_Size = 0x200;;      /* required amount of heap  */
58 
+_Min_Stack_Size = 0x400;; /* required amount of stack */
59 
+
60 
+/* Specify the memory areas */
61 
+MEMORY
62 
+{
63 
+FLASH (rx)      : ORIGIN = 0x8008000, LENGTH = 1024K
64 
+RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 128K
65 
+CCMRAM (rw)      : ORIGIN = 0x10000000, LENGTH = 64K
66 
+}
67 
+
68 
+/* Define output sections */
69 
+SECTIONS
70 
+{
71 
+  /* The startup code goes first into FLASH */
72 
+  .isr_vector :
73 
+  {
74 
+    . = ALIGN(4);
75 
+    KEEP(*(.isr_vector)) /* Startup code */
76 
+    . = ALIGN(4);
77 
+  } >FLASH
78 
+
79 
+  /* The program code and other data goes into FLASH */
80 
+  .text ALIGN(4):
81 
+  {
82 
+    . = ALIGN(4);
83 
+    *(.text)           /* .text sections (code) */
84 
+    *(.text*)          /* .text* sections (code) */
85 
+    *(.glue_7)         /* glue arm to thumb code */
86 
+    *(.glue_7t)        /* glue thumb to arm code */
87 
+    *(.eh_frame)
88 
+
89 
+    KEEP (*(.init))
90 
+    KEEP (*(.fini))
91 
+
92 
+    . = ALIGN(4);
93 
+    _etext = .;        /* define a global symbols at end of code */
94 
+  } >FLASH
95 
+
96 
+  /* Constant data goes into FLASH */
97 
+  .rodata ALIGN(4):
98 
+  {
99 
+    . = ALIGN(4);
100 
+    *(.rodata)         /* .rodata sections (constants, strings, etc.) */
101 
+    *(.rodata*)        /* .rodata* sections (constants, strings, etc.) */
102 
+    . = ALIGN(4);
103 
+  } >FLASH
104 
+
105 
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
106 
+  .ARM : {
107 
+    __exidx_start = .;
108 
+    *(.ARM.exidx*)
109 
+    __exidx_end = .;
110 
+  } >FLASH
111 
+
112 
+  .preinit_array     :
113 
+  {
114 
+    PROVIDE_HIDDEN (__preinit_array_start = .);
115 
+    KEEP (*(.preinit_array*))
116 
+    PROVIDE_HIDDEN (__preinit_array_end = .);
117 
+  } >FLASH
118 
+  .init_array :
119 
+  {
120 
+    PROVIDE_HIDDEN (__init_array_start = .);
121 
+    KEEP (*(SORT(.init_array.*)))
122 
+    KEEP (*(.init_array*))
123 
+    PROVIDE_HIDDEN (__init_array_end = .);
124 
+  } >FLASH
125 
+  .fini_array :
126 
+  {
127 
+    PROVIDE_HIDDEN (__fini_array_start = .);
128 
+    KEEP (*(SORT(.fini_array.*)))
129 
+    KEEP (*(.fini_array*))
130 
+    PROVIDE_HIDDEN (__fini_array_end = .);
131 
+  } >FLASH
132 
+
133 
+  /* used by the startup to initialize data */
134 
+  _sidata = LOADADDR(.data);
135 
+
136 
+  /* Initialized data sections goes into RAM, load LMA copy after code */
137 
+  .data :
138 
+  {
139 
+    . = ALIGN(4);
140 
+    _sdata = .;        /* create a global symbol at data start */
141 
+    *(.data)           /* .data sections */
142 
+    *(.data*)          /* .data* sections */
143 
+
144 
+    . = ALIGN(4);
145 
+    _edata = .;        /* define a global symbol at data end */
146 
+  } >RAM AT> FLASH
147 
+
148 
+  _siccmram = LOADADDR(.ccmram);
149 
+
150 
+  /* CCM-RAM section
151 
+   *
152 
+   * IMPORTANT NOTE!
153 
+   * If initialized variables will be placed in this section,
154 
+   * the startup code needs to be modified to copy the init-values.
155 
+   */
156 
+  .ccmram :
157 
+  {
158 
+    . = ALIGN(4);
159 
+    _sccmram = .;       /* create a global symbol at ccmram start */
160 
+    *(.ccmram)
161 
+    *(.ccmram*)
162 
+
163 
+    . = ALIGN(4);
164 
+    _eccmram = .;       /* create a global symbol at ccmram end */
165 
+  } >CCMRAM AT> FLASH
166 
+
167 
+
168 
+  /* Uninitialized data section */
169 
+  . = ALIGN(4);
170 
+  .bss :
171 
+  {
172 
+    /* This is used by the startup in order to initialize the .bss secion */
173 
+    _sbss = .;         /* define a global symbol at bss start */
174 
+    __bss_start__ = _sbss;
175 
+    *(.bss)
176 
+    *(.bss*)
177 
+    *(COMMON)
178 
+
179 
+    . = ALIGN(4);
180 
+    _ebss = .;         /* define a global symbol at bss end */
181 
+    __bss_end__ = _ebss;
182 
+  } >RAM
183 
+
184 
+  /* User_heap_stack section, used to check that there is enough RAM left */
185 
+  ._user_heap_stack :
186 
+  {
187 
+    . = ALIGN(4);
188 
+    PROVIDE ( end = . );
189 
+    PROVIDE ( _end = . );
190 
+    . = . + _Min_Heap_Size;
191 
+    . = . + _Min_Stack_Size;
192 
+    . = ALIGN(4);
193 
+  } >RAM
194 
+
195 
+  /* Remove information from the standard libraries */
196 
+  /DISCARD/ :
197 
+  {
198 
+    libc.a ( * )
199 
+    libm.a ( * )
200 
+    libgcc.a ( * )
201 
+  }
202 
+
203 
+  .ARM.attributes 0 : { *(.ARM.attributes) }
204 
+}

+ 260
- 0
buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/variant.cpp Datei anzeigen 

@@ -0,0 +1,260 @@
1 
+/*
2 
+ *******************************************************************************
3 
+ * Copyright (c) 2017, STMicroelectronics
4 
+ * All rights reserved.
5 
+ *
6 
+ * Redistribution and use in source and binary forms, with or without
7 
+ * modification, are permitted provided that the following conditions are met:
8 
+ *
9 
+ * 1. Redistributions of source code must retain the above copyright notice,
10 
+ *    this list of conditions and the following disclaimer.
11 
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12 
+ *    this list of conditions and the following disclaimer in the documentation
13 
+ *    and/or other materials provided with the distribution.
14 
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
15 
+ *    may be used to endorse or promote products derived from this software
16 
+ *    without specific prior written permission.
17 
+ *
18 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25 
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 
+ *******************************************************************************
29 
+ */
30 
+
31 
+#include "pins_arduino.h"
32 
+
33 
+#ifdef __cplusplus
34 
+extern "C" {
35 
+#endif
36 
+
37 
+// Pin number
38 
+// This array allows to wrap Arduino pin number(Dx or x)
39 
+// to STM32 PinName (PX_n)
40 
+const PinName digitalPin[] = {
41 
+#if STM32F4X_PIN_NUM >= 64  //64 pins mcu, 51 gpio
42 
+  PC_13, //D0
43 
+  PC_14, //D1  - OSC32_IN
44 
+  PC_15, //D2  - OSC32_OUT
45 
+  PH_0,  //D3  - OSC_IN
46 
+  PH_1,  //D4  - OSC_OUT
47 
+  PB_2,  //D5  - BOOT1
48 
+  PB_10, //D6  - 1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
49 
+  PB_11, //D7  - 1:I2C2_SDA / USART3_RX / TIM2_CH4
50 
+  PB_12, //D8  - 1:SPI2_NSS / OTG_HS_ID
51 
+  PB_13, //D9  - 1:SPI2_SCK  2:OTG_HS_VBUS
52 
+  PB_14, //D10 - 1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
53 
+  PB_15, //D11 - SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
54 
+  PC_6,  //D12 - 1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
55 
+  PC_7,  //D13 - 1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
56 
+  PC_8,  //D14 - 1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
57 
+  PC_9,  //D15 - 1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
58 
+  PA_8,  //D16 - 1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
59 
+  PA_9,  //D17 - 1:USART1_TX / TIM1_CH2  2:OTG_FS_VBUS
60 
+  PA_10, //D18 - 1:USART1_RX / TIM1_CH3 / OTG_FS_ID
61 
+  PA_11, //D19 - 1:TIM1_CH4 / OTG_FS_DM
62 
+  PA_12, //D20 - 1:OTG_FS_DP
63 
+  PA_13, //D21 - 0:JTMS-SWDIO
64 
+  PA_14, //D22 - 0:JTCK-SWCLK
65 
+  PA_15, //D23 - 0:JTDI  1:SPI3_NSS / SPI1_NSS
66 
+  PC_10, //D24 - 1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
67 
+  PC_11, //D25 - 1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
68 
+  PC_12, //D26 - 1:UART5_TX / SPI3_MOSI / SDIO_CK
69 
+  PD_2,  //D27 - 1:UART5_RX / SDIO_CMD
70 
+  PB_3,  //D28 - 0:JTDO  1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
71 
+  PB_4,  //D29 - 0:NJTRST  1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
72 
+  PB_5,  //D30 - 1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
73 
+  PB_6,  //D31 - 1:I2C1_SCL / TIM4_CH1 / USART1_TX
74 
+  PB_7,  //D32 - 1:I2C1_SDA / TIM4_CH2 / USART1_RX
75 
+  PB_8,  //D33 - 1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
76 
+  PB_9,  //D34 - 1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
77 
+  PA_0,  //D35/A0 - 1:UART4_TX / TIM5_CH1  2:ADC123_IN0
78 
+  PA_1,  //D36/A1 - 1:UART4_RX / TIM5_CH2 / TIM2_CH2  2:ADC123_IN1
79 
+  PA_2,  //D37/A2 - 1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3  2:ADC123_IN2
80 
+  PA_3,  //D38/A3 - 1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4  2:ADC123_IN3
81 
+  PA_4,  //D39/A4 - NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK  2:ADC12_IN4 / DAC_OUT1
82 
+  PA_5,  //D40/A5 - NOT FT 1:SPI1_SCK  2:ADC12_IN5 / DAC_OUT2
83 
+  PA_6,  //D41/A6 - 1:SPI1_MISO / TIM13_CH1 / TIM3_CH1  2:ADC12_IN6
84 
+  PA_7,  //D42/A7 - 1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2  2:ADC12_IN7
85 
+  PB_0,  //D43/A8 - 1:TIM3_CH3  2:ADC12_IN8
86 
+  PB_1,  //D44/A9 - 1:TIM3_CH4  2:ADC12_IN9
87 
+  PC_0,  //D45/A10 - 1:  2:ADC123_IN10
88 
+  PC_1,  //D46/A11 - 1:  2:ADC123_IN11
89 
+  PC_2,  //D47/A12 - 1:SPI2_MISO  2:ADC123_IN12
90 
+  PC_3,  //D48/A13 - 1:SPI2_MOSI  2:ADC123_IN13
91 
+  PC_4,  //D49/A14 - 1:  2:ADC12_IN14
92 
+  PC_5,  //D50/A15 - 1:  2:ADC12_IN15
93 
+  #if STM32F4X_PIN_NUM >= 144
94 
+    PF_3,  //D51/A16 - 1:FSMC_A3  2:ADC3_IN9
95 
+    PF_4,  //D52/A17 - 1:FSMC_A4  2:ADC3_IN14
96 
+    PF_5,  //D53/A18 - 1:FSMC_A5  2:ADC3_IN15
97 
+    PF_6,  //D54/A19 - 1:TIM10_CH1  2:ADC3_IN4
98 
+    PF_7,  //D55/A20 - 1:TIM11_CH1  2:ADC3_IN5
99 
+    PF_8,  //D56/A21 - 1:TIM13_CH1  2:ADC3_IN6
100 
+    PF_9,  //D57/A22 - 1;TIM14_CH1  2:ADC3_IN7
101 
+    PF_10, //D58/A23 - 2:ADC3_IN8
102 
+  #endif
103 
+#endif
104 
+#if STM32F4X_PIN_NUM >= 100  //100 pins mcu, 82 gpio
105 
+  PE_2,  //D59 - 1:FSMC_A23
106 
+  PE_3,  //D60 - 1:FSMC_A19
107 
+  PE_4,  //D61 - 1:FSMC_A20
108 
+  PE_5,  //D62 - 1:FSMC_A21
109 
+  PE_6,  //D63 - 1:FSMC_A22
110 
+  PE_7,  //D64 - 1:FSMC_D4
111 
+  PE_8,  //D65 - 1:FSMC_D5
112 
+  PE_9,  //D66 - 1:FSMC_D6 / TIM1_CH1
113 
+  PE_10, //D67 - 1:FSMC_D7
114 
+  PE_11, //D68 - 1:FSMC_D8 / TIM1_CH2
115 
+  PE_12, //D69 - 1:FSMC_D9
116 
+  PE_13, //D70 - 1:FSMC_D10 / TIM1_CH3
117 
+  PE_14, //D71 - 1:FSMC_D11 / TIM1_CH4
118 
+  PE_15, //D72 - 1:FSMC_D12
119 
+  PD_8,  //D73 - 1:FSMC_D13 / USART3_TX
120 
+  PD_9,  //D74 - 1:FSMC_D14 / USART3_RX
121 
+  PD_10, //D75 - 1:FSMC_D15
122 
+  PD_11, //D76 - 1:FSMC_A16
123 
+  PD_12, //D77 - 1:FSMC_A17 / TIM4_CH1
124 
+  PD_13, //D78 - 1:FSMC_A18 / TIM4_CH2
125 
+  PD_14, //D79 - 1:FSMC_D0 / TIM4_CH3
126 
+  PD_15, //D80 - 1:FSMC_D1 / TIM4_CH4
127 
+  PD_0,  //D81 - 1:FSMC_D2
128 
+  PD_1,  //D82 - 1:FSMC_D3
129 
+  PD_3,  //D83 - 1:FSMC_CLK
130 
+  PD_4,  //D84 - 1:FSMC_NOE
131 
+  PD_5,  //D85 - 1:USART2_TX
132 
+  PD_6,  //D86 - 1:USART2_RX
133 
+  PD_7,  //D87
134 
+  PE_0,  //D88
135 
+  PE_1,  //D89
136 
+#endif
137 
+#if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
138 
+  PF_0,  //D90 - 1:FSMC_A0 / I2C2_SDA
139 
+  PF_1,  //D91 - 1:FSMC_A1 / I2C2_SCL
140 
+  PF_2,  //D92 - 1:FSMC_A2
141 
+  PF_11, //D93
142 
+  PF_12, //D94 - 1:FSMC_A6
143 
+  PF_13, //D95 - 1:FSMC_A7
144 
+  PF_14, //D96 - 1:FSMC_A8
145 
+  PF_15, //D97 - 1:FSMC_A9
146 
+  PG_0,  //D98 - 1:FSMC_A10
147 
+  PG_1,  //D99 - 1:FSMC_A11
148 
+  PG_2,  //D100 - 1:FSMC_A12
149 
+  PG_3,  //D101 - 1:FSMC_A13
150 
+  PG_4,  //D102 - 1:FSMC_A14
151 
+  PG_5,  //D103 - 1:FSMC_A15
152 
+  PG_6,  //D104
153 
+  PG_7,  //D105
154 
+  PG_8,  //D106
155 
+  PG_9,  //D107 - 1:USART6_RX
156 
+  PG_10, //D108 - 1:FSMC_NE3
157 
+  PG_11, //D109
158 
+  PG_12, //D110 - 1:FSMC_NE4
159 
+  PG_13, //D111 - 1:FSMC_A24
160 
+  PG_14, //D112 - 1:FSMC_A25 / USART6_TX
161 
+  PG_15, //D113
162 
+#endif
163 
+#if STM32F4X_PIN_NUM >= 176  //176 pins mcu, 140 gpio
164 
+  PI_8,  //D114
165 
+  PI_9,  //D115
166 
+  PI_10, //D116
167 
+  PI_11, //D117
168 
+  PH_2,  //D118
169 
+  PH_3,  //D119
170 
+  PH_4,  //D120 - 1:I2C2_SCL
171 
+  PH_5,  //D121 - 1:I2C2_SDA
172 
+  PH_6,  //D122 - 1:TIM12_CH1
173 
+  PH_7,  //D123 - 1:I2C3_SCL
174 
+  PH_8,  //D124 - 1:I2C3_SDA
175 
+  PH_9,  //D125 - 1:TIM12_CH2
176 
+  PH_10, //D126 - 1:TIM5_CH1
177 
+  PH_11, //D127 - 1:TIM5_CH2
178 
+  PH_12, //D128 - 1:TIM5_CH3
179 
+  PH_13, //D129
180 
+  PH_14, //D130
181 
+  PH_15, //D131
182 
+  PI_0,  //D132 - 1:TIM5_CH4 / SPI2_NSS
183 
+  PI_1,  //D133 - 1:SPI2_SCK
184 
+  PI_2,  //D134 - 1:TIM8_CH4 /SPI2_MISO
185 
+  PI_3,  //D135 - 1:SPI2_MOS
186 
+  PI_4,  //D136
187 
+  PI_5,  //D137 - 1:TIM8_CH1
188 
+  PI_6,  //D138 - 1:TIM8_CH2
189 
+  PI_7,  //D139 - 1:TIM8_CH3
190 
+#endif
191 
+};
192 
+
193 
+#ifdef __cplusplus
194 
+}
195 
+#endif
196 
+
197 
+// ------------------------
198 
+
199 
+#ifdef __cplusplus
200 
+extern "C" {
201 
+#endif
202 
+
203 
+ /**
204 
+  * @brief  System Clock Configuration
205 
+  * @param  None
206 
+  * @retval None
207 
+  */
208 
+WEAK void SystemClock_Config() {
209 
+
210 
+  RCC_OscInitTypeDef RCC_OscInitStruct;
211 
+  RCC_ClkInitTypeDef RCC_ClkInitStruct;
212 
+
213 
+  /**Configure the main internal regulator output voltage
214 
+  */
215 
+  __HAL_RCC_PWR_CLK_ENABLE();
216 
+
217 
+  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
218 
+
219 
+  /**Initializes the CPU, AHB and APB busses clocks
220 
+  */
221 
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
222 
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
223 
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
224 
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
225 
+  RCC_OscInitStruct.PLL.PLLM = 8;
226 
+  RCC_OscInitStruct.PLL.PLLN = 336;
227 
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
228 
+  RCC_OscInitStruct.PLL.PLLQ = 7;
229 
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
230 
+    _Error_Handler(__FILE__, __LINE__);
231 
+  }
232 
+
233 
+  /**Initializes the CPU, AHB and APB busses clocks
234 
+  */
235 
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
236 
+                                | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
237 
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
238 
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
239 
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
240 
+  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
241 
+
242 
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
243 
+    _Error_Handler(__FILE__, __LINE__);
244 
+  }
245 
+
246 
+  /**Configure the Systick interrupt time
247 
+  */
248 
+  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
249 
+
250 
+  /**Configure the Systick
251 
+  */
252 
+  HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
253 
+
254 
+  /* SysTick_IRQn interrupt configuration */
255 
+  HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
256 
+}
257 
+
258 
+#ifdef __cplusplus
259 
+}
260 
+#endif

+ 322
- 0
buildroot/share/PlatformIO/variants/BIGTREE_GTR_V1/variant.h Datei anzeigen 

@@ -0,0 +1,322 @@
1 
+/*
2 
+ *******************************************************************************
3 
+ * Copyright (c) 2017, STMicroelectronics
4 
+ * All rights reserved.
5 
+ *
6 
+ * Redistribution and use in source and binary forms, with or without
7 
+ * modification, are permitted provided that the following conditions are met:
8 
+ *
9 
+ * 1. Redistributions of source code must retain the above copyright notice,
10 
+ *    this list of conditions and the following disclaimer.
11 
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
12 
+ *    this list of conditions and the following disclaimer in the documentation
13 
+ *    and/or other materials provided with the distribution.
14 
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
15 
+ *    may be used to endorse or promote products derived from this software
16 
+ *    without specific prior written permission.
17 
+ *
18 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
22 
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
25 
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 
+ *******************************************************************************
29 
+ */
30 
+#pragma once
31 
+
32 
+#ifdef __cplusplus
33 
+extern "C" {
34 
+#endif // __cplusplus
35 
+
36 
+/*----------------------------------------------------------------------------
37 
+ *        Pins
38 
+ *----------------------------------------------------------------------------*/
39 
+
40 
+#ifdef STM32F405RX
41 
+  #define STM32F4X_PIN_NUM  64  //64 pins mcu, 51 gpio
42 
+  #define STM32F4X_GPIO_NUM 51
43 
+  #define STM32F4X_ADC_NUM  16
44 
+#elif defined(STM32F407_5VX)
45 
+  #define STM32F4X_PIN_NUM  100  //100 pins mcu, 82 gpio
46 
+  #define STM32F4X_GPIO_NUM 82
47 
+  #define STM32F4X_ADC_NUM  16
48 
+#elif defined(STM32F407_5ZX)
49 
+  #define STM32F4X_PIN_NUM  144  //144 pins mcu, 114 gpio
50 
+  #define STM32F4X_GPIO_NUM 114
51 
+  #define STM32F4X_ADC_NUM  24
52 
+#elif defined(STM32F407IX)
53 
+  #define STM32F4X_PIN_NUM  176  //176 pins mcu, 140 gpio
54 
+  #define STM32F4X_GPIO_NUM 140
55 
+  #define STM32F4X_ADC_NUM  24
56 
+#else
57 
+  #error "no match MCU defined"
58 
+#endif
59 
+
60 
+#if STM32F4X_PIN_NUM >= 64  //64 pins mcu, 51 gpio
61 
+  #define PC13  0
62 
+  #define PC14  1 //OSC32_IN
63 
+  #define PC15  2 //OSC32_OUT
64 
+  #define PH0   3 //OSC_IN
65 
+  #define PH1   4 //OSC_OUT
66 
+  #define PB2   5 //BOOT1
67 
+  #define PB10  6 //1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
68 
+  #define PB11  7 //1:I2C2_SDA / USART3_RX / TIM2_CH4
69 
+  #define PB12  8 //1:SPI2_NSS / OTG_HS_ID
70 
+  #define PB13  9 //1:SPI2_SCK  2:OTG_HS_VBUS
71 
+  #define PB14  10 //1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
72 
+  #define PB15  11 //SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
73 
+  #define PC6   12 //1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
74 
+  #define PC7   13 //1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
75 
+  #define PC8   14 //1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
76 
+  #define PC9   15 //1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
77 
+  #define PA8   16 //1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
78 
+  #define PA9   17 //1:USART1_TX / TIM1_CH2  2:OTG_FS_VBUS
79 
+  #define PA10  18 //1:USART1_RX / TIM1_CH3 / OTG_FS_ID
80 
+  #define PA11  19 //1:TIM1_CH4 / OTG_FS_DM
81 
+  #define PA12  20 //1:OTG_FS_DP
82 
+  #define PA13  21 //0:JTMS-SWDIO
83 
+  #define PA14  22 //0:JTCK-SWCLK
84 
+  #define PA15  23 //0:JTDI  1:SPI3_NSS / SPI1_NSS
85 
+  #define PC10  24 //1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
86 
+  #define PC11  25 //1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
87 
+  #define PC12  26 //1:UART5_TX / SPI3_MOSI / SDIO_CK
88 
+  #define PD2   27 //1:UART5_RX / SDIO_CMD
89 
+  #define PB3   28 //0:JTDO  1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
90 
+  #define PB4   29 //0:NJTRST  1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
91 
+  #define PB5   30 //1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
92 
+  #define PB6   31 //1:I2C1_SCL / TIM4_CH1 / USART1_TX
93 
+  #define PB7   32 //1:I2C1_SDA / TIM4_CH2 / USART1_RX
94 
+  #define PB8   33 //1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
95 
+  #define PB9   34 //1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
96 
+  #define PA0   35 //1:UART4_TX / TIM5_CH1  2:ADC123_IN0
97 
+  #define PA1   36 //1:UART4_RX / TIM5_CH2 / TIM2_CH2  2:ADC123_IN1
98 
+  #define PA2   37 //1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3  2:ADC123_IN2
99 
+  #define PA3   38 //1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4  2:ADC123_IN3
100 
+  #define PA4   39 //NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK  2:ADC12_IN4 / DAC_OUT1
101 
+  #define PA5   40 //NOT FT 1:SPI1_SCK  2:ADC12_IN5 / DAC_OUT2
102 
+  #define PA6   41 //1:SPI1_MISO / TIM13_CH1 / TIM3_CH1  2:ADC12_IN6
103 
+  #define PA7   42 //1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2  2:ADC12_IN7
104 
+  #define PB0   43 //1:TIM3_CH3  2:ADC12_IN8
105 
+  #define PB1   44 //1:TIM3_CH4  2:ADC12_IN9
106 
+  #define PC0   45 //1:  2:ADC123_IN10
107 
+  #define PC1   46 //1:  2:ADC123_IN11
108 
+  #define PC2   47 //1:SPI2_MISO  2:ADC123_IN12
109 
+  #define PC3   48 //1:SPI2_MOSI  2:ADC123_IN13
110 
+  #define PC4   49 //1:  2:ADC12_IN14
111 
+  #define PC5   50 //1:  2:ADC12_IN15
112 
+  #if STM32F4X_PIN_NUM >= 144
113 
+    #define PF3   51 //1:FSMC_A3  2:ADC3_IN9
114 
+    #define PF4   52 //1:FSMC_A4  2:ADC3_IN14
115 
+    #define PF5   53 //1:FSMC_A5  2:ADC3_IN15
116 
+    #define PF6   54 //1:TIM10_CH1  2:ADC3_IN4
117 
+    #define PF7   55 //1:TIM11_CH1  2:ADC3_IN5
118 
+    #define PF8   56 //1:TIM13_CH1  2:ADC3_IN6
119 
+    #define PF9   57 //1;TIM14_CH1  2:ADC3_IN7
120 
+    #define PF10  58 //2:ADC3_IN8
121 
+  #endif
122 
+#endif
123 
+#if STM32F4X_PIN_NUM >= 100  //100 pins mcu, 82 gpio
124 
+  #define PE2   (35+STM32F4X_ADC_NUM) //1:FSMC_A23
125 
+  #define PE3   (36+STM32F4X_ADC_NUM) //1:FSMC_A19
126 
+  #define PE4   (37+STM32F4X_ADC_NUM) //1:FSMC_A20
127 
+  #define PE5   (38+STM32F4X_ADC_NUM) //1:FSMC_A21
128 
+  #define PE6   (39+STM32F4X_ADC_NUM) //1:FSMC_A22
129 
+  #define PE7   (40+STM32F4X_ADC_NUM) //1:FSMC_D4
130 
+  #define PE8   (41+STM32F4X_ADC_NUM) //1:FSMC_D5
131 
+  #define PE9   (42+STM32F4X_ADC_NUM) //1:FSMC_D6 / TIM1_CH1
132 
+  #define PE10  (43+STM32F4X_ADC_NUM) //1:FSMC_D7
133 
+  #define PE11  (44+STM32F4X_ADC_NUM) //1:FSMC_D8 / TIM1_CH2
134 
+  #define PE12  (45+STM32F4X_ADC_NUM) //1:FSMC_D9
135 
+  #define PE13  (46+STM32F4X_ADC_NUM) //1:FSMC_D10 / TIM1_CH3
136 
+  #define PE14  (47+STM32F4X_ADC_NUM) //1:FSMC_D11 / TIM1_CH4
137 
+  #define PE15  (48+STM32F4X_ADC_NUM) //1:FSMC_D12
138 
+  #define PD8   (49+STM32F4X_ADC_NUM) //1:FSMC_D13 / USART3_TX
139 
+  #define PD9   (50+STM32F4X_ADC_NUM) //1:FSMC_D14 / USART3_RX
140 
+  #define PD10  (51+STM32F4X_ADC_NUM) //1:FSMC_D15
141 
+  #define PD11  (52+STM32F4X_ADC_NUM) //1:FSMC_A16
142 
+  #define PD12  (53+STM32F4X_ADC_NUM) //1:FSMC_A17 / TIM4_CH1
143 
+  #define PD13  (54+STM32F4X_ADC_NUM) //1:FSMC_A18 / TIM4_CH2
144 
+  #define PD14  (55+STM32F4X_ADC_NUM) //1:FSMC_D0 / TIM4_CH3
145 
+  #define PD15  (56+STM32F4X_ADC_NUM) //1:FSMC_D1 / TIM4_CH4
146 
+  #define PD0   (57+STM32F4X_ADC_NUM) //1:FSMC_D2
147 
+  #define PD1   (58+STM32F4X_ADC_NUM) //1:FSMC_D3
148 
+  #define PD3   (59+STM32F4X_ADC_NUM) //1:FSMC_CLK
149 
+  #define PD4   (60+STM32F4X_ADC_NUM) //1:FSMC_NOE
150 
+  #define PD5   (61+STM32F4X_ADC_NUM) //1:USART2_TX
151 
+  #define PD6   (62+STM32F4X_ADC_NUM) //1:USART2_RX
152 
+  #define PD7   (63+STM32F4X_ADC_NUM)
153 
+  #define PE0   (64+STM32F4X_ADC_NUM)
154 
+  #define PE1   (65+STM32F4X_ADC_NUM)
155 
+#endif
156 
+#if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
157 
+  #define PF0   (66+STM32F4X_ADC_NUM) //1:FSMC_A0 / I2C2_SDA
158 
+  #define PF1   (67+STM32F4X_ADC_NUM) //1:FSMC_A1 / I2C2_SCL
159 
+  #define PF2   (68+STM32F4X_ADC_NUM) //1:FSMC_A2
160 
+  #define PF11  (69+STM32F4X_ADC_NUM)
161 
+  #define PF12  (70+STM32F4X_ADC_NUM) //1:FSMC_A6
162 
+  #define PF13  (71+STM32F4X_ADC_NUM) //1:FSMC_A7
163 
+  #define PF14  (72+STM32F4X_ADC_NUM) //1:FSMC_A8
164 
+  #define PF15  (73+STM32F4X_ADC_NUM) //1:FSMC_A9
165 
+  #define PG0   (74+STM32F4X_ADC_NUM) //1:FSMC_A10
166 
+  #define PG1   (75+STM32F4X_ADC_NUM) //1:FSMC_A11
167 
+  #define PG2   (76+STM32F4X_ADC_NUM) //1:FSMC_A12
168 
+  #define PG3   (77+STM32F4X_ADC_NUM) //1:FSMC_A13
169 
+  #define PG4   (78+STM32F4X_ADC_NUM) //1:FSMC_A14
170 
+  #define PG5   (79+STM32F4X_ADC_NUM) //1:FSMC_A15
171 
+  #define PG6   (80+STM32F4X_ADC_NUM)
172 
+  #define PG7   (81+STM32F4X_ADC_NUM)
173 
+  #define PG8   (82+STM32F4X_ADC_NUM)
174 
+  #define PG9   (83+STM32F4X_ADC_NUM) //1:USART6_RX
175 
+  #define PG10  (84+STM32F4X_ADC_NUM) //1:FSMC_NE3
176 
+  #define PG11  (85+STM32F4X_ADC_NUM)
177 
+  #define PG12  (86+STM32F4X_ADC_NUM) //1:FSMC_NE4
178 
+  #define PG13  (87+STM32F4X_ADC_NUM) //1:FSMC_A24
179 
+  #define PG14  (88+STM32F4X_ADC_NUM) //1:FSMC_A25 / USART6_TX
180 
+  #define PG15  (89+STM32F4X_ADC_NUM)
181 
+#endif
182 
+#if STM32F4X_PIN_NUM >= 176  //176 pins mcu, 140 gpio
183 
+  #define PI8   (90+STM32F4X_ADC_NUM)
184 
+  #define PI9   (91+STM32F4X_ADC_NUM)
185 
+  #define PI10  (92+STM32F4X_ADC_NUM)
186 
+  #define PI11  (93+STM32F4X_ADC_NUM)
187 
+  #define PH2   (94+STM32F4X_ADC_NUM)
188 
+  #define PH3   (95+STM32F4X_ADC_NUM)
189 
+  #define PH4   (96+STM32F4X_ADC_NUM) //1:I2C2_SCL
190 
+  #define PH5   (97+STM32F4X_ADC_NUM) //1:I2C2_SDA
191 
+  #define PH6   (98+STM32F4X_ADC_NUM) //1:TIM12_CH1
192 
+  #define PH7   (99+STM32F4X_ADC_NUM) //1:I2C3_SCL
193 
+  #define PH8   (100+STM32F4X_ADC_NUM) //1:I2C3_SDA
194 
+  #define PH9   (101+STM32F4X_ADC_NUM) //1:TIM12_CH2
195 
+  #define PH10  (102+STM32F4X_ADC_NUM) //1:TIM5_CH1
196 
+  #define PH11  (103+STM32F4X_ADC_NUM) //1:TIM5_CH2
197 
+  #define PH12  (104+STM32F4X_ADC_NUM) //1:TIM5_CH3
198 
+  #define PH13  (105+STM32F4X_ADC_NUM)
199 
+  #define PH14  (106+STM32F4X_ADC_NUM)
200 
+  #define PH15  (107+STM32F4X_ADC_NUM)
201 
+  #define PI0   (108+STM32F4X_ADC_NUM) //1:TIM5_CH4 / SPI2_NSS
202 
+  #define PI1   (109+STM32F4X_ADC_NUM) //1:SPI2_SCK
203 
+  #define PI2   (110+STM32F4X_ADC_NUM) //1:TIM8_CH4 /SPI2_MISO
204 
+  #define PI3   (111+STM32F4X_ADC_NUM) //1:SPI2_MOS
205 
+  #define PI4   (112+STM32F4X_ADC_NUM)
206 
+  #define PI5   (113+STM32F4X_ADC_NUM) //1:TIM8_CH1
207 
+  #define PI6   (114+STM32F4X_ADC_NUM) //1:TIM8_CH2
208 
+  #define PI7   (115+STM32F4X_ADC_NUM) //1:TIM8_CH3
209 
+#endif
210 
+
211 
+
212 
+// This must be a literal
213 
+#define NUM_DIGITAL_PINS        (STM32F4X_GPIO_NUM)
214 
+// This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS
215 
+#define NUM_ANALOG_INPUTS       (STM32F4X_ADC_NUM)
216 
+#define NUM_ANALOG_FIRST        35
217 
+
218 
+// Below ADC, DAC and PWM definitions already done in the core
219 
+// Could be redefined here if needed
220 
+// ADC resolution is 12bits
221 
+//#define ADC_RESOLUTION          12
222 
+//#define DACC_RESOLUTION         12
223 
+
224 
+// PWM resolution
225 
+/*
226 
+ * BEWARE:
227 
+ * Changing this value from the default (1000) will affect the PWM output value of analogWrite (to a PWM pin)
228 
+ * Since the pin is toggled on capture, if you change the frequency of the timer you have to adapt the compare value (analogWrite thinks you did)
229 
+ */
230 
+//#define PWM_FREQUENCY           20000
231 
+//The bottom values are the default and don't need to be redefined
232 
+//#define PWM_RESOLUTION          8
233 
+//#define PWM_MAX_DUTY_CYCLE      255
234 
+
235 
+// On-board LED pin number
236 
+#define LED_BUILTIN             PA7
237 
+#define LED_GREEN               LED_BUILTIN
238 
+
239 
+// Below SPI and I2C definitions already done in the core
240 
+// Could be redefined here if differs from the default one
241 
+// SPI Definitions
242 
+#define PIN_SPI_MOSI            PB15
243 
+#define PIN_SPI_MISO            PB14
244 
+#define PIN_SPI_SCK             PB13
245 
+#define PIN_SPI_SS              PB12
246 
+
247 
+// I2C Definitions
248 
+#if STM32F4X_PIN_NUM >= 176
249 
+  #define PIN_WIRE_SDA          PH5
250 
+  #define PIN_WIRE_SCL          PH4
251 
+#else
252 
+  #define PIN_WIRE_SDA          PB7
253 
+  #define PIN_WIRE_SCL          PB6
254 
+#endif
255 
+
256 
+// Timer Definitions
257 
+//Do not use timer used by PWM pins when possible. See PinMap_PWM in PeripheralPins.c
258 
+#define TIMER_TONE              TIM2
259 
+#define TIMER_SERVO             TIM5 // Only 1 Servo PIN on SKR-PRO, so use the same timer as defined in PeripheralPins
260 
+#define TIMER_SERIAL            TIM7
261 
+
262 
+// UART Definitions
263 
+//#define ENABLE_HWSERIAL1        done automatically by the #define SERIAL_UART_INSTANCE below
264 
+#define ENABLE_HWSERIAL3
265 
+#define ENABLE_HWSERIAL6
266 
+
267 
+// Define here Serial instance number to map on Serial generic name (if not already used by SerialUSB)
268 
+#define SERIAL_UART_INSTANCE    1 //1 for Serial = Serial1 (USART1)
269 
+
270 
+// DEBUG_UART could be redefined to print on another instance than 'Serial'
271 
+//#define DEBUG_UART              ((USART_TypeDef *) U(S)ARTX) // ex: USART3
272 
+// DEBUG_UART baudrate, default: 9600 if not defined
273 
+//#define DEBUG_UART_BAUDRATE     x
274 
+// DEBUG_UART Tx pin name, default: the first one found in PinMap_UART_TX for DEBUG_UART
275 
+//#define DEBUG_PINNAME_TX        PX_n // PinName used for TX
276 
+
277 
+// Default pin used for 'Serial' instance (ex: ST-Link)
278 
+// Mandatory for Firmata
279 
+#define PIN_SERIAL_RX           PA10
280 
+#define PIN_SERIAL_TX           PA9
281 
+
282 
+// Optional PIN_SERIALn_RX and PIN_SERIALn_TX where 'n' is the U(S)ART number
283 
+// Used when user instanciate a hardware Serial using its peripheral name.
284 
+// Example: HardwareSerial mySerial(USART3);
285 
+// will use PIN_SERIAL3_RX and PIN_SERIAL3_TX if defined.
286 
+#define PIN_SERIAL1_RX          PA10
287 
+#define PIN_SERIAL1_TX          PA9
288 
+#define PIN_SERIAL3_RX          PD9
289 
+#define PIN_SERIAL3_TX          PD8
290 
+#define PIN_SERIAL6_RX          PC7
291 
+#define PIN_SERIAL6_TX          PC6
292 
+//#define PIN_SERIALLP1_RX        x // For LPUART1 RX
293 
+//#define PIN_SERIALLP1_TX        x // For LPUART1 TX
294 
+
295 
+#ifdef __cplusplus
296 
+} // extern "C"
297 
+#endif
298 
+/*----------------------------------------------------------------------------
299 
+ *        Arduino objects - C++ only
300 
+ *----------------------------------------------------------------------------*/
301 
+
302 
+#ifdef __cplusplus
303 
+// These serial port names are intended to allow libraries and architecture-neutral
304 
+// sketches to automatically default to the correct port name for a particular type
305 
+// of use.  For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
306 
+// the first hardware serial port whose RX/TX pins are not dedicated to another use.
307 
+//
308 
+// SERIAL_PORT_MONITOR        Port which normally prints to the Arduino Serial Monitor
309 
+//
310 
+// SERIAL_PORT_USBVIRTUAL     Port which is USB virtual serial
311 
+//
312 
+// SERIAL_PORT_LINUXBRIDGE    Port which connects to a Linux system via Bridge library
313 
+//
314 
+// SERIAL_PORT_HARDWARE       Hardware serial port, physical RX & TX pins.
315 
+//
316 
+// SERIAL_PORT_HARDWARE_OPEN  Hardware serial ports which are open for use.  Their RX & TX
317 
+//                            pins are NOT connected to anything by default.
318 
+#define SERIAL_PORT_MONITOR         Serial
319 
+#define SERIAL_PORT_HARDWARE        Serial1
320 
+#define SERIAL_PORT_HARDWARE_OPEN   Serial3
321 
+#define SERIAL_PORT_HARDWARE_OPEN1  Serial6
322 
+#endif

+ 12
- 13
buildroot/share/PlatformIO/variants/BIGTREE_SKR_PRO_1v1/PeripheralPins.c Datei anzeigen 

@@ -94,7 +94,7 @@ const PinMap PinMap_I2C_SDA[] = {
94 94 
     #if STM32F4X_PIN_NUM >= 176
95 95 
       {PH_5,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
96 96 
       {PH_8,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
97 
-  	#else
97 
+    #else
98 98 
       {PF_0,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
99 99 
     #endif
100 100 
   #endif
 
@@ -113,7 +113,7 @@ const PinMap PinMap_I2C_SCL[] = {
113 113 
       //{PF_1,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
114 114 
       {PH_4,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
115 115 
       {PH_7,  I2C3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
116 
-  	#else
116 
+    #else
117 117 
       {PF_1,  I2C2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
118 118 
     #endif
119 119 
   #endif
 
@@ -152,8 +152,8 @@ const PinMap PinMap_PWM[] = {
152 152 
    */
153 153 
   //{PA_0,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
154 154 
   //{PA_0,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1
155 
-  {PA_1,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2   BLTOUCH is a "servo"
156 
-  {PA_2,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3   BLTOUCH is a "servo"
155 
+  //{PA_1,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2   BLTOUCH is a "servo"
156 
+  //{PA_2,  TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3   BLTOUCH is a "servo"
157 157 
   //{PA_1,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2
158 158 
   //{PA_2,  TIM5,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3
159 159 
   //{PA_2,  TIM9,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
 
@@ -186,7 +186,7 @@ const PinMap PinMap_PWM[] = {
186 186 
   //{PB_9,  TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
187 187 
   //{PB_9,  TIM11,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
188 188 
   //{PB_10, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
189 
-  {PB_11, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
189 
+  //{PB_11, TIM2,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
190 190 
   //{PB_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
191 191 
   //{PB_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
192 192 
   //{PB_14, TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N
 
@@ -199,15 +199,15 @@ const PinMap PinMap_PWM[] = {
199 199 
   //{PC_7,  TIM8,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2
200 200 
   //{PC_8,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
201 201 
   //{PC_9,  TIM3,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
202 
-  {PD_13, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
203 
-  {PD_15, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
202 
+  //{PD_13, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
203 
+  //{PD_15, TIM4,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
204 204 
   //{PE_8,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
205 
-  {PE_9,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
205 
+  //{PE_9,  TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
206 206 
   //{PE_10, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
207 
-  {PE_11, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
207 
+  //{PE_11, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
208 208 
   //{PE_12, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
209 
-  {PE_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
210 
-  {PE_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
209 
+  //{PE_13, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
210 
+  //{PE_14, TIM1,   STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
211 211 
   #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
212 212 
     //{PF_6,  TIM10,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
213 213 
     //{PF_7,  TIM11,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
 
@@ -295,8 +295,7 @@ const PinMap PinMap_UART_CTS[] = {
295 295
296 296 
 #ifdef HAL_SPI_MODULE_ENABLED
297 297 
 const PinMap PinMap_SPI_MOSI[] = {
298 
-  //{PB_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
299 
-  {PA_7,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
298 
+  {PB_5,  SPI1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
300 299 
   {PB_15, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
301 300 
   {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
302 301 
   {NC,    NP,    0}

+ 1
- 1
platformio.ini Datei anzeigen 

@@ -777,7 +777,7 @@ debug_init_break  =
777 777 
 [env:BIGTREE_GTR_V1_0]
778 778 
 platform          = ststm32@>=5.7.0
779 779 
 platform_packages = framework-arduinoststm32@${common.arduinoststm32_ver}
780 
-board             = BigTree_SKR_Pro
780 
+board             = BigTree_GTR_v1
781 781 
 extra_scripts     = pre:buildroot/share/PlatformIO/scripts/generic_create_variant.py
782 782 
 build_flags       = ${common.build_flags}
783 783 
   -DUSBCON -DUSBD_USE_CDC -DUSBD_VID=0x0483 -DUSB_PRODUCT=\"STM32F407IG\"

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