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@@ -346,7 +346,6 @@ extern "C" {
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346
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346
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void UART0_IRQHandler (void)
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347
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347
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{
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348
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348
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uint8_t IIRValue, LSRValue;
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349
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- uint8_t Dummy = Dummy;
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350
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349
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351
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350
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IIRValue = LPC_UART0->IIR;
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352
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351
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@@ -354,59 +353,59 @@ void UART0_IRQHandler (void)
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353
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
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355
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354
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if ( IIRValue == IIR_RLS ) /* Receive Line Status */
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356
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355
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{
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357
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- LSRValue = LPC_UART0->LSR;
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358
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- /* Receive Line Status */
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359
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- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
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360
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- {
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361
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- /* There are errors or break interrupt */
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362
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- /* Read LSR will clear the interrupt */
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363
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- UART0Status = LSRValue;
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364
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- Dummy = LPC_UART0->RBR; /* Dummy read on RX to clear
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365
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- interrupt, then bail out */
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366
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- return;
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367
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- }
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368
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- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
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369
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- {
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370
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- /* If no error on RLS, normal ready, save into the data buffer. */
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371
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- /* Note: read RBR will clear the interrupt */
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372
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- if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
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373
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- {
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374
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- UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
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375
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- UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
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376
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- }
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377
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- else
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378
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- dummy = LPC_UART0->RBR;;
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379
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- }
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356
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+ LSRValue = LPC_UART0->LSR;
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357
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+ /* Receive Line Status */
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358
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+ if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
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359
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+ {
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360
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+ /* There are errors or break interrupt */
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361
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+ /* Read LSR will clear the interrupt */
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362
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+ UART0Status = LSRValue;
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363
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+ dummy = LPC_UART0->RBR; /* Dummy read on RX to clear
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364
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+ interrupt, then bail out */
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365
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+ return;
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366
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+ }
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367
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+ if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
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368
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+ {
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369
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+ /* If no error on RLS, normal ready, save into the data buffer. */
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370
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+ /* Note: read RBR will clear the interrupt */
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371
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+ if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
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372
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+ {
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373
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+ UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
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374
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+ UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
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375
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+ }
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+ else
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377
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+ dummy = LPC_UART0->RBR;
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+ }
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380
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379
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}
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381
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380
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else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
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382
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381
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{
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383
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- /* Receive Data Available */
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382
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+ /* Receive Data Available */
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384
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383
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if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
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385
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384
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{
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386
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385
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UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
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387
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386
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UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
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388
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387
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}
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389
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388
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else
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390
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- dummy = LPC_UART1->RBR;;
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389
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+ dummy = LPC_UART1->RBR;
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391
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390
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}
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392
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391
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else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
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393
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392
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{
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394
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- /* Character Time-out indicator */
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395
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- UART0Status |= 0x100; /* Bit 9 as the CTI error */
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393
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+ /* Character Time-out indicator */
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394
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+ UART0Status |= 0x100; /* Bit 9 as the CTI error */
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396
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395
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}
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397
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396
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else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
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398
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397
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{
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399
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- /* THRE interrupt */
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400
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- LSRValue = LPC_UART0->LSR; /* Check status in the LSR to see if
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401
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- valid data in U0THR or not */
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402
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- if ( LSRValue & LSR_THRE )
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403
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- {
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404
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- UART0TxEmpty = 1;
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405
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- }
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406
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- else
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407
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- {
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408
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- UART0TxEmpty = 0;
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409
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- }
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398
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+ /* THRE interrupt */
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399
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+ LSRValue = LPC_UART0->LSR; /* Check status in the LSR to see if
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400
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+ valid data in U0THR or not */
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401
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+ if ( LSRValue & LSR_THRE )
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402
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+ {
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403
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+ UART0TxEmpty = 1;
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404
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+ }
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405
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+ else
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406
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+ {
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407
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+ UART0TxEmpty = 0;
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408
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+ }
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410
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409
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}
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411
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410
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}
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412
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411
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@@ -422,7 +421,6 @@ void UART0_IRQHandler (void)
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422
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421
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void UART1_IRQHandler (void)
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423
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422
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{
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424
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423
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uint8_t IIRValue, LSRValue;
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425
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- uint8_t Dummy = Dummy;
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426
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424
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427
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425
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IIRValue = LPC_UART1->IIR;
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428
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426
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@@ -430,61 +428,60 @@ void UART1_IRQHandler (void)
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430
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428
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
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431
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429
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if ( IIRValue == IIR_RLS ) /* Receive Line Status */
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432
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430
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{
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433
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- LSRValue = LPC_UART1->LSR;
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434
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- /* Receive Line Status */
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435
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- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
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436
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- {
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437
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- /* There are errors or break interrupt */
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438
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- /* Read LSR will clear the interrupt */
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439
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- UART1Status = LSRValue;
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440
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- Dummy = LPC_UART1->RBR; /* Dummy read on RX to clear
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441
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- interrupt, then bail out */
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442
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- return;
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443
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- }
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444
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- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
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445
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- {
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446
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- /* If no error on RLS, normal ready, save into the data buffer. */
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447
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- /* Note: read RBR will clear the interrupt */
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448
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- if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
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449
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- {
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450
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- UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
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451
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- UART1RxQueueWritePos =(UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
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452
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- }
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453
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- else
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454
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- dummy = LPC_UART1->RBR;;
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455
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- }
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431
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+ LSRValue = LPC_UART1->LSR;
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432
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+ /* Receive Line Status */
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433
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+ if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
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434
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+ {
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|
435
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+ /* There are errors or break interrupt */
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436
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+ /* Read LSR will clear the interrupt */
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437
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+ UART1Status = LSRValue;
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438
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+ dummy = LPC_UART1->RBR; /* Dummy read on RX to clear
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439
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+ interrupt, then bail out */
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440
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+ return;
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441
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+ }
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442
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+ if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
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443
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+ {
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444
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+ /* If no error on RLS, normal ready, save into the data buffer. */
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445
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+ /* Note: read RBR will clear the interrupt */
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|
446
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+ if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
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447
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+ {
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448
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+ UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
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449
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+ UART1RxQueueWritePos =(UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
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450
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+ }
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451
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+ else
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452
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+ dummy = LPC_UART1->RBR;
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453
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+ }
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456
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454
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}
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457
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455
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else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
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458
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456
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{
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459
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- /* Receive Data Available */
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457
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+ /* Receive Data Available */
|
460
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458
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if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
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461
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459
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{
|
462
|
460
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UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
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463
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461
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UART1RxQueueWritePos = (UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
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464
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462
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}
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465
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463
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else
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466
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- dummy = LPC_UART1->RBR;;
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|
464
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+ dummy = LPC_UART1->RBR;
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467
|
465
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}
|
468
|
466
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else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
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469
|
467
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{
|
470
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- /* Character Time-out indicator */
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471
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- UART1Status |= 0x100; /* Bit 9 as the CTI error */
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472
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- }
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473
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- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
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474
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- {
|
475
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- /* THRE interrupt */
|
476
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- LSRValue = LPC_UART1->LSR; /* Check status in the LSR to see if
|
477
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- valid data in U0THR or not */
|
478
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- if ( LSRValue & LSR_THRE )
|
479
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- {
|
480
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- UART1TxEmpty = 1;
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481
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- }
|
482
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- else
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483
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- {
|
484
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- UART1TxEmpty = 0;
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485
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- }
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|
468
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+ /* Character Time-out indicator */
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|
469
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+ UART1Status |= 0x100; /* Bit 9 as the CTI error */
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|
470
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+ }
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|
471
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+ else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
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|
472
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+ {
|
|
473
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+ /* THRE interrupt */
|
|
474
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+ LSRValue = LPC_UART1->LSR; /* Check status in the LSR to see if
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|
475
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+ valid data in U0THR or not */
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|
476
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+ if ( LSRValue & LSR_THRE )
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|
477
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+ {
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|
478
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+ UART1TxEmpty = 1;
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|
479
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+ }
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|
480
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+ else
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|
481
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+ {
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|
482
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+ UART1TxEmpty = 0;
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|
483
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+ }
|
486
|
484
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}
|
487
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-
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488
|
485
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}
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489
|
486
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/*****************************************************************************
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490
|
487
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** Function name: UART2_IRQHandler
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@@ -498,7 +495,6 @@ void UART1_IRQHandler (void)
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498
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495
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void UART2_IRQHandler (void)
|
499
|
496
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{
|
500
|
497
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uint8_t IIRValue, LSRValue;
|
501
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- uint8_t Dummy = Dummy;
|
502
|
498
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|
503
|
499
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IIRValue = LPC_UART2->IIR;
|
504
|
500
|
|
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@@ -506,57 +502,57 @@ void UART2_IRQHandler (void)
|
506
|
502
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IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
507
|
503
|
if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
508
|
504
|
{
|
509
|
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- LSRValue = LPC_UART2->LSR;
|
510
|
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- /* Receive Line Status */
|
511
|
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- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
512
|
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- {
|
513
|
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- /* There are errors or break interrupt */
|
514
|
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- /* Read LSR will clear the interrupt */
|
515
|
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- UART2Status = LSRValue;
|
516
|
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- Dummy = LPC_UART2->RBR; /* Dummy read on RX to clear
|
517
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- interrupt, then bail out */
|
518
|
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- return;
|
519
|
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- }
|
520
|
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- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
521
|
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- {
|
522
|
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- /* If no error on RLS, normal ready, save into the data buffer. */
|
523
|
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- /* Note: read RBR will clear the interrupt */
|
524
|
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- if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
|
525
|
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- {
|
526
|
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- UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
|
527
|
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- UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
528
|
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- }
|
529
|
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- }
|
|
505
|
+ LSRValue = LPC_UART2->LSR;
|
|
506
|
+ /* Receive Line Status */
|
|
507
|
+ if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
|
508
|
+ {
|
|
509
|
+ /* There are errors or break interrupt */
|
|
510
|
+ /* Read LSR will clear the interrupt */
|
|
511
|
+ UART2Status = LSRValue;
|
|
512
|
+ dummy = LPC_UART2->RBR; /* Dummy read on RX to clear
|
|
513
|
+ interrupt, then bail out */
|
|
514
|
+ return;
|
|
515
|
+ }
|
|
516
|
+ if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
|
517
|
+ {
|
|
518
|
+ /* If no error on RLS, normal ready, save into the data buffer. */
|
|
519
|
+ /* Note: read RBR will clear the interrupt */
|
|
520
|
+ if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
|
|
521
|
+ {
|
|
522
|
+ UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
|
|
523
|
+ UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
|
524
|
+ }
|
|
525
|
+ }
|
530
|
526
|
}
|
531
|
527
|
else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
532
|
528
|
{
|
533
|
|
- /* Receive Data Available */
|
|
529
|
+ /* Receive Data Available */
|
534
|
530
|
if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
|
535
|
531
|
{
|
536
|
532
|
UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
|
537
|
533
|
UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
538
|
534
|
}
|
539
|
535
|
else
|
540
|
|
- dummy = LPC_UART2->RBR;;
|
|
536
|
+ dummy = LPC_UART2->RBR;
|
541
|
537
|
}
|
542
|
538
|
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
543
|
539
|
{
|
544
|
|
- /* Character Time-out indicator */
|
545
|
|
- UART2Status |= 0x100; /* Bit 9 as the CTI error */
|
|
540
|
+ /* Character Time-out indicator */
|
|
541
|
+ UART2Status |= 0x100; /* Bit 9 as the CTI error */
|
546
|
542
|
}
|
547
|
543
|
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
548
|
544
|
{
|
549
|
|
- /* THRE interrupt */
|
550
|
|
- LSRValue = LPC_UART2->LSR; /* Check status in the LSR to see if
|
551
|
|
- valid data in U0THR or not */
|
552
|
|
- if ( LSRValue & LSR_THRE )
|
553
|
|
- {
|
554
|
|
- UART2TxEmpty = 1;
|
555
|
|
- }
|
556
|
|
- else
|
557
|
|
- {
|
558
|
|
- UART2TxEmpty = 0;
|
559
|
|
- }
|
|
545
|
+ /* THRE interrupt */
|
|
546
|
+ LSRValue = LPC_UART2->LSR; /* Check status in the LSR to see if
|
|
547
|
+ valid data in U0THR or not */
|
|
548
|
+ if ( LSRValue & LSR_THRE )
|
|
549
|
+ {
|
|
550
|
+ UART2TxEmpty = 1;
|
|
551
|
+ }
|
|
552
|
+ else
|
|
553
|
+ {
|
|
554
|
+ UART2TxEmpty = 0;
|
|
555
|
+ }
|
560
|
556
|
}
|
561
|
557
|
}
|
562
|
558
|
/*****************************************************************************
|
|
@@ -571,7 +567,6 @@ void UART2_IRQHandler (void)
|
571
|
567
|
void UART3_IRQHandler (void)
|
572
|
568
|
{
|
573
|
569
|
uint8_t IIRValue, LSRValue;
|
574
|
|
- uint8_t Dummy = Dummy;
|
575
|
570
|
|
576
|
571
|
IIRValue = LPC_UART3->IIR;
|
577
|
572
|
|
|
@@ -579,57 +574,57 @@ void UART3_IRQHandler (void)
|
579
|
574
|
IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
580
|
575
|
if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
581
|
576
|
{
|
582
|
|
- LSRValue = LPC_UART3->LSR;
|
583
|
|
- /* Receive Line Status */
|
584
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
585
|
|
- {
|
586
|
|
- /* There are errors or break interrupt */
|
587
|
|
- /* Read LSR will clear the interrupt */
|
588
|
|
- UART3Status = LSRValue;
|
589
|
|
- Dummy = LPC_UART3->RBR; /* Dummy read on RX to clear
|
590
|
|
- interrupt, then bail out */
|
591
|
|
- return;
|
592
|
|
- }
|
593
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
594
|
|
- {
|
595
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
596
|
|
- /* Note: read RBR will clear the interrupt */
|
597
|
|
- if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
|
598
|
|
- {
|
599
|
|
- UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
|
600
|
|
- UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
601
|
|
- }
|
602
|
|
- }
|
|
577
|
+ LSRValue = LPC_UART3->LSR;
|
|
578
|
+ /* Receive Line Status */
|
|
579
|
+ if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
|
580
|
+ {
|
|
581
|
+ /* There are errors or break interrupt */
|
|
582
|
+ /* Read LSR will clear the interrupt */
|
|
583
|
+ UART3Status = LSRValue;
|
|
584
|
+ dummy = LPC_UART3->RBR; /* Dummy read on RX to clear
|
|
585
|
+ interrupt, then bail out */
|
|
586
|
+ return;
|
|
587
|
+ }
|
|
588
|
+ if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
|
589
|
+ {
|
|
590
|
+ /* If no error on RLS, normal ready, save into the data buffer. */
|
|
591
|
+ /* Note: read RBR will clear the interrupt */
|
|
592
|
+ if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
|
|
593
|
+ {
|
|
594
|
+ UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
|
|
595
|
+ UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
|
596
|
+ }
|
|
597
|
+ }
|
603
|
598
|
}
|
604
|
599
|
else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
605
|
600
|
{
|
606
|
|
- /* Receive Data Available */
|
|
601
|
+ /* Receive Data Available */
|
607
|
602
|
if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
|
608
|
603
|
{
|
609
|
604
|
UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
|
610
|
605
|
UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
611
|
606
|
}
|
612
|
607
|
else
|
613
|
|
- dummy = LPC_UART3->RBR;;
|
|
608
|
+ dummy = LPC_UART3->RBR;
|
614
|
609
|
}
|
615
|
610
|
else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
616
|
611
|
{
|
617
|
|
- /* Character Time-out indicator */
|
618
|
|
- UART3Status |= 0x100; /* Bit 9 as the CTI error */
|
|
612
|
+ /* Character Time-out indicator */
|
|
613
|
+ UART3Status |= 0x100; /* Bit 9 as the CTI error */
|
619
|
614
|
}
|
620
|
615
|
else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
621
|
616
|
{
|
622
|
|
- /* THRE interrupt */
|
623
|
|
- LSRValue = LPC_UART3->LSR; /* Check status in the LSR to see if
|
624
|
|
- valid data in U0THR or not */
|
625
|
|
- if ( LSRValue & LSR_THRE )
|
626
|
|
- {
|
627
|
|
- UART3TxEmpty = 1;
|
628
|
|
- }
|
629
|
|
- else
|
630
|
|
- {
|
631
|
|
- UART3TxEmpty = 0;
|
632
|
|
- }
|
|
617
|
+ /* THRE interrupt */
|
|
618
|
+ LSRValue = LPC_UART3->LSR; /* Check status in the LSR to see if
|
|
619
|
+ valid data in U0THR or not */
|
|
620
|
+ if ( LSRValue & LSR_THRE )
|
|
621
|
+ {
|
|
622
|
+ UART3TxEmpty = 1;
|
|
623
|
+ }
|
|
624
|
+ else
|
|
625
|
+ {
|
|
626
|
+ UART3TxEmpty = 0;
|
|
627
|
+ }
|
633
|
628
|
}
|
634
|
629
|
}
|
635
|
630
|
|