thomas
/
marlin
Watch 1
Star 0
Fork 0
Code Issues 0 Pull Requests 0 Releases 0 Wiki Activity
Browse Source

Fix Bigtreetech STM32F40x variants ADC (#14996)

BigTreeTech 4 years ago
parent
67f8ba6fed
commit
bb4a252567
2 changed files with 233 additions and 257 deletions
Split View Show Diff Stats
  1. 90
    116
      buildroot/share/PlatformIO/variants/BIGTREE_GENERIC_STM32F407_5X/variant.cpp
  2. 143
    141
      buildroot/share/PlatformIO/variants/BIGTREE_GENERIC_STM32F407_5X/variant.h

+ 90
- 116
buildroot/share/PlatformIO/variants/BIGTREE_GENERIC_STM32F407_5X/variant.cpp View File 

@@ -44,98 +44,100 @@ const PinName digitalPin[] = {
44 44 
   PC_15, //D2  - OSC32_OUT
45 45 
   PH_0,  //D3  - OSC_IN
46 46 
   PH_1,  //D4  - OSC_OUT
47 
-  PC_0,  //D5  - 1:  2:ADC123_IN10
48 
-  PC_1,  //D6  - 1:  2:ADC123_IN11
49 
-  PC_2,  //D7  - 1:SPI2_MISO  2:ADC123_IN12
50 
-  PC_3,  //D8  - 1:SPI2_MOSI  2:ADC123_IN13
51 
-  PA_0,  //D9  - 1:UART4_TX / TIM5_CH1  2:ADC123_IN0
52 
-  PA_1,  //D10 - 1:UART4_RX / TIM5_CH2 / TIM2_CH2  2:ADC123_IN1
53 
-  PA_2,  //D11 - 1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3  2:ADC123_IN2
54 
-  PA_3,  //D12 - 1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4  2:ADC123_IN3
55 
-  PA_4,  //D13 - NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK  2:ADC12_IN4 / DAC_OUT1
56 
-  PA_5,  //D14 - NOT FT 1:SPI1_SCK  2:ADC12_IN5 / DAC_OUT2
57 
-  PA_6,  //D15 - 1:SPI1_MISO / TIM13_CH1 / TIM3_CH1  2:ADC12_IN6
58 
-  PA_7,  //D16 - 1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2  2:ADC12_IN7
59 
-  PC_4,  //D17 - 1:  2:ADC12_IN14
60 
-  PC_5,  //D18 - 1:  2:ADC12_IN15
61 
-  PB_0,  //D19 - 1:TIM3_CH3  2:ADC12_IN8
62 
-  PB_1,  //D20 - 1:TIM3_CH4  2:ADC12_IN9
63 
-  PB_2,  //D21 - BOOT1
64 
-  PB_10, //D22 - 1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
65 
-  PB_11, //D23 - 1:I2C2_SDA / USART3_RX / TIM2_CH4
66 
-  PB_12, //D24 - 1:SPI2_NSS / OTG_HS_ID
67 
-  PB_13, //D25 - 1:SPI2_SCK  2:OTG_HS_VBUS
68 
-  PB_14, //D26 - 1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
69 
-  PB_15, //D27 - SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
70 
-  PC_6,  //D28 - 1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
71 
-  PC_7,  //D29 - 1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
72 
-  PC_8,  //D30 - 1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
73 
-  PC_9,  //D31 - 1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
74 
-  PA_8,  //D32 - 1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
75 
-  PA_9,  //D33 - 1:USART1_TX / TIM1_CH2  2:OTG_FS_VBUS
76 
-  PA_10, //34 - 1:USART1_RX / TIM1_CH3 / OTG_FS_ID
77 
-  PA_11, //D35 - 1:TIM1_CH4 / OTG_FS_DM
78 
-  PA_12, //D36 - 1:OTG_FS_DP
79 
-  PA_13, //D37 - 0:JTMS-SWDIO
80 
-  PA_14, //D38 - 0:JTCK-SWCLK
81 
-  PA_15, //D39 - 0:JTDI  1:SPI3_NSS / SPI1_NSS
82 
-  PC_10, //D40 - 1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
83 
-  PC_11, //D41 - 1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
84 
-  PC_12, //D42 - 1:UART5_TX / SPI3_MOSI / SDIO_CK
85 
-  PD_2,  //D43 - 1:UART5_RX / SDIO_CMD
86 
-  PB_3,  //D44 - 0:JTDO  1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
87 
-  PB_4,  //D45 - 0:NJTRST  1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
88 
-  PB_5,  //D45 - 1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
89 
-  PB_6,  //D47 - 1:I2C1_SCL / TIM4_CH1 / USART1_TX
90 
-  PB_7,  //D48 - 1:I2C1_SDA / TIM4_CH2 / USART1_RX
91 
-  PB_8,  //D49 - 1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
92 
-  PB_9,  //D50 - 1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
47 
+  PB_2,  //D5  - BOOT1
48 
+  PB_10, //D6  - 1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
49 
+  PB_11, //D7  - 1:I2C2_SDA / USART3_RX / TIM2_CH4
50 
+  PB_12, //D8  - 1:SPI2_NSS / OTG_HS_ID
51 
+  PB_13, //D9  - 1:SPI2_SCK  2:OTG_HS_VBUS
52 
+  PB_14, //D10 - 1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
53 
+  PB_15, //D11 - SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
54 
+  PC_6,  //D12 - 1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
55 
+  PC_7,  //D13 - 1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
56 
+  PC_8,  //D14 - 1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
57 
+  PC_9,  //D15 - 1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
58 
+  PA_8,  //D16 - 1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
59 
+  PA_9,  //D17 - 1:USART1_TX / TIM1_CH2  2:OTG_FS_VBUS
60 
+  PA_10, //D18 - 1:USART1_RX / TIM1_CH3 / OTG_FS_ID
61 
+  PA_11, //D19 - 1:TIM1_CH4 / OTG_FS_DM
62 
+  PA_12, //D20 - 1:OTG_FS_DP
63 
+  PA_13, //D21 - 0:JTMS-SWDIO
64 
+  PA_14, //D22 - 0:JTCK-SWCLK
65 
+  PA_15, //D23 - 0:JTDI  1:SPI3_NSS / SPI1_NSS
66 
+  PC_10, //D24 - 1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
67 
+  PC_11, //D25 - 1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
68 
+  PC_12, //D26 - 1:UART5_TX / SPI3_MOSI / SDIO_CK
69 
+  PD_2,  //D27 - 1:UART5_RX / SDIO_CMD
70 
+  PB_3,  //D28 - 0:JTDO  1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
71 
+  PB_4,  //D29 - 0:NJTRST  1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
72 
+  PB_5,  //D30 - 1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
73 
+  PB_6,  //D31 - 1:I2C1_SCL / TIM4_CH1 / USART1_TX
74 
+  PB_7,  //D32 - 1:I2C1_SDA / TIM4_CH2 / USART1_RX
75 
+  PB_8,  //D33 - 1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
76 
+  PB_9,  //D34 - 1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
77 
+  PA_0,  //D35/A0 - 1:UART4_TX / TIM5_CH1  2:ADC123_IN0
78 
+  PA_1,  //D36/A1 - 1:UART4_RX / TIM5_CH2 / TIM2_CH2  2:ADC123_IN1
79 
+  PA_2,  //D37/A2 - 1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3  2:ADC123_IN2
80 
+  PA_3,  //D38/A3 - 1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4  2:ADC123_IN3
81 
+  PA_4,  //D39/A4 - NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK  2:ADC12_IN4 / DAC_OUT1
82 
+  PA_5,  //D40/A5 - NOT FT 1:SPI1_SCK  2:ADC12_IN5 / DAC_OUT2
83 
+  PA_6,  //D41/A6 - 1:SPI1_MISO / TIM13_CH1 / TIM3_CH1  2:ADC12_IN6
84 
+  PA_7,  //D42/A7 - 1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2  2:ADC12_IN7
85 
+  PB_0,  //D43/A8 - 1:TIM3_CH3  2:ADC12_IN8
86 
+  PB_1,  //D44/A9 - 1:TIM3_CH4  2:ADC12_IN9
87 
+  PC_0,  //D45/A10 - 1:  2:ADC123_IN10
88 
+  PC_1,  //D46/A11 - 1:  2:ADC123_IN11
89 
+  PC_2,  //D47/A12 - 1:SPI2_MISO  2:ADC123_IN12
90 
+  PC_3,  //D48/A13 - 1:SPI2_MOSI  2:ADC123_IN13
91 
+  PC_4,  //D49/A14 - 1:  2:ADC12_IN14
92 
+  PC_5,  //D50/A15 - 1:  2:ADC12_IN15
93 
+  #if STM32F4X_PIN_NUM >= 144
94 
+    PF_3,  //D51/A16 - 1:FSMC_A3  2:ADC3_IN9
95 
+    PF_4,  //D52/A17 - 1:FSMC_A4  2:ADC3_IN14
96 
+    PF_5,  //D53/A18 - 1:FSMC_A5  2:ADC3_IN15
97 
+    PF_6,  //D54/A19 - 1:TIM10_CH1  2:ADC3_IN4
98 
+    PF_7,  //D55/A20 - 1:TIM11_CH1  2:ADC3_IN5
99 
+    PF_8,  //D56/A21 - 1:TIM13_CH1  2:ADC3_IN6
100 
+    PF_9,  //D57/A22 - 1;TIM14_CH1  2:ADC3_IN7
101 
+    PF_10, //D58/A23 - 2:ADC3_IN8
102 
+  #endif
93 103 
 #endif
94 104 
 #if STM32F4X_PIN_NUM >= 100  //100 pins mcu, 82 gpio
95 
-  PE_2,  //D51 - 1:FSMC_A23
96 
-  PE_3,  //D52 - 1:FSMC_A19
97 
-  PE_4,  //D53 - 1:FSMC_A20
98 
-  PE_5,  //D54 - 1:FSMC_A21
99 
-  PE_6,  //D55 - 1:FSMC_A22
100 
-  PE_7,  //D56 - 1:FSMC_D4
101 
-  PE_8,  //D57 - 1:FSMC_D5
102 
-  PE_9,  //D58 - 1:FSMC_D6 / TIM1_CH1
103 
-  PE_10, //D59 - 1:FSMC_D7
104 
-  PE_11, //D60 - 1:FSMC_D8 / TIM1_CH2
105 
-  PE_12, //D61 - 1:FSMC_D9
106 
-  PE_13, //D62 - 1:FSMC_D10 / TIM1_CH3
107 
-  PE_14, //D63 - 1:FSMC_D11 / TIM1_CH4
108 
-  PE_15, //D64 - 1:FSMC_D12
109 
-  PD_8,  //D65 - 1:FSMC_D13 / USART3_TX
110 
-  PD_9,  //D66 - 1:FSMC_D14 / USART3_RX
111 
-  PD_10, //D67 - 1:FSMC_D15
112 
-  PD_11, //D68 - 1:FSMC_A16
113 
-  PD_12, //D69 - 1:FSMC_A17 / TIM4_CH1
114 
-  PD_13, //D70 - 1:FSMC_A18 / TIM4_CH2
115 
-  PD_14, //D71 - 1:FSMC_D0 / TIM4_CH3
116 
-  PD_15, //D72 - 1:FSMC_D1 / TIM4_CH4
117 
-  PD_0,  //D73 - 1:FSMC_D2
118 
-  PD_1,  //D74 - 1:FSMC_D3
119 
-  PD_3,  //D75 - 1:FSMC_CLK
120 
-  PD_4,  //D76 - 1:FSMC_NOE
121 
-  PD_5,  //D77 - 1:USART2_TX
122 
-  PD_6,  //D78 - 1:USART2_RX
123 
-  PD_7,  //D79
124 
-  PE_0,  //D80
125 
-  PE_1,  //D81
105 
+  PE_2,  //D59 - 1:FSMC_A23
106 
+  PE_3,  //D60 - 1:FSMC_A19
107 
+  PE_4,  //D61 - 1:FSMC_A20
108 
+  PE_5,  //D62 - 1:FSMC_A21
109 
+  PE_6,  //D63 - 1:FSMC_A22
110 
+  PE_7,  //D64 - 1:FSMC_D4
111 
+  PE_8,  //D65 - 1:FSMC_D5
112 
+  PE_9,  //D66 - 1:FSMC_D6 / TIM1_CH1
113 
+  PE_10, //D67 - 1:FSMC_D7
114 
+  PE_11, //D68 - 1:FSMC_D8 / TIM1_CH2
115 
+  PE_12, //D69 - 1:FSMC_D9
116 
+  PE_13, //D70 - 1:FSMC_D10 / TIM1_CH3
117 
+  PE_14, //D71 - 1:FSMC_D11 / TIM1_CH4
118 
+  PE_15, //D72 - 1:FSMC_D12
119 
+  PD_8,  //D73 - 1:FSMC_D13 / USART3_TX
120 
+  PD_9,  //D74 - 1:FSMC_D14 / USART3_RX
121 
+  PD_10, //D75 - 1:FSMC_D15
122 
+  PD_11, //D76 - 1:FSMC_A16
123 
+  PD_12, //D77 - 1:FSMC_A17 / TIM4_CH1
124 
+  PD_13, //D78 - 1:FSMC_A18 / TIM4_CH2
125 
+  PD_14, //D79 - 1:FSMC_D0 / TIM4_CH3
126 
+  PD_15, //D80 - 1:FSMC_D1 / TIM4_CH4
127 
+  PD_0,  //D81 - 1:FSMC_D2
128 
+  PD_1,  //D82 - 1:FSMC_D3
129 
+  PD_3,  //D83 - 1:FSMC_CLK
130 
+  PD_4,  //D84 - 1:FSMC_NOE
131 
+  PD_5,  //D85 - 1:USART2_TX
132 
+  PD_6,  //D86 - 1:USART2_RX
133 
+  PD_7,  //D87
134 
+  PE_0,  //D88
135 
+  PE_1,  //D89
126 136 
 #endif
127 137 
 #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
128 
-  PF_0,  //D82 - 1:FSMC_A0 / I2C2_SDA
129 
-  PF_1,  //D83 - 1:FSMC_A1 / I2C2_SCL
130 
-  PF_2,  //D84 - 1:FSMC_A2
131 
-  PF_3,  //D85 - 1:FSMC_A3  2:ADC3_IN9
132 
-  PF_4,  //D86 - 1:FSMC_A4  2:ADC3_IN14
133 
-  PF_5,  //D87 - 1:FSMC_A5  2:ADC3_IN15
134 
-  PF_6,  //D88 - 1:TIM10_CH1  2:ADC3_IN4
135 
-  PF_7,  //D89 - 1:TIM11_CH1  2:ADC3_IN5
136 
-  PF_8,  //D90 - 1:TIM13_CH1  2:ADC3_IN6
137 
-  PF_9,  //D91 - 1;TIM14_CH1  2:ADC3_IN7
138 
-  PF_10, //D92 - 2:ADC3_IN8
138 
+  PF_0,  //D90 - 1:FSMC_A0 / I2C2_SDA
139 
+  PF_1,  //D91 - 1:FSMC_A1 / I2C2_SCL
140 
+  PF_2,  //D92 - 1:FSMC_A2
139 141 
   PF_11, //D93
140 142 
   PF_12, //D94 - 1:FSMC_A6
141 143 
   PF_13, //D95 - 1:FSMC_A7
 
@@ -186,34 +188,6 @@ const PinName digitalPin[] = {
186 188 
   PI_6,  //D138 - 1:TIM8_CH2
187 189 
   PI_7,  //D139 - 1:TIM8_CH3
188 190 
 #endif
189 
-#if STM32F4X_PIN_NUM >= 64  //64 pins mcu, 51 gpio, 16 ADC
190 
-  PA_0,  //D140/A0 = D9  - 1:UART4_TX / TIM5_CH1  2:ADC123_IN0
191 
-  PA_1,  //D141/A1 = D10 - 1:UART4_RX / TIM5_CH2 / TIM2_CH2  2:ADC123_IN1
192 
-  PA_2,  //D142/A2 = D11 - 1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3  2:ADC123_IN2
193 
-  PA_3,  //D143/A3 = D12 - 1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4  2:ADC123_IN3
194 
-  PA_4,  //D144/A4 = D13 - NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK  2:ADC12_IN4 / DAC_OUT1
195 
-  PA_5,  //D145/A5 = D14 - NOT FT 1:SPI1_SCK  2:ADC12_IN5 / DAC_OUT2
196 
-  PA_6,  //D146/A6 = D15 - 1:SPI1_MISO / TIM13_CH1 / TIM3_CH1  2:ADC12_IN6
197 
-  PA_7,  //D147/A7 = D16 - 1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2  2:ADC12_IN7
198 
-  PB_0,  //D148/A8 = D19 - 1:TIM3_CH3  2:ADC12_IN8
199 
-  PB_1,  //D149/A9 = D20 - 1:TIM3_CH4  2:ADC12_IN9
200 
-  PC_0,  //D150/A10 = D5  - 1:  2:ADC123_IN10
201 
-  PC_1,  //D151/A11 = D6  - 1:  2:ADC123_IN11
202 
-  PC_2,  //D152/A12 = D7  - 1:SPI2_MISO  2:ADC123_IN12
203 
-  PC_3,  //D153/A13 = D8  - 1:SPI2_MOSI  2:ADC123_IN13
204 
-  PC_4,  //D154/A14 = D17 - 1:  2:ADC12_IN14
205 
-  PC_5,  //D155/A15 = D18 - 1:  2:ADC12_IN15
206 
-#endif
207 
-#if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio, 24 ADC
208 
-  PF_3,  //D156/A16 = D85 - 1:FSMC_A3  2:ADC3_IN9
209 
-  PF_4,  //D157/A17 = D86 - 1:FSMC_A4  2:ADC3_IN14
210 
-  PF_5,  //D158/A18 = D87 - 1:FSMC_A5  2:ADC3_IN15
211 
-  PF_6,  //D159/A19 = D88 - 1:TIM10_CH1  2:ADC3_IN4
212 
-  PF_7,  //D160/A20 = D89 - 1:TIM11_CH1  2:ADC3_IN5
213 
-  PF_8,  //D161/A21 = D90 - 1:TIM13_CH1  2:ADC3_IN6
214 
-  PF_9,  //D162/A22 = D91 - 1;TIM14_CH1  2:ADC3_IN7
215 
-  PF_10, //D163/A23 = D92 - 2:ADC3_IN8
216 
-#endif
217 191 
 };
218 192
219 193 
 #ifdef __cplusplus

+ 143
- 141
buildroot/share/PlatformIO/variants/BIGTREE_GENERIC_STM32F407_5X/variant.h View File 

@@ -65,159 +65,161 @@ extern const PinName digitalPin[];
65 65
66 66 
 #if STM32F4X_PIN_NUM >= 64  //64 pins mcu, 51 gpio
67 67 
   #define PC13  0
68 
-  #define PC14  1  //OSC32_IN
69 
-  #define PC15  2  //OSC32_OUT
70 
-  #define PH0   3  //OSC_IN
71 
-  #define PH1   4  //OSC_OUT
72 
-  #define PC0   5  //1:  2:ADC123_IN10
73 
-  #define PC1   6  //1:  2:ADC123_IN11
74 
-  #define PC2   7  //1:SPI2_MISO  2:ADC123_IN12
75 
-  #define PC3   8  //1:SPI2_MOSI  2:ADC123_IN13
76 
-  #define PA0   9  //1:UART4_TX / TIM5_CH1  2:ADC123_IN0
77 
-  #define PA1   10 //1:UART4_RX / TIM5_CH2 / TIM2_CH2  2:ADC123_IN1
78 
-  #define PA2   11 //1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3  2:ADC123_IN2
79 
-  #define PA3   12 //1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4  2:ADC123_IN3
80 
-  #define PA4   13 //NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK  2:ADC12_IN4 / DAC_OUT1
81 
-  #define PA5   14 //NOT FT 1:SPI1_SCK  2:ADC12_IN5 / DAC_OUT2
82 
-  #define PA6   15 //1:SPI1_MISO / TIM13_CH1 / TIM3_CH1  2:ADC12_IN6
83 
-  #define PA7   16 //1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2  2:ADC12_IN7
84 
-  #define PC4   17 //1:  2:ADC12_IN14
85 
-  #define PC5   18 //1:  2:ADC12_IN15
86 
-  #define PB0   19 //1:TIM3_CH3  2:ADC12_IN8
87 
-  #define PB1   20 //1:TIM3_CH4  2:ADC12_IN9
88 
-  #define PB2   21 //BOOT1
89 
-  #define PB10  22 //1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
90 
-  #define PB11  23 //1:I2C2_SDA / USART3_RX / TIM2_CH4
91 
-  #define PB12  24 //1:SPI2_NSS / OTG_HS_ID
92 
-  #define PB13  25 //1:SPI2_SCK  2:OTG_HS_VBUS
93 
-  #define PB14  26 //1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
94 
-  #define PB15  27 //SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
95 
-  #define PC6   28 //1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
96 
-  #define PC7   29 //1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
97 
-  #define PC8   30 //1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
98 
-  #define PC9   31 //1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
99 
-  #define PA8   32 //1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
100 
-  #define PA9   33 //1:USART1_TX / TIM1_CH2  2:OTG_FS_VBUS
101 
-  #define PA10  34 //1:USART1_RX / TIM1_CH3 / OTG_FS_ID
102 
-  #define PA11  35 //1:TIM1_CH4 / OTG_FS_DM
103 
-  #define PA12  36 //1:OTG_FS_DP
104 
-  #define PA13  37 //0:JTMS-SWDIO
105 
-  #define PA14  38 //0:JTCK-SWCLK
106 
-  #define PA15  39 //0:JTDI  1:SPI3_NSS / SPI1_NSS
107 
-  #define PC10  40 //1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
108 
-  #define PC11  41 //1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
109 
-  #define PC12  42 //1:UART5_TX / SPI3_MOSI / SDIO_CK
110 
-  #define PD2   43 //1:UART5_RX / SDIO_CMD
111 
-  #define PB3   44 //0:JTDO  1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
112 
-  #define PB4   45 //0:NJTRST  1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
113 
-  #define PB5   46 //1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
114 
-  #define PB6   47 //1:I2C1_SCL / TIM4_CH1 / USART1_TX
115 
-  #define PB7   48 //1:I2C1_SDA / TIM4_CH2 / USART1_RX
116 
-  #define PB8   49 //1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
117 
-  #define PB9   50 //1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
68 
+  #define PC14  1 //OSC32_IN
69 
+  #define PC15  2 //OSC32_OUT
70 
+  #define PH0   3 //OSC_IN
71 
+  #define PH1   4 //OSC_OUT
72 
+  #define PB2   5 //BOOT1
73 
+  #define PB10  6 //1:SPI2_SCK / I2C2_SCL / USART3_TX / TIM2_CH3
74 
+  #define PB11  7 //1:I2C2_SDA / USART3_RX / TIM2_CH4
75 
+  #define PB12  8 //1:SPI2_NSS / OTG_HS_ID
76 
+  #define PB13  9 //1:SPI2_SCK  2:OTG_HS_VBUS
77 
+  #define PB14  10 //1:SPI2_MISO / TIM12_CH1 / OTG_HS_DM
78 
+  #define PB15  11 //SPI2_MOSI / TIM12_CH2 / OTG_HS_DP
79 
+  #define PC6   12 //1:TIM8_CH1 / SDIO_D6 / USART6_TX / TIM3_CH1
80 
+  #define PC7   13 //1:TIM8_CH2 / SDIO_D7 / USART6_RX / TIM3_CH2
81 
+  #define PC8   14 //1:TIM8_CH3 / SDIO_D0 / TIM3_CH3
82 
+  #define PC9   15 //1:TIM8_CH4 / SDIO_D1 / TIM3_CH4
83 
+  #define PA8   16 //1:TIM1_CH1 / I2C3_SCL / OTG_FS_SOF
84 
+  #define PA9   17 //1:USART1_TX / TIM1_CH2  2:OTG_FS_VBUS
85 
+  #define PA10  18 //1:USART1_RX / TIM1_CH3 / OTG_FS_ID
86 
+  #define PA11  19 //1:TIM1_CH4 / OTG_FS_DM
87 
+  #define PA12  20 //1:OTG_FS_DP
88 
+  #define PA13  21 //0:JTMS-SWDIO
89 
+  #define PA14  22 //0:JTCK-SWCLK
90 
+  #define PA15  23 //0:JTDI  1:SPI3_NSS / SPI1_NSS
91 
+  #define PC10  24 //1:UART4_TX / SPI3_SCK / SDIO_D2 / USART3_TX
92 
+  #define PC11  25 //1:UART4_RX / SPI3_MISO / SDIO_D3 / USART3_RX
93 
+  #define PC12  26 //1:UART5_TX / SPI3_MOSI / SDIO_CK
94 
+  #define PD2   27 //1:UART5_RX / SDIO_CMD
95 
+  #define PB3   28 //0:JTDO  1:SPI3_SCK / TIM2_CH2 / SPI1_SCK
96 
+  #define PB4   29 //0:NJTRST  1:SPI3_MISO / TIM3_CH1 / SPI1_MISO
97 
+  #define PB5   30 //1:TIM3_CH2 / SPI1_MOSI / SPI3_MOSI
98 
+  #define PB6   31 //1:I2C1_SCL / TIM4_CH1 / USART1_TX
99 
+  #define PB7   32 //1:I2C1_SDA / TIM4_CH2 / USART1_RX
100 
+  #define PB8   33 //1:I2C1_SCL / TIM4_CH3 / SDIO_D4 / TIM10_CH1
101 
+  #define PB9   34 //1:I2C1_SDA / TIM4_CH4 / SDIO_D5 / TIM11_CH1 / SPI2_NSS
102 
+  #define PA0   35 //1:UART4_TX / TIM5_CH1  2:ADC123_IN0
103 
+  #define PA1   36 //1:UART4_RX / TIM5_CH2 / TIM2_CH2  2:ADC123_IN1
104 
+  #define PA2   37 //1:USART2_TX /TIM5_CH3 / TIM9_CH1 / TIM2_CH3  2:ADC123_IN2
105 
+  #define PA3   38 //1:USART2_RX /TIM5_CH4 / TIM9_CH2 / TIM2_CH4  2:ADC123_IN3
106 
+  #define PA4   39 //NOT FT 1:SPI1_NSS / SPI3_NSS / USART2_CK  2:ADC12_IN4 / DAC_OUT1
107 
+  #define PA5   40 //NOT FT 1:SPI1_SCK  2:ADC12_IN5 / DAC_OUT2
108 
+  #define PA6   41 //1:SPI1_MISO / TIM13_CH1 / TIM3_CH1  2:ADC12_IN6
109 
+  #define PA7   42 //1:SPI1_MOSI / TIM14_CH1 / TIM3_CH2  2:ADC12_IN7
110 
+  #define PB0   43 //1:TIM3_CH3  2:ADC12_IN8
111 
+  #define PB1   44 //1:TIM3_CH4  2:ADC12_IN9
112 
+  #define PC0   45 //1:  2:ADC123_IN10
113 
+  #define PC1   46 //1:  2:ADC123_IN11
114 
+  #define PC2   47 //1:SPI2_MISO  2:ADC123_IN12
115 
+  #define PC3   48 //1:SPI2_MOSI  2:ADC123_IN13
116 
+  #define PC4   49 //1:  2:ADC12_IN14
117 
+  #define PC5   50 //1:  2:ADC12_IN15
118 
+  #if STM32F4X_PIN_NUM >= 144
119 
+    #define PF3   51 //1:FSMC_A3  2:ADC3_IN9
120 
+    #define PF4   52 //1:FSMC_A4  2:ADC3_IN14
121 
+    #define PF5   53 //1:FSMC_A5  2:ADC3_IN15
122 
+    #define PF6   54 //1:TIM10_CH1  2:ADC3_IN4
123 
+    #define PF7   55 //1:TIM11_CH1  2:ADC3_IN5
124 
+    #define PF8   56 //1:TIM13_CH1  2:ADC3_IN6
125 
+    #define PF9   57 //1;TIM14_CH1  2:ADC3_IN7
126 
+    #define PF10  58 //2:ADC3_IN8
127 
+  #endif
118 128 
 #endif
119 129 
 #if STM32F4X_PIN_NUM >= 100  //100 pins mcu, 82 gpio
120 
-  #define PE2   51 //1:FSMC_A23
121 
-  #define PE3   52 //1:FSMC_A19
122 
-  #define PE4   53 //1:FSMC_A20
123 
-  #define PE5   54 //1:FSMC_A21
124 
-  #define PE6   55 //1:FSMC_A22
125 
-  #define PE7   56 //1:FSMC_D4
126 
-  #define PE8   57 //1:FSMC_D5
127 
-  #define PE9   58 //1:FSMC_D6 / TIM1_CH1
128 
-  #define PE10  59 //1:FSMC_D7
129 
-  #define PE11  60 //1:FSMC_D8 / TIM1_CH2
130 
-  #define PE12  61 //1:FSMC_D9
131 
-  #define PE13  62 //1:FSMC_D10 / TIM1_CH3
132 
-  #define PE14  63 //1:FSMC_D11 / TIM1_CH4
133 
-  #define PE15  64 //1:FSMC_D12
134 
-  #define PD8   65 //1:FSMC_D13 / USART3_TX
135 
-  #define PD9   66 //1:FSMC_D14 / USART3_RX
136 
-  #define PD10  67 //1:FSMC_D15
137 
-  #define PD11  68 //1:FSMC_A16
138 
-  #define PD12  69 //1:FSMC_A17 / TIM4_CH1
139 
-  #define PD13  70 //1:FSMC_A18 / TIM4_CH2
140 
-  #define PD14  71 //1:FSMC_D0 / TIM4_CH3
141 
-  #define PD15  72 //1:FSMC_D1 / TIM4_CH4
142 
-  #define PD0   73 //1:FSMC_D2
143 
-  #define PD1   74 //1:FSMC_D3
144 
-  #define PD3   75 //1:FSMC_CLK
145 
-  #define PD4   76 //1:FSMC_NOE
146 
-  #define PD5   77 //1:USART2_TX
147 
-  #define PD6   78 //1:USART2_RX
148 
-  #define PD7   79
149 
-  #define PE0   80
150 
-  #define PE1   81
130 
+  #define PE2   (35+STM32F4X_ADC_NUM) //1:FSMC_A23
131 
+  #define PE3   (36+STM32F4X_ADC_NUM) //1:FSMC_A19
132 
+  #define PE4   (37+STM32F4X_ADC_NUM) //1:FSMC_A20
133 
+  #define PE5   (38+STM32F4X_ADC_NUM) //1:FSMC_A21
134 
+  #define PE6   (39+STM32F4X_ADC_NUM) //1:FSMC_A22
135 
+  #define PE7   (40+STM32F4X_ADC_NUM) //1:FSMC_D4
136 
+  #define PE8   (41+STM32F4X_ADC_NUM) //1:FSMC_D5
137 
+  #define PE9   (42+STM32F4X_ADC_NUM) //1:FSMC_D6 / TIM1_CH1
138 
+  #define PE10  (43+STM32F4X_ADC_NUM) //1:FSMC_D7
139 
+  #define PE11  (44+STM32F4X_ADC_NUM) //1:FSMC_D8 / TIM1_CH2
140 
+  #define PE12  (45+STM32F4X_ADC_NUM) //1:FSMC_D9
141 
+  #define PE13  (46+STM32F4X_ADC_NUM) //1:FSMC_D10 / TIM1_CH3
142 
+  #define PE14  (47+STM32F4X_ADC_NUM) //1:FSMC_D11 / TIM1_CH4
143 
+  #define PE15  (48+STM32F4X_ADC_NUM) //1:FSMC_D12
144 
+  #define PD8   (49+STM32F4X_ADC_NUM) //1:FSMC_D13 / USART3_TX
145 
+  #define PD9   (50+STM32F4X_ADC_NUM) //1:FSMC_D14 / USART3_RX
146 
+  #define PD10  (51+STM32F4X_ADC_NUM) //1:FSMC_D15
147 
+  #define PD11  (52+STM32F4X_ADC_NUM) //1:FSMC_A16
148 
+  #define PD12  (53+STM32F4X_ADC_NUM) //1:FSMC_A17 / TIM4_CH1
149 
+  #define PD13  (54+STM32F4X_ADC_NUM) //1:FSMC_A18 / TIM4_CH2
150 
+  #define PD14  (55+STM32F4X_ADC_NUM) //1:FSMC_D0 / TIM4_CH3
151 
+  #define PD15  (56+STM32F4X_ADC_NUM) //1:FSMC_D1 / TIM4_CH4
152 
+  #define PD0   (57+STM32F4X_ADC_NUM) //1:FSMC_D2
153 
+  #define PD1   (58+STM32F4X_ADC_NUM) //1:FSMC_D3
154 
+  #define PD3   (59+STM32F4X_ADC_NUM) //1:FSMC_CLK
155 
+  #define PD4   (60+STM32F4X_ADC_NUM) //1:FSMC_NOE
156 
+  #define PD5   (61+STM32F4X_ADC_NUM) //1:USART2_TX
157 
+  #define PD6   (62+STM32F4X_ADC_NUM) //1:USART2_RX
158 
+  #define PD7   (63+STM32F4X_ADC_NUM)
159 
+  #define PE0   (64+STM32F4X_ADC_NUM)
160 
+  #define PE1   (65+STM32F4X_ADC_NUM)
151 161 
 #endif
152 162 
 #if STM32F4X_PIN_NUM >= 144  //144 pins mcu, 114 gpio
153 
-  #define PF0   82 //1:FSMC_A0 / I2C2_SDA
154 
-  #define PF1   83 //1:FSMC_A1 / I2C2_SCL
155 
-  #define PF2   84 //1:FSMC_A2
156 
-  #define PF3   85 //1:FSMC_A3  2:ADC3_IN9
157 
-  #define PF4   86 //1:FSMC_A4  2:ADC3_IN14
158 
-  #define PF5   87 //1:FSMC_A5  2:ADC3_IN15
159 
-  #define PF6   88 //1:TIM10_CH1  2:ADC3_IN4
160 
-  #define PF7   89 //1:TIM11_CH1  2:ADC3_IN5
161 
-  #define PF8   90 //1:TIM13_CH1  2:ADC3_IN6
162 
-  #define PF9   91 //1;TIM14_CH1  2:ADC3_IN7
163 
-  #define PF10  92 //2:ADC3_IN8
164 
-  #define PF11  93
165 
-  #define PF12  94 //1:FSMC_A6
166 
-  #define PF13  95 //1:FSMC_A7
167 
-  #define PF14  96 //1:FSMC_A8
168 
-  #define PF15  97 //1:FSMC_A9
169 
-  #define PG0   98 //1:FSMC_A10
170 
-  #define PG1   99 //1:FSMC_A11
171 
-  #define PG2   100 //1:FSMC_A12
172 
-  #define PG3   101 //1:FSMC_A13
173 
-  #define PG4   102 //1:FSMC_A14
174 
-  #define PG5   103 //1:FSMC_A15
175 
-  #define PG6   104
176 
-  #define PG7   105
177 
-  #define PG8   106
178 
-  #define PG9   107 //1:USART6_RX
179 
-  #define PG10  108 //1:FSMC_NE3
180 
-  #define PG11  109
181 
-  #define PG12  110 //1:FSMC_NE4
182 
-  #define PG13  111 //1:FSMC_A24
183 
-  #define PG14  112 //1:FSMC_A25 / USART6_TX
184 
-  #define PG15  113
163 
+  #define PF0   (66+STM32F4X_ADC_NUM) //1:FSMC_A0 / I2C2_SDA
164 
+  #define PF1   (67+STM32F4X_ADC_NUM) //1:FSMC_A1 / I2C2_SCL
165 
+  #define PF2   (68+STM32F4X_ADC_NUM) //1:FSMC_A2
166 
+  #define PF11  (69+STM32F4X_ADC_NUM)
167 
+  #define PF12  (70+STM32F4X_ADC_NUM) //1:FSMC_A6
168 
+  #define PF13  (71+STM32F4X_ADC_NUM) //1:FSMC_A7
169 
+  #define PF14  (72+STM32F4X_ADC_NUM) //1:FSMC_A8
170 
+  #define PF15  (73+STM32F4X_ADC_NUM) //1:FSMC_A9
171 
+  #define PG0   (74+STM32F4X_ADC_NUM) //1:FSMC_A10
172 
+  #define PG1   (75+STM32F4X_ADC_NUM) //1:FSMC_A11
173 
+  #define PG2   (76+STM32F4X_ADC_NUM) //1:FSMC_A12
174 
+  #define PG3   (77+STM32F4X_ADC_NUM) //1:FSMC_A13
175 
+  #define PG4   (78+STM32F4X_ADC_NUM) //1:FSMC_A14
176 
+  #define PG5   (79+STM32F4X_ADC_NUM) //1:FSMC_A15
177 
+  #define PG6   (80+STM32F4X_ADC_NUM)
178 
+  #define PG7   (81+STM32F4X_ADC_NUM)
179 
+  #define PG8   (82+STM32F4X_ADC_NUM)
180 
+  #define PG9   (83+STM32F4X_ADC_NUM) //1:USART6_RX
181 
+  #define PG10  (84+STM32F4X_ADC_NUM) //1:FSMC_NE3
182 
+  #define PG11  (85+STM32F4X_ADC_NUM)
183 
+  #define PG12  (86+STM32F4X_ADC_NUM) //1:FSMC_NE4
184 
+  #define PG13  (87+STM32F4X_ADC_NUM) //1:FSMC_A24
185 
+  #define PG14  (88+STM32F4X_ADC_NUM) //1:FSMC_A25 / USART6_TX
186 
+  #define PG15  (89+STM32F4X_ADC_NUM)
185 187 
 #endif
186 188 
 #if STM32F4X_PIN_NUM >= 176  //176 pins mcu, 140 gpio
187 
-  #define PI8   114
188 
-  #define PI9   115
189 
-  #define PI10  116
190 
-  #define PI11  117
191 
-  #define PH2   118
192 
-  #define PH3   119
193 
-  #define PH4   120 //1:I2C2_SCL
194 
-  #define PH5   121 //1:I2C2_SDA
195 
-  #define PH6   122 //1:TIM12_CH1
196 
-  #define PH7   123 //1:I2C3_SCL
197 
-  #define PH8   124 //1:I2C3_SDA
198 
-  #define PH9   125 //1:TIM12_CH2
199 
-  #define PH10  126 //1:TIM5_CH1
200 
-  #define PH11  127 //1:TIM5_CH2
201 
-  #define PH12  128 //1:TIM5_CH3
202 
-  #define PH13  129
203 
-  #define PH14  130
204 
-  #define PH15  131
205 
-  #define PI0   132 //1:TIM5_CH4 / SPI2_NSS
206 
-  #define PI1   133 //1:SPI2_SCK
207 
-  #define PI2   134 //1:TIM8_CH4 /SPI2_MISO
208 
-  #define PI3   135 //1:SPI2_MOS
209 
-  #define PI4   136
210 
-  #define PI5   137 //1:TIM8_CH1
211 
-  #define PI6   138 //1:TIM8_CH2
212 
-  #define PI7   139 //1:TIM8_CH3
189 
+  #define PI8   (90+STM32F4X_ADC_NUM)
190 
+  #define PI9   (91+STM32F4X_ADC_NUM)
191 
+  #define PI10  (92+STM32F4X_ADC_NUM)
192 
+  #define PI11  (93+STM32F4X_ADC_NUM)
193 
+  #define PH2   (94+STM32F4X_ADC_NUM)
194 
+  #define PH3   (95+STM32F4X_ADC_NUM)
195 
+  #define PH4   (96+STM32F4X_ADC_NUM) //1:I2C2_SCL
196 
+  #define PH5   (97+STM32F4X_ADC_NUM) //1:I2C2_SDA
197 
+  #define PH6   (98+STM32F4X_ADC_NUM) //1:TIM12_CH1
198 
+  #define PH7   (99+STM32F4X_ADC_NUM) //1:I2C3_SCL
199 
+  #define PH8   (100+STM32F4X_ADC_NUM) //1:I2C3_SDA
200 
+  #define PH9   (101+STM32F4X_ADC_NUM) //1:TIM12_CH2
201 
+  #define PH10  (102+STM32F4X_ADC_NUM) //1:TIM5_CH1
202 
+  #define PH11  (103+STM32F4X_ADC_NUM) //1:TIM5_CH2
203 
+  #define PH12  (104+STM32F4X_ADC_NUM) //1:TIM5_CH3
204 
+  #define PH13  (105+STM32F4X_ADC_NUM)
205 
+  #define PH14  (106+STM32F4X_ADC_NUM)
206 
+  #define PH15  (107+STM32F4X_ADC_NUM)
207 
+  #define PI0   (108+STM32F4X_ADC_NUM) //1:TIM5_CH4 / SPI2_NSS
208 
+  #define PI1   (109+STM32F4X_ADC_NUM) //1:SPI2_SCK
209 
+  #define PI2   (110+STM32F4X_ADC_NUM) //1:TIM8_CH4 /SPI2_MISO
210 
+  #define PI3   (111+STM32F4X_ADC_NUM) //1:SPI2_MOS
211 
+  #define PI4   (112+STM32F4X_ADC_NUM)
212 
+  #define PI5   (113+STM32F4X_ADC_NUM) //1:TIM8_CH1
213 
+  #define PI6   (114+STM32F4X_ADC_NUM) //1:TIM8_CH2
214 
+  #define PI7   (115+STM32F4X_ADC_NUM) //1:TIM8_CH3
213 215 
 #endif
214 216
215 217
216 218 
 // This must be a literal
217 
-#define NUM_DIGITAL_PINS        (STM32F4X_GPIO_NUM + STM32F4X_ADC_NUM)
219 
+#define NUM_DIGITAL_PINS        (STM32F4X_GPIO_NUM)
218 220 
 // This must be a literal with a value less than or equal to MAX_ANALOG_INPUTS
219 221 
 #define NUM_ANALOG_INPUTS       (STM32F4X_ADC_NUM)
220 
-#define NUM_ANALOG_FIRST        (STM32F4X_GPIO_NUM)
222 
+#define NUM_ANALOG_FIRST        35
221 223
222 224 
 // Below ADC, DAC and PWM definitions already done in the core
223 225 
 // Could be redefined here if needed

Write Preview
Loading…
Cancel
Save