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@@ -35,606 +35,301 @@ volatile uint32_t UART0RxQueueWritePos = 0, UART1RxQueueWritePos = 0, UART2RxQue
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volatile uint32_t UART0RxQueueReadPos = 0, UART1RxQueueReadPos = 0, UART2RxQueueReadPos = 0, UART3RxQueueReadPos = 0;
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volatile uint8_t dummy;
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- void HardwareSerial::begin(uint32_t baudrate) {
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- uint32_t Fdiv;
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- uint32_t pclkdiv, pclk;
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-
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- if ( PortNum == 0 )
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- {
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- LPC_PINCON->PINSEL0 &= ~0x000000F0;
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- LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 6~7 is for UART0 */
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- pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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-
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- LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART0->DLM = Fdiv / 256;
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- LPC_UART0->DLL = Fdiv % 256;
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- LPC_UART0->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART0_IRQn);
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-
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- LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART0 interrupt */
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- }
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- else if ( PortNum == 1 )
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- {
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- LPC_PINCON->PINSEL4 &= ~0x0000000F;
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- LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
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-
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 8,9 are for UART1 */
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- pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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-
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- LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART1->DLM = Fdiv / 256;
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- LPC_UART1->DLL = Fdiv % 256;
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- LPC_UART1->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART1_IRQn);
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-
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- LPC_UART1->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART1 interrupt */
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- }
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- else if ( PortNum == 2 )
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- {
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- //LPC_PINCON->PINSEL4 &= ~0x000F0000; /*Pinsel4 Bits 16-19*/
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- //LPC_PINCON->PINSEL4 |= 0x000A0000; /* RxD2 is P2.9 and TxD2 is P2.8, value 10*/
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- LPC_PINCON->PINSEL0 &= ~0x00F00000; /*Pinsel0 Bits 20-23*/
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- LPC_PINCON->PINSEL0 |= 0x00500000; /* RxD2 is P0.11 and TxD2 is P0.10, value 01*/
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-
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- LPC_SC->PCONP |= 1<<24; //Enable PCUART2
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 6~7 is for UART3 */
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- pclkdiv = (LPC_SC->PCLKSEL1 >> 16) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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- LPC_UART2->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART2->DLM = Fdiv / 256;
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- LPC_UART2->DLL = Fdiv % 256;
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- LPC_UART2->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART2->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART2_IRQn);
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-
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- LPC_UART2->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
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- }
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- else if ( PortNum == 3 )
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- {
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- LPC_PINCON->PINSEL0 &= ~0x0000000F;
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- LPC_PINCON->PINSEL0 |= 0x0000000A; /* RxD3 is P0.1 and TxD3 is P0.0 */
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- LPC_SC->PCONP |= 1<<4 | 1<<25; //Enable PCUART1
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- /* By default, the PCLKSELx value is zero, thus, the PCLK for
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- all the peripherals is 1/4 of the SystemFrequency. */
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- /* Bit 6~7 is for UART3 */
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- pclkdiv = (LPC_SC->PCLKSEL1 >> 18) & 0x03;
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- switch ( pclkdiv )
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- {
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- case 0x00:
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- default:
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- pclk = SystemCoreClock/4;
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- break;
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- case 0x01:
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- pclk = SystemCoreClock;
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- break;
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- case 0x02:
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- pclk = SystemCoreClock/2;
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- break;
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- case 0x03:
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- pclk = SystemCoreClock/8;
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- break;
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- }
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- LPC_UART3->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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- Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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- LPC_UART3->DLM = Fdiv / 256;
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- LPC_UART3->DLL = Fdiv % 256;
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- LPC_UART3->LCR = 0x03; /* DLAB = 0 */
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- LPC_UART3->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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-
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- NVIC_EnableIRQ(UART3_IRQn);
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-
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- LPC_UART3->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
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- }
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- }
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-
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- int HardwareSerial::read() {
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- uint8_t rx;
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- if ( PortNum == 0 )
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- {
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- if (UART0RxQueueReadPos == UART0RxQueueWritePos)
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- return -1;
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-
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- // Read from "head"
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- rx = UART0Buffer[UART0RxQueueReadPos]; // grab next byte
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- UART0RxQueueReadPos = (UART0RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- if ( PortNum == 1 )
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- {
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- if (UART1RxQueueReadPos == UART1RxQueueWritePos)
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- return -1;
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+void HardwareSerial::begin(uint32_t baudrate) {
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+ uint32_t Fdiv, pclkdiv, pclk;
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+
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+ if (PortNum == 0) {
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+ LPC_PINCON->PINSEL0 &= ~0x000000F0;
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+ LPC_PINCON->PINSEL0 |= 0x00000050; /* RxD0 is P0.3 and TxD0 is P0.2 */
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+ /* By default, the PCLKSELx value is zero, thus, the PCLK for
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+ all the peripherals is 1/4 of the SystemFrequency. */
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+ /* Bit 6~7 is for UART0 */
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+ pclkdiv = (LPC_SC->PCLKSEL0 >> 6) & 0x03;
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+ switch (pclkdiv) {
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+ case 0x00:
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+ default:
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+ pclk = SystemCoreClock / 4;
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+ break;
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+ case 0x01:
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+ pclk = SystemCoreClock;
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+ break;
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+ case 0x02:
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+ pclk = SystemCoreClock / 2;
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+ break;
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+ case 0x03:
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+ pclk = SystemCoreClock / 8;
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+ break;
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+ }
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- // Read from "head"
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- rx = UART1Buffer[UART1RxQueueReadPos]; // grab next byte
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- UART1RxQueueReadPos = (UART1RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- if ( PortNum == 2 )
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- {
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- if (UART2RxQueueReadPos == UART2RxQueueWritePos)
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- return -1;
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+ LPC_UART0->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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+ Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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+ LPC_UART0->DLM = Fdiv / 256;
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+ LPC_UART0->DLL = Fdiv % 256;
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+ LPC_UART0->LCR = 0x03; /* DLAB = 0 */
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+ LPC_UART0->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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- // Read from "head"
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- rx = UART2Buffer[UART2RxQueueReadPos]; // grab next byte
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- UART2RxQueueReadPos = (UART2RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- if ( PortNum == 3 )
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- {
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- if (UART3RxQueueReadPos == UART3RxQueueWritePos)
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- return -1;
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+ NVIC_EnableIRQ(UART0_IRQn);
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- // Read from "head"
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- rx = UART3Buffer[UART3RxQueueReadPos]; // grab next byte
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- UART3RxQueueReadPos = (UART3RxQueueReadPos + 1) % UARTRXQUEUESIZE;
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- return rx;
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- }
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- return 0;
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+ LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART0 interrupt */
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}
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+ else if (PortNum == 1) {
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+ LPC_PINCON->PINSEL4 &= ~0x0000000F;
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+ LPC_PINCON->PINSEL4 |= 0x0000000A; /* Enable RxD1 P2.1, TxD1 P2.0 */
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+
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+ /* By default, the PCLKSELx value is zero, thus, the PCLK for
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+ all the peripherals is 1/4 of the SystemFrequency. */
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+ /* Bit 8,9 are for UART1 */
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+ pclkdiv = (LPC_SC->PCLKSEL0 >> 8) & 0x03;
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+ switch (pclkdiv) {
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+ case 0x00:
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+ default:
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+ pclk = SystemCoreClock / 4;
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+ break;
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+ case 0x01:
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+ pclk = SystemCoreClock;
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+ break;
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+ case 0x02:
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+ pclk = SystemCoreClock / 2;
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+ break;
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+ case 0x03:
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+ pclk = SystemCoreClock / 8;
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+ break;
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+ }
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- size_t HardwareSerial::write(uint8_t send) {
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- if ( PortNum == 0 )
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- {
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- /* THRE status, contain valid data */
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- while ( !(UART0TxEmpty & 0x01) );
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- LPC_UART0->THR = send;
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- UART0TxEmpty = 0; /* not empty in the THR until it shifts out */
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- }
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- else if (PortNum == 1)
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- {
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-
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- /* THRE status, contain valid data */
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- while ( !(UART1TxEmpty & 0x01) );
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- LPC_UART1->THR = send;
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- UART1TxEmpty = 0; /* not empty in the THR until it shifts out */
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-
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-
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- }
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- else if ( PortNum == 2 )
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- {
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- /* THRE status, contain valid data */
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- while ( !(UART2TxEmpty & 0x01) );
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- LPC_UART2->THR = send;
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- UART2TxEmpty = 0; /* not empty in the THR until it shifts out */
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-
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- }
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- else if ( PortNum == 3 )
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- {
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- /* THRE status, contain valid data */
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- while ( !(UART3TxEmpty & 0x01) );
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- LPC_UART3->THR = send;
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- UART3TxEmpty = 0; /* not empty in the THR until it shifts out */
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+ LPC_UART1->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
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+ Fdiv = ( pclk / 16 ) / baudrate ; /*baud rate */
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+ LPC_UART1->DLM = Fdiv / 256;
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+ LPC_UART1->DLL = Fdiv % 256;
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+ LPC_UART1->LCR = 0x03; /* DLAB = 0 */
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+ LPC_UART1->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
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- }
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- return 0;
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- }
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+ NVIC_EnableIRQ(UART1_IRQn);
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107
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- int HardwareSerial::available() {
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- if ( PortNum == 0 )
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-{
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- return (UART0RxQueueWritePos + UARTRXQUEUESIZE - UART0RxQueueReadPos) % UARTRXQUEUESIZE;
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-}
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-if ( PortNum == 1 )
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-{
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- return (UART1RxQueueWritePos + UARTRXQUEUESIZE - UART1RxQueueReadPos) % UARTRXQUEUESIZE;
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-}
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-if ( PortNum == 2 )
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-{
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- return (UART2RxQueueWritePos + UARTRXQUEUESIZE - UART2RxQueueReadPos) % UARTRXQUEUESIZE;
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-}
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-if ( PortNum == 3 )
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-{
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- return (UART3RxQueueWritePos + UARTRXQUEUESIZE - UART3RxQueueReadPos) % UARTRXQUEUESIZE;
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-}
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-return 0;
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+ LPC_UART1->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART1 interrupt */
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}
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+ else if (PortNum == 2) {
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111
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+ //LPC_PINCON->PINSEL4 &= ~0x000F0000; /*Pinsel4 Bits 16-19*/
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112
|
+ //LPC_PINCON->PINSEL4 |= 0x000A0000; /* RxD2 is P2.9 and TxD2 is P2.8, value 10*/
|
|
113
|
+ LPC_PINCON->PINSEL0 &= ~0x00F00000; /*Pinsel0 Bits 20-23*/
|
|
114
|
+ LPC_PINCON->PINSEL0 |= 0x00500000; /* RxD2 is P0.11 and TxD2 is P0.10, value 01*/
|
|
115
|
+
|
|
116
|
+ LPC_SC->PCONP |= 1 << 24; //Enable PCUART2
|
|
117
|
+ /* By default, the PCLKSELx value is zero, thus, the PCLK for
|
|
118
|
+ all the peripherals is 1/4 of the SystemFrequency. */
|
|
119
|
+ /* Bit 6~7 is for UART3 */
|
|
120
|
+ pclkdiv = (LPC_SC->PCLKSEL1 >> 16) & 0x03;
|
|
121
|
+ switch (pclkdiv) {
|
|
122
|
+ case 0x00:
|
|
123
|
+ default:
|
|
124
|
+ pclk = SystemCoreClock / 4;
|
|
125
|
+ break;
|
|
126
|
+ case 0x01:
|
|
127
|
+ pclk = SystemCoreClock;
|
|
128
|
+ break;
|
|
129
|
+ case 0x02:
|
|
130
|
+ pclk = SystemCoreClock / 2;
|
|
131
|
+ break;
|
|
132
|
+ case 0x03:
|
|
133
|
+ pclk = SystemCoreClock / 8;
|
|
134
|
+ break;
|
|
135
|
+ }
|
|
136
|
+ LPC_UART2->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
|
137
|
+ Fdiv = (pclk / 16) / baudrate; /*baud rate */
|
|
138
|
+ LPC_UART2->DLM = Fdiv >> 8;
|
|
139
|
+ LPC_UART2->DLL = Fdiv & 0xFF;
|
|
140
|
+ LPC_UART2->LCR = 0x03; /* DLAB = 0 */
|
|
141
|
+ LPC_UART2->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
293
|
142
|
|
294
|
|
- void HardwareSerial::flush() {
|
295
|
|
- if ( PortNum == 0 )
|
296
|
|
-{
|
297
|
|
- UART0RxQueueWritePos = 0;
|
298
|
|
- UART0RxQueueReadPos = 0;
|
|
143
|
+ NVIC_EnableIRQ(UART2_IRQn);
|
299
|
144
|
|
300
|
|
-}
|
301
|
|
-if ( PortNum == 1 )
|
302
|
|
-{
|
303
|
|
- UART1RxQueueWritePos = 0;
|
304
|
|
- UART1RxQueueReadPos = 0;
|
305
|
|
-}
|
306
|
|
-if ( PortNum == 2 )
|
307
|
|
-{
|
308
|
|
- UART2RxQueueWritePos = 0;
|
309
|
|
- UART2RxQueueReadPos = 0;
|
310
|
|
-}
|
311
|
|
-if ( PortNum == 3 )
|
312
|
|
-{
|
313
|
|
- UART3RxQueueWritePos = 0;
|
314
|
|
- UART3RxQueueReadPos = 0;
|
315
|
|
-}
|
316
|
|
-return;
|
|
145
|
+ LPC_UART2->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
|
317
|
146
|
}
|
318
|
|
-
|
319
|
|
- void HardwareSerial::printf(const char *format, ...) {
|
320
|
|
- static char buffer[256];
|
321
|
|
- va_list vArgs;
|
322
|
|
- va_start(vArgs, format);
|
323
|
|
- int length = vsnprintf((char *) buffer, 256, (char const *) format, vArgs);
|
324
|
|
- va_end(vArgs);
|
325
|
|
- if (length > 0 && length < 256) {
|
326
|
|
- for (int i = 0; i < length;) {
|
327
|
|
- write(buffer[i]);
|
328
|
|
- ++i;
|
329
|
|
- }
|
330
|
|
- }
|
|
147
|
+ else if (PortNum == 3) {
|
|
148
|
+ LPC_PINCON->PINSEL0 &= ~0x0000000F;
|
|
149
|
+ LPC_PINCON->PINSEL0 |= 0x0000000A; /* RxD3 is P0.1 and TxD3 is P0.0 */
|
|
150
|
+ LPC_SC->PCONP |= 1 << 4 | 1 << 25; //Enable PCUART1
|
|
151
|
+ /* By default, the PCLKSELx value is zero, thus, the PCLK for
|
|
152
|
+ all the peripherals is 1/4 of the SystemFrequency. */
|
|
153
|
+ /* Bit 6~7 is for UART3 */
|
|
154
|
+ pclkdiv = (LPC_SC->PCLKSEL1 >> 18) & 0x03;
|
|
155
|
+ switch (pclkdiv) {
|
|
156
|
+ case 0x00:
|
|
157
|
+ default:
|
|
158
|
+ pclk = SystemCoreClock / 4;
|
|
159
|
+ break;
|
|
160
|
+ case 0x01:
|
|
161
|
+ pclk = SystemCoreClock;
|
|
162
|
+ break;
|
|
163
|
+ case 0x02:
|
|
164
|
+ pclk = SystemCoreClock / 2;
|
|
165
|
+ break;
|
|
166
|
+ case 0x03:
|
|
167
|
+ pclk = SystemCoreClock / 8;
|
|
168
|
+ break;
|
331
|
169
|
}
|
|
170
|
+ LPC_UART3->LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
|
|
171
|
+ Fdiv = (pclk / 16) / baudrate ; /*baud rate */
|
|
172
|
+ LPC_UART3->DLM = Fdiv >> 8;
|
|
173
|
+ LPC_UART3->DLL = Fdiv & 0xFF;
|
|
174
|
+ LPC_UART3->LCR = 0x03; /* DLAB = 0 */
|
|
175
|
+ LPC_UART3->FCR = 0x07; /* Enable and reset TX and RX FIFO. */
|
332
|
176
|
|
333
|
|
-#ifdef __cplusplus
|
334
|
|
-extern "C" {
|
335
|
|
-#endif
|
|
177
|
+ NVIC_EnableIRQ(UART3_IRQn);
|
336
|
178
|
|
337
|
|
-/*****************************************************************************
|
338
|
|
-** Function name: UART0_IRQHandler
|
339
|
|
-**
|
340
|
|
-** Descriptions: UART0 interrupt handler
|
341
|
|
-**
|
342
|
|
-** parameters: None
|
343
|
|
-** Returned value: None
|
344
|
|
-**
|
345
|
|
-*****************************************************************************/
|
346
|
|
-void UART0_IRQHandler (void)
|
347
|
|
-{
|
348
|
|
- uint8_t IIRValue, LSRValue;
|
349
|
|
- uint8_t Dummy = Dummy;
|
350
|
|
-
|
351
|
|
- IIRValue = LPC_UART0->IIR;
|
|
179
|
+ LPC_UART3->IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART3 interrupt */
|
|
180
|
+ }
|
|
181
|
+}
|
352
|
182
|
|
353
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
354
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
355
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
356
|
|
- {
|
357
|
|
- LSRValue = LPC_UART0->LSR;
|
358
|
|
- /* Receive Line Status */
|
359
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
360
|
|
- {
|
361
|
|
- /* There are errors or break interrupt */
|
362
|
|
- /* Read LSR will clear the interrupt */
|
363
|
|
- UART0Status = LSRValue;
|
364
|
|
- Dummy = LPC_UART0->RBR; /* Dummy read on RX to clear
|
365
|
|
- interrupt, then bail out */
|
366
|
|
- return;
|
367
|
|
- }
|
368
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
369
|
|
- {
|
370
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
371
|
|
- /* Note: read RBR will clear the interrupt */
|
372
|
|
- if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
|
373
|
|
- {
|
374
|
|
- UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
|
375
|
|
- UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
376
|
|
- }
|
377
|
|
- else
|
378
|
|
- dummy = LPC_UART0->RBR;;
|
379
|
|
- }
|
|
183
|
+int HardwareSerial::read() {
|
|
184
|
+ uint8_t rx;
|
|
185
|
+ if (PortNum == 0) {
|
|
186
|
+ if (UART0RxQueueReadPos == UART0RxQueueWritePos) return -1;
|
|
187
|
+ // Read from "head"
|
|
188
|
+ rx = UART0Buffer[UART0RxQueueReadPos]; // grab next byte
|
|
189
|
+ UART0RxQueueReadPos = (UART0RxQueueReadPos + 1) % UARTRXQUEUESIZE;
|
|
190
|
+ return rx;
|
380
|
191
|
}
|
381
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
382
|
|
- {
|
383
|
|
- /* Receive Data Available */
|
384
|
|
- if ((UART0RxQueueWritePos+1) % UARTRXQUEUESIZE != UART0RxQueueReadPos)
|
385
|
|
- {
|
386
|
|
- UART0Buffer[UART0RxQueueWritePos] = LPC_UART0->RBR;
|
387
|
|
- UART0RxQueueWritePos = (UART0RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
388
|
|
- }
|
389
|
|
- else
|
390
|
|
- dummy = LPC_UART1->RBR;;
|
|
192
|
+ if (PortNum == 1) {
|
|
193
|
+ if (UART1RxQueueReadPos == UART1RxQueueWritePos) return -1;
|
|
194
|
+ rx = UART1Buffer[UART1RxQueueReadPos];
|
|
195
|
+ UART1RxQueueReadPos = (UART1RxQueueReadPos + 1) % UARTRXQUEUESIZE;
|
|
196
|
+ return rx;
|
391
|
197
|
}
|
392
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
393
|
|
- {
|
394
|
|
- /* Character Time-out indicator */
|
395
|
|
- UART0Status |= 0x100; /* Bit 9 as the CTI error */
|
|
198
|
+ if (PortNum == 2) {
|
|
199
|
+ if (UART2RxQueueReadPos == UART2RxQueueWritePos) return -1;
|
|
200
|
+ rx = UART2Buffer[UART2RxQueueReadPos];
|
|
201
|
+ UART2RxQueueReadPos = (UART2RxQueueReadPos + 1) % UARTRXQUEUESIZE;
|
|
202
|
+ return rx;
|
396
|
203
|
}
|
397
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
398
|
|
- {
|
399
|
|
- /* THRE interrupt */
|
400
|
|
- LSRValue = LPC_UART0->LSR; /* Check status in the LSR to see if
|
401
|
|
- valid data in U0THR or not */
|
402
|
|
- if ( LSRValue & LSR_THRE )
|
403
|
|
- {
|
404
|
|
- UART0TxEmpty = 1;
|
405
|
|
- }
|
406
|
|
- else
|
407
|
|
- {
|
408
|
|
- UART0TxEmpty = 0;
|
409
|
|
- }
|
|
204
|
+ if (PortNum == 3) {
|
|
205
|
+ if (UART3RxQueueReadPos == UART3RxQueueWritePos) return -1;
|
|
206
|
+ rx = UART3Buffer[UART3RxQueueReadPos];
|
|
207
|
+ UART3RxQueueReadPos = (UART3RxQueueReadPos + 1) % UARTRXQUEUESIZE;
|
|
208
|
+ return rx;
|
410
|
209
|
}
|
|
210
|
+ return 0;
|
411
|
211
|
}
|
412
|
212
|
|
413
|
|
-/*****************************************************************************
|
414
|
|
-** Function name: UART1_IRQHandler
|
415
|
|
-**
|
416
|
|
-** Descriptions: UART1 interrupt handler
|
417
|
|
-**
|
418
|
|
-** parameters: None
|
419
|
|
-** Returned value: None
|
420
|
|
-**
|
421
|
|
-*****************************************************************************/
|
422
|
|
-void UART1_IRQHandler (void)
|
423
|
|
-{
|
424
|
|
- uint8_t IIRValue, LSRValue;
|
425
|
|
- uint8_t Dummy = Dummy;
|
426
|
|
-
|
427
|
|
- IIRValue = LPC_UART1->IIR;
|
428
|
|
-
|
429
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
430
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
431
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
432
|
|
- {
|
433
|
|
- LSRValue = LPC_UART1->LSR;
|
434
|
|
- /* Receive Line Status */
|
435
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
436
|
|
- {
|
437
|
|
- /* There are errors or break interrupt */
|
438
|
|
- /* Read LSR will clear the interrupt */
|
439
|
|
- UART1Status = LSRValue;
|
440
|
|
- Dummy = LPC_UART1->RBR; /* Dummy read on RX to clear
|
441
|
|
- interrupt, then bail out */
|
442
|
|
- return;
|
443
|
|
- }
|
444
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
445
|
|
- {
|
446
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
447
|
|
- /* Note: read RBR will clear the interrupt */
|
448
|
|
- if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
|
449
|
|
- {
|
450
|
|
- UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
|
451
|
|
- UART1RxQueueWritePos =(UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
452
|
|
- }
|
453
|
|
- else
|
454
|
|
- dummy = LPC_UART1->RBR;;
|
455
|
|
- }
|
|
213
|
+size_t HardwareSerial::write(uint8_t send) {
|
|
214
|
+ if (PortNum == 0) {
|
|
215
|
+ /* THRE status, contain valid data */
|
|
216
|
+ while (!(UART0TxEmpty & 0x01));
|
|
217
|
+ LPC_UART0->THR = send;
|
|
218
|
+ UART0TxEmpty = 0; /* not empty in the THR until it shifts out */
|
456
|
219
|
}
|
457
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
458
|
|
- {
|
459
|
|
- /* Receive Data Available */
|
460
|
|
- if ((UART1RxQueueWritePos+1) % UARTRXQUEUESIZE != UART1RxQueueReadPos)
|
461
|
|
- {
|
462
|
|
- UART1Buffer[UART1RxQueueWritePos] = LPC_UART1->RBR;
|
463
|
|
- UART1RxQueueWritePos = (UART1RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
464
|
|
- }
|
465
|
|
- else
|
466
|
|
- dummy = LPC_UART1->RBR;;
|
|
220
|
+ else if (PortNum == 1) {
|
|
221
|
+ while (!(UART1TxEmpty & 0x01));
|
|
222
|
+ LPC_UART1->THR = send;
|
|
223
|
+ UART1TxEmpty = 0;
|
467
|
224
|
}
|
468
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
469
|
|
- {
|
470
|
|
- /* Character Time-out indicator */
|
471
|
|
- UART1Status |= 0x100; /* Bit 9 as the CTI error */
|
|
225
|
+ else if (PortNum == 2) {
|
|
226
|
+ while (!(UART2TxEmpty & 0x01));
|
|
227
|
+ LPC_UART2->THR = send;
|
|
228
|
+ UART2TxEmpty = 0;
|
472
|
229
|
}
|
473
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
474
|
|
- {
|
475
|
|
- /* THRE interrupt */
|
476
|
|
- LSRValue = LPC_UART1->LSR; /* Check status in the LSR to see if
|
477
|
|
- valid data in U0THR or not */
|
478
|
|
- if ( LSRValue & LSR_THRE )
|
479
|
|
- {
|
480
|
|
- UART1TxEmpty = 1;
|
481
|
|
- }
|
482
|
|
- else
|
483
|
|
- {
|
484
|
|
- UART1TxEmpty = 0;
|
485
|
|
- }
|
|
230
|
+ else if (PortNum == 3) {
|
|
231
|
+ while (!(UART3TxEmpty & 0x01));
|
|
232
|
+ LPC_UART3->THR = send;
|
|
233
|
+ UART3TxEmpty = 0;
|
486
|
234
|
}
|
|
235
|
+ return 0;
|
|
236
|
+}
|
487
|
237
|
|
|
238
|
+int HardwareSerial::available() {
|
|
239
|
+ if (PortNum == 0)
|
|
240
|
+ return (UART0RxQueueWritePos + UARTRXQUEUESIZE - UART0RxQueueReadPos) % UARTRXQUEUESIZE;
|
|
241
|
+ if (PortNum == 1)
|
|
242
|
+ return (UART1RxQueueWritePos + UARTRXQUEUESIZE - UART1RxQueueReadPos) % UARTRXQUEUESIZE;
|
|
243
|
+ if (PortNum == 2)
|
|
244
|
+ return (UART2RxQueueWritePos + UARTRXQUEUESIZE - UART2RxQueueReadPos) % UARTRXQUEUESIZE;
|
|
245
|
+ if (PortNum == 3)
|
|
246
|
+ return (UART3RxQueueWritePos + UARTRXQUEUESIZE - UART3RxQueueReadPos) % UARTRXQUEUESIZE;
|
|
247
|
+ return 0;
|
488
|
248
|
}
|
489
|
|
-/*****************************************************************************
|
490
|
|
-** Function name: UART2_IRQHandler
|
491
|
|
-**
|
492
|
|
-** Descriptions: UART2 interrupt handler
|
493
|
|
-**
|
494
|
|
-** parameters: None
|
495
|
|
-** Returned value: None
|
496
|
|
-**
|
497
|
|
-*****************************************************************************/
|
498
|
|
-void UART2_IRQHandler (void)
|
499
|
|
-{
|
500
|
|
- uint8_t IIRValue, LSRValue;
|
501
|
|
- uint8_t Dummy = Dummy;
|
502
|
249
|
|
503
|
|
- IIRValue = LPC_UART2->IIR;
|
|
250
|
+void HardwareSerial::flush() {
|
|
251
|
+ if (PortNum == 0)
|
|
252
|
+ UART0RxQueueWritePos = UART0RxQueueReadPos = 0;
|
|
253
|
+ if (PortNum == 1)
|
|
254
|
+ UART1RxQueueWritePos = UART1RxQueueReadPos = 0;
|
|
255
|
+ if (PortNum == 2)
|
|
256
|
+ UART2RxQueueWritePos = UART2RxQueueReadPos = 0;
|
|
257
|
+ if (PortNum == 3)
|
|
258
|
+ UART3RxQueueWritePos = UART3RxQueueReadPos = 0;
|
|
259
|
+}
|
504
|
260
|
|
505
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
506
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
507
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
508
|
|
- {
|
509
|
|
- LSRValue = LPC_UART2->LSR;
|
510
|
|
- /* Receive Line Status */
|
511
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
512
|
|
- {
|
513
|
|
- /* There are errors or break interrupt */
|
514
|
|
- /* Read LSR will clear the interrupt */
|
515
|
|
- UART2Status = LSRValue;
|
516
|
|
- Dummy = LPC_UART2->RBR; /* Dummy read on RX to clear
|
517
|
|
- interrupt, then bail out */
|
518
|
|
- return;
|
519
|
|
- }
|
520
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
521
|
|
- {
|
522
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
523
|
|
- /* Note: read RBR will clear the interrupt */
|
524
|
|
- if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
|
525
|
|
- {
|
526
|
|
- UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
|
527
|
|
- UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
528
|
|
- }
|
529
|
|
- }
|
530
|
|
- }
|
531
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
532
|
|
- {
|
533
|
|
- /* Receive Data Available */
|
534
|
|
- if ((UART2RxQueueWritePos+1) % UARTRXQUEUESIZE != UART2RxQueueReadPos)
|
535
|
|
- {
|
536
|
|
- UART2Buffer[UART2RxQueueWritePos] = LPC_UART2->RBR;
|
537
|
|
- UART2RxQueueWritePos = (UART2RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
538
|
|
- }
|
539
|
|
- else
|
540
|
|
- dummy = LPC_UART2->RBR;;
|
541
|
|
- }
|
542
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
543
|
|
- {
|
544
|
|
- /* Character Time-out indicator */
|
545
|
|
- UART2Status |= 0x100; /* Bit 9 as the CTI error */
|
546
|
|
- }
|
547
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
548
|
|
- {
|
549
|
|
- /* THRE interrupt */
|
550
|
|
- LSRValue = LPC_UART2->LSR; /* Check status in the LSR to see if
|
551
|
|
- valid data in U0THR or not */
|
552
|
|
- if ( LSRValue & LSR_THRE )
|
553
|
|
- {
|
554
|
|
- UART2TxEmpty = 1;
|
555
|
|
- }
|
556
|
|
- else
|
557
|
|
- {
|
558
|
|
- UART2TxEmpty = 0;
|
559
|
|
- }
|
560
|
|
- }
|
|
261
|
+void HardwareSerial::printf(const char *format, ...) {
|
|
262
|
+ static char buffer[256];
|
|
263
|
+ va_list vArgs;
|
|
264
|
+ va_start(vArgs, format);
|
|
265
|
+ int length = vsnprintf((char *) buffer, 256, (char const *) format, vArgs);
|
|
266
|
+ va_end(vArgs);
|
|
267
|
+ if (length > 0 && length < 256)
|
|
268
|
+ for (int i = 0; i < length; ++i)
|
|
269
|
+ write(buffer[i]);
|
561
|
270
|
}
|
|
271
|
+
|
562
|
272
|
/*****************************************************************************
|
563
|
|
-** Function name: UART3_IRQHandler
|
|
273
|
+** Function name: UARTn_IRQHandler
|
564
|
274
|
**
|
565
|
|
-** Descriptions: UART0 interrupt handler
|
|
275
|
+** Descriptions: UARTn interrupt handler
|
566
|
276
|
**
|
567
|
|
-** parameters: None
|
568
|
|
-** Returned value: None
|
|
277
|
+** parameters: None
|
|
278
|
+** Returned value: None
|
569
|
279
|
**
|
570
|
280
|
*****************************************************************************/
|
571
|
|
-void UART3_IRQHandler (void)
|
572
|
|
-{
|
573
|
|
- uint8_t IIRValue, LSRValue;
|
574
|
|
- uint8_t Dummy = Dummy;
|
|
281
|
+#define DEFINE_UART_HANDLER(NUM) \
|
|
282
|
+ void UART3_IRQHandler(void) { \
|
|
283
|
+ uint8_t IIRValue, LSRValue; \
|
|
284
|
+ uint8_t Dummy = Dummy; \
|
|
285
|
+ IIRValue = LPC_UART ##NUM## ->IIR; \
|
|
286
|
+ IIRValue >>= 1; \
|
|
287
|
+ IIRValue &= 0x07; \
|
|
288
|
+ switch (IIRValue) { \
|
|
289
|
+ case IIR_RLS: \
|
|
290
|
+ LSRValue = LPC_UART ##NUM## ->LSR; \
|
|
291
|
+ if (LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI)) { \
|
|
292
|
+ UART ##NUM## Status = LSRValue; \
|
|
293
|
+ Dummy = LPC_UART ##NUM## ->RBR; \
|
|
294
|
+ return; \
|
|
295
|
+ } \
|
|
296
|
+ if (LSRValue & LSR_RDR) { \
|
|
297
|
+ if ((UART ##NUM## RxQueueWritePos+1) % UARTRXQUEUESIZE != UART ##NUM## RxQueueReadPos) { \
|
|
298
|
+ UART ##NUM## Buffer[UART ##NUM## RxQueueWritePos] = LPC_UART ##NUM## ->RBR; \
|
|
299
|
+ UART ##NUM## RxQueueWritePos = (UART ##NUM## RxQueueWritePos+1) % UARTRXQUEUESIZE; \
|
|
300
|
+ } \
|
|
301
|
+ } \
|
|
302
|
+ break; \
|
|
303
|
+ case IIR_RDA: \
|
|
304
|
+ if ((UART ##NUM## RxQueueWritePos+1) % UARTRXQUEUESIZE != UART ##NUM## RxQueueReadPos) { \
|
|
305
|
+ UART ##NUM## Buffer[UART ##NUM## RxQueueWritePos] = LPC_UART ##NUM## ->RBR; \
|
|
306
|
+ UART ##NUM## RxQueueWritePos = (UART ##NUM## RxQueueWritePos+1) % UARTRXQUEUESIZE; \
|
|
307
|
+ } \
|
|
308
|
+ else \
|
|
309
|
+ dummy = LPC_UART ##NUM## ->RBR;; \
|
|
310
|
+ break; \
|
|
311
|
+ case IIR_CTI: \
|
|
312
|
+ UART ##NUM## Status |= 0x100; \
|
|
313
|
+ break; \
|
|
314
|
+ case IIR_THRE: \
|
|
315
|
+ LSRValue = LPC_UART ##NUM## ->LSR; \
|
|
316
|
+ UART ##NUM## TxEmpty = (LSRValue & LSR_THRE) ? 1 : 0; \
|
|
317
|
+ break; \
|
|
318
|
+ } \
|
|
319
|
+ } \
|
|
320
|
+ typedef void _uart_ ## NUM
|
575
|
321
|
|
576
|
|
- IIRValue = LPC_UART3->IIR;
|
|
322
|
+#ifdef __cplusplus
|
|
323
|
+ extern "C" {
|
|
324
|
+#endif
|
577
|
325
|
|
578
|
|
- IIRValue >>= 1; /* skip pending bit in IIR */
|
579
|
|
- IIRValue &= 0x07; /* check bit 1~3, interrupt identification */
|
580
|
|
- if ( IIRValue == IIR_RLS ) /* Receive Line Status */
|
581
|
|
- {
|
582
|
|
- LSRValue = LPC_UART3->LSR;
|
583
|
|
- /* Receive Line Status */
|
584
|
|
- if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
|
585
|
|
- {
|
586
|
|
- /* There are errors or break interrupt */
|
587
|
|
- /* Read LSR will clear the interrupt */
|
588
|
|
- UART3Status = LSRValue;
|
589
|
|
- Dummy = LPC_UART3->RBR; /* Dummy read on RX to clear
|
590
|
|
- interrupt, then bail out */
|
591
|
|
- return;
|
592
|
|
- }
|
593
|
|
- if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
|
594
|
|
- {
|
595
|
|
- /* If no error on RLS, normal ready, save into the data buffer. */
|
596
|
|
- /* Note: read RBR will clear the interrupt */
|
597
|
|
- if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
|
598
|
|
- {
|
599
|
|
- UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
|
600
|
|
- UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
601
|
|
- }
|
602
|
|
- }
|
603
|
|
- }
|
604
|
|
- else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
|
605
|
|
- {
|
606
|
|
- /* Receive Data Available */
|
607
|
|
- if ((UART3RxQueueWritePos+1) % UARTRXQUEUESIZE != UART3RxQueueReadPos)
|
608
|
|
- {
|
609
|
|
- UART3Buffer[UART3RxQueueWritePos] = LPC_UART3->RBR;
|
610
|
|
- UART3RxQueueWritePos = (UART3RxQueueWritePos+1) % UARTRXQUEUESIZE;
|
611
|
|
- }
|
612
|
|
- else
|
613
|
|
- dummy = LPC_UART3->RBR;;
|
614
|
|
- }
|
615
|
|
- else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
|
616
|
|
- {
|
617
|
|
- /* Character Time-out indicator */
|
618
|
|
- UART3Status |= 0x100; /* Bit 9 as the CTI error */
|
619
|
|
- }
|
620
|
|
- else if ( IIRValue == IIR_THRE ) /* THRE, transmit holding register empty */
|
621
|
|
- {
|
622
|
|
- /* THRE interrupt */
|
623
|
|
- LSRValue = LPC_UART3->LSR; /* Check status in the LSR to see if
|
624
|
|
- valid data in U0THR or not */
|
625
|
|
- if ( LSRValue & LSR_THRE )
|
626
|
|
- {
|
627
|
|
- UART3TxEmpty = 1;
|
628
|
|
- }
|
629
|
|
- else
|
630
|
|
- {
|
631
|
|
- UART3TxEmpty = 0;
|
632
|
|
- }
|
633
|
|
- }
|
634
|
|
-}
|
|
326
|
+ DEFINE_UART_HANDLER(0);
|
|
327
|
+ DEFINE_UART_HANDLER(1);
|
|
328
|
+ DEFINE_UART_HANDLER(2);
|
|
329
|
+ DEFINE_UART_HANDLER(3);
|
635
|
330
|
|
636
|
331
|
#ifdef __cplusplus
|
637
|
|
-}
|
|
332
|
+ }
|
638
|
333
|
#endif
|
639
|
334
|
|
640
|
335
|
#endif // TARGET_LPC1768
|