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@@ -56,16 +56,15 @@
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ring_buffer_r rx_buffer = { { 0 }, 0, 0 };
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#if TX_BUFFER_SIZE > 0
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ring_buffer_t tx_buffer = { { 0 }, 0, 0 };
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- static bool _written;
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#endif
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+ static bool _written;
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#endif
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#if ENABLED(SERIAL_XON_XOFF)
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- constexpr uint8_t XON_XOFF_CHAR_SENT = 0x80; // XON / XOFF Character was sent
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- constexpr uint8_t XON_XOFF_CHAR_MASK = 0x1F; // XON / XOFF character to send
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+ constexpr uint8_t XON_XOFF_CHAR_SENT = 0x80, // XON / XOFF Character was sent
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+ XON_XOFF_CHAR_MASK = 0x1F; // XON / XOFF character to send
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// XON / XOFF character definitions
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- constexpr uint8_t XON_CHAR = 17;
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- constexpr uint8_t XOFF_CHAR = 19;
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+ constexpr uint8_t XON_CHAR = 17, XOFF_CHAR = 19;
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uint8_t xon_xoff_state = XON_XOFF_CHAR_SENT | XON_CHAR;
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#endif
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@@ -91,125 +90,196 @@
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static EmergencyParser::State emergency_state; // = EP_RESET
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#endif
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- const ring_buffer_pos_t h = rx_buffer.head,
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- i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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+ // Get the tail - Nothing can alter its value while we are at this ISR
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+ const ring_buffer_pos_t t = rx_buffer.tail;
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- // Read the character
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- const uint8_t c = M_UDRx;
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+ // Get the head pointer
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+ ring_buffer_pos_t h = rx_buffer.head;
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+
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+ // Get the next element
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+ ring_buffer_pos_t i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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+
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+ // Read the character from the USART
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+ uint8_t c = M_UDRx;
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+
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+ #if ENABLED(EMERGENCY_PARSER)
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+ emergency_parser.update(emergency_state, c);
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+ #endif
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// If the character is to be stored at the index just before the tail
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- // (such that the head would advance to the current tail), the buffer is
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- // critical, so don't write the character or advance the head.
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- if (i != rx_buffer.tail) {
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+ // (such that the head would advance to the current tail), the RX FIFO is
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+ // full, so don't write the character or advance the head.
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+ if (i != t) {
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rx_buffer.buffer[h] = c;
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- rx_buffer.head = i;
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- }
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- else {
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- #if ENABLED(SERIAL_STATS_DROPPED_RX)
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- if (!++rx_dropped_bytes) ++rx_dropped_bytes;
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- #endif
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+ h = i;
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}
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+ #if ENABLED(SERIAL_STATS_DROPPED_RX)
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+ else if (!++rx_dropped_bytes) --rx_dropped_bytes;
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+ #endif
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#if ENABLED(SERIAL_STATS_MAX_RX_QUEUED)
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- // calculate count of bytes stored into the RX buffer
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- ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(rx_buffer.head - rx_buffer.tail) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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+ // Calculate count of bytes stored into the RX buffer
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+ const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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+
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// Keep track of the maximum count of enqueued bytes
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NOLESS(rx_max_enqueued, rx_count);
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#endif
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#if ENABLED(SERIAL_XON_XOFF)
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-
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- // for high speed transfers, we can use XON/XOFF protocol to do
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- // software handshake and avoid overruns.
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+ // If the last char that was sent was an XON
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if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XON_CHAR) {
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- // calculate count of bytes stored into the RX buffer
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- ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(rx_buffer.head - rx_buffer.tail) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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+ // Bytes stored into the RX buffer
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+ const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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- // if we are above 12.5% of RX buffer capacity, send XOFF before
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- // we run out of RX buffer space .. We need 325 bytes @ 250kbits/s to
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- // let the host react and stop sending bytes. This translates to 13mS
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- // propagation time.
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+ // If over 12.5% of RX buffer capacity, send XOFF before running out of
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+ // RX buffer space .. 325 bytes @ 250kbits/s needed to let the host react
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+ // and stop sending bytes. This translates to 13mS propagation time.
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if (rx_count >= (RX_BUFFER_SIZE) / 8) {
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- // If TX interrupts are disabled and data register is empty,
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- // just write the byte to the data register and be done. This
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- // shortcut helps significantly improve the effective datarate
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- // at high (>500kbit/s) bitrates, where interrupt overhead
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- // becomes a slowdown.
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- if (!TEST(M_UCSRxB, M_UDRIEx) && TEST(M_UCSRxA, M_UDREx)) {
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-
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- // Send an XOFF character
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- M_UDRx = XOFF_CHAR;
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-
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- // clear the TXC bit -- "can be cleared by writing a one to its bit
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- // location". This makes sure flush() won't return until the bytes
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- // actually got written
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- SBI(M_UCSRxA, M_TXCx);
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-
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- // And remember it was sent
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- xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
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+ // At this point, definitely no TX interrupt was executing, since the TX isr can't be preempted.
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+ // Don't enable the TX interrupt here as a means to trigger the XOFF char, because if it happens
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+ // to be in the middle of trying to disable the RX interrupt in the main program, eventually the
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+ // enabling of the TX interrupt could be undone. The ONLY reliable thing this can do to ensure
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+ // the sending of the XOFF char is to send it HERE AND NOW.
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+
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+ // About to send the XOFF char
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+ xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
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+
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+ // Wait until the TX register becomes empty and send it - Here there could be a problem
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+ // - While waiting for the TX register to empty, the RX register could receive a new
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+ // character. This must also handle that situation!
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+ while (!TEST(M_UCSRxA, M_UDREx)) {
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+
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+ if (TEST(M_UCSRxA,M_RXCx)) {
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+ // A char arrived while waiting for the TX buffer to be empty - Receive and process it!
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+
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+ i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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+
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+ // Read the character from the USART
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+ c = M_UDRx;
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+
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+ #if ENABLED(EMERGENCY_PARSER)
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+ emergency_parser.update(emergency_state, c);
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+ #endif
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+
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+ // If the character is to be stored at the index just before the tail
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+ // (such that the head would advance to the current tail), the FIFO is
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+ // full, so don't write the character or advance the head.
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+ if (i != t) {
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+ rx_buffer.buffer[h] = c;
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+ h = i;
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+ }
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+ #if ENABLED(SERIAL_STATS_DROPPED_RX)
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+ else if (!++rx_dropped_bytes) --rx_dropped_bytes;
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+ #endif
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+ }
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+ sw_barrier();
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}
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- else {
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- // TX interrupts disabled, but buffer still not empty ... or
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- // TX interrupts enabled. Reenable TX ints and schedule XOFF
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- // character to be sent
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- #if TX_BUFFER_SIZE > 0
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- SBI(M_UCSRxB, M_UDRIEx);
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- xon_xoff_state = XOFF_CHAR;
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- #else
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- // We are not using TX interrupts, we will have to send this manually
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- while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
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- M_UDRx = XOFF_CHAR;
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-
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- // clear the TXC bit -- "can be cleared by writing a one to its bit
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- // location". This makes sure flush() won't return until the bytes
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- // actually got written
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- SBI(M_UCSRxA, M_TXCx);
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-
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- // And remember we already sent it
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- xon_xoff_state = XOFF_CHAR | XON_XOFF_CHAR_SENT;
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- #endif
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179
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+
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180
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+ M_UDRx = XOFF_CHAR;
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+
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182
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+ // Clear the TXC bit -- "can be cleared by writing a one to its bit
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+ // location". This makes sure flush() won't return until the bytes
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+ // actually got written
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+ SBI(M_UCSRxA, M_TXCx);
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186
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+
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187
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+ // At this point there could be a race condition between the write() function
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188
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+ // and this sending of the XOFF char. This interrupt could happen between the
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189
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+ // wait to be empty TX buffer loop and the actual write of the character. Since
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190
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+ // the TX buffer is full because it's sending the XOFF char, the only way to be
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191
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+ // sure the write() function will succeed is to wait for the XOFF char to be
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192
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+ // completely sent. Since an extra character could be received during the wait
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193
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+ // it must also be handled!
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194
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+ while (!TEST(M_UCSRxA, M_UDREx)) {
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195
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+
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196
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+ if (TEST(M_UCSRxA,M_RXCx)) {
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197
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+ // A char arrived while waiting for the TX buffer to be empty - Receive and process it!
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198
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+
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199
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+ i = (ring_buffer_pos_t)(h + 1) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
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200
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+
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201
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+ // Read the character from the USART
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202
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+ c = M_UDRx;
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203
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+
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204
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+ #if ENABLED(EMERGENCY_PARSER)
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205
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+ emergency_parser.update(emergency_state, c);
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206
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+ #endif
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207
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+
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208
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+ // If the character is to be stored at the index just before the tail
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209
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+ // (such that the head would advance to the current tail), the FIFO is
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210
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+ // full, so don't write the character or advance the head.
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211
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+ if (i != t) {
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212
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+ rx_buffer.buffer[h] = c;
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213
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+ h = i;
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214
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+ }
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215
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+ #if ENABLED(SERIAL_STATS_DROPPED_RX)
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216
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+ else if (!++rx_dropped_bytes) --rx_dropped_bytes;
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217
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+ #endif
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218
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+ }
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219
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+ sw_barrier();
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173
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220
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}
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221
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+
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222
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+ // At this point everything is ready. The write() function won't
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223
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+ // have any issues writing to the UART TX register if it needs to!
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174
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224
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}
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175
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225
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}
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176
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226
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#endif // SERIAL_XON_XOFF
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177
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227
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|
178
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- #if ENABLED(EMERGENCY_PARSER)
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179
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- emergency_parser.update(emergency_state, c);
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180
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- #endif
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228
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+ // Store the new head value
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229
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+ rx_buffer.head = h;
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181
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230
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}
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182
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231
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183
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232
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#if TX_BUFFER_SIZE > 0
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184
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233
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185
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234
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// (called with TX irqs disabled)
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186
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235
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FORCE_INLINE void _tx_udr_empty_irq(void) {
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187
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- // If interrupts are enabled, there must be more data in the output
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188
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- // buffer.
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236
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+
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237
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+ // Read positions
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238
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+ uint8_t t = tx_buffer.tail;
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239
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+ const uint8_t h = tx_buffer.head;
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189
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240
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|
190
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241
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#if ENABLED(SERIAL_XON_XOFF)
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191
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- // Do a priority insertion of an XON/XOFF char, if needed.
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192
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- const uint8_t state = xon_xoff_state;
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193
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- if (!(state & XON_XOFF_CHAR_SENT)) {
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194
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- M_UDRx = state & XON_XOFF_CHAR_MASK;
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195
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- xon_xoff_state = state | XON_XOFF_CHAR_SENT;
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242
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+ // If an XON char is pending to be sent, do it now
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243
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+ if (xon_xoff_state == XON_CHAR) {
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244
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+
|
|
245
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+ // Send the character
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246
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+ M_UDRx = XON_CHAR;
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|
247
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+
|
|
248
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+ // clear the TXC bit -- "can be cleared by writing a one to its bit
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|
249
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+ // location". This makes sure flush() won't return until the bytes
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|
250
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+ // actually got written
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|
251
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+ SBI(M_UCSRxA, M_TXCx);
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|
252
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+
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|
253
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+ // Remember we sent it.
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|
254
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+ xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
|
255
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+
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|
256
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+ // If nothing else to transmit, just disable TX interrupts.
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257
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+ if (h == t) CBI(M_UCSRxB, M_UDRIEx); // (Non-atomic, could be reenabled by the main program, but eventually this will succeed)
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258
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+
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259
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+ return;
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196
|
260
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}
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197
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- else
|
198
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261
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#endif
|
199
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- { // Send the next byte
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200
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- const uint8_t t = tx_buffer.tail, c = tx_buffer.buffer[t];
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201
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- tx_buffer.tail = (t + 1) & (TX_BUFFER_SIZE - 1);
|
202
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- M_UDRx = c;
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262
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+
|
|
263
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+ // If nothing to transmit, just disable TX interrupts. This could
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|
264
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+ // happen as the result of the non atomicity of the disabling of RX
|
|
265
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+ // interrupts that could end reenabling TX interrupts as a side effect.
|
|
266
|
+ if (h == t) {
|
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267
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+ CBI(M_UCSRxB, M_UDRIEx); // (Non-atomic, could be reenabled by the main program, but eventually this will succeed)
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268
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+ return;
|
203
|
269
|
}
|
204
|
270
|
|
205
|
|
- // clear the TXC bit -- "can be cleared by writing a one to its bit
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206
|
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- // location". This makes sure flush() won't return until the bytes
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207
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|
- // actually got written
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271
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+ // There is something to TX, Send the next byte
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272
|
+ const uint8_t c = tx_buffer.buffer[t];
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|
273
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+ t = (t + 1) & (TX_BUFFER_SIZE - 1);
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|
274
|
+ M_UDRx = c;
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|
275
|
+ tx_buffer.tail = t;
|
|
276
|
+
|
|
277
|
+ // Clear the TXC bit (by writing a one to its bit location).
|
|
278
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+ // Ensures flush() won't return until the bytes are actually written/
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208
|
279
|
SBI(M_UCSRxA, M_TXCx);
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209
|
280
|
|
210
|
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- // Disable interrupts if the buffer is empty
|
211
|
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- if (tx_buffer.head == tx_buffer.tail)
|
212
|
|
- CBI(M_UCSRxB, M_UDRIEx);
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|
281
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+ // Disable interrupts if there is nothing to transmit following this byte
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|
282
|
+ if (h == t) CBI(M_UCSRxB, M_UDRIEx); // (Non-atomic, could be reenabled by the main program, but eventually this will succeed)
|
213
|
283
|
}
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214
|
284
|
|
215
|
285
|
#ifdef M_USARTx_UDRE_vect
|
|
@@ -253,8 +323,8 @@
|
253
|
323
|
SBI(M_UCSRxB, M_RXCIEx);
|
254
|
324
|
#if TX_BUFFER_SIZE > 0
|
255
|
325
|
CBI(M_UCSRxB, M_UDRIEx);
|
256
|
|
- _written = false;
|
257
|
326
|
#endif
|
|
327
|
+ _written = false;
|
258
|
328
|
}
|
259
|
329
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|
260
|
330
|
void MarlinSerial::end() {
|
|
@@ -281,11 +351,11 @@
|
281
|
351
|
}
|
282
|
352
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|
283
|
353
|
int MarlinSerial::read(void) {
|
284
|
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- int v;
|
285
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354
|
|
286
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355
|
#if RX_BUFFER_SIZE > 256
|
287
|
|
- // Disable RX interrupts to ensure atomic reads
|
288
|
|
- const bool isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
|
356
|
+ // Disable RX interrupts to ensure atomic reads - This could reenable TX interrupts,
|
|
357
|
+ // but this situation is explicitly handled at the TX isr, so no problems there
|
|
358
|
+ bool isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
289
|
359
|
CBI(M_UCSRxB, M_RXCIEx);
|
290
|
360
|
#endif
|
291
|
361
|
|
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@@ -298,43 +368,50 @@
|
298
|
368
|
|
299
|
369
|
ring_buffer_pos_t t = rx_buffer.tail;
|
300
|
370
|
|
301
|
|
- if (h == t)
|
302
|
|
- v = -1;
|
303
|
|
- else {
|
304
|
|
- v = rx_buffer.buffer[t];
|
305
|
|
- t = (ring_buffer_pos_t)(t + 1) & (RX_BUFFER_SIZE - 1);
|
306
|
|
-
|
307
|
|
- #if RX_BUFFER_SIZE > 256
|
308
|
|
- // Disable RX interrupts to ensure atomic write to tail, so
|
309
|
|
- // the RX isr can't read partially updated values
|
310
|
|
- const bool isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
311
|
|
- CBI(M_UCSRxB, M_RXCIEx);
|
312
|
|
- #endif
|
|
371
|
+ // If nothing to read, return now
|
|
372
|
+ if (h == t) return -1;
|
313
|
373
|
|
314
|
|
- // Advance tail
|
315
|
|
- rx_buffer.tail = t;
|
|
374
|
+ // Get the next char
|
|
375
|
+ const int v = rx_buffer.buffer[t];
|
|
376
|
+ t = (ring_buffer_pos_t)(t + 1) & (RX_BUFFER_SIZE - 1);
|
316
|
377
|
|
317
|
|
- #if RX_BUFFER_SIZE > 256
|
318
|
|
- // End critical section
|
319
|
|
- if (isr_enabled) SBI(M_UCSRxB, M_RXCIEx);
|
320
|
|
- #endif
|
|
378
|
+ #if RX_BUFFER_SIZE > 256
|
|
379
|
+ // Disable RX interrupts to ensure atomic write to tail, so
|
|
380
|
+ // the RX isr can't read partially updated values - This could
|
|
381
|
+ // reenable TX interrupts, but this situation is explicitly
|
|
382
|
+ // handled at the TX isr, so no problems there
|
|
383
|
+ isr_enabled = TEST(M_UCSRxB, M_RXCIEx);
|
|
384
|
+ CBI(M_UCSRxB, M_RXCIEx);
|
|
385
|
+ #endif
|
321
|
386
|
|
322
|
|
- #if ENABLED(SERIAL_XON_XOFF)
|
323
|
|
- if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
|
387
|
+ // Advance tail
|
|
388
|
+ rx_buffer.tail = t;
|
324
|
389
|
|
325
|
|
- // Get count of bytes in the RX buffer
|
326
|
|
- ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
|
390
|
+ #if RX_BUFFER_SIZE > 256
|
|
391
|
+ // End critical section
|
|
392
|
+ if (isr_enabled) SBI(M_UCSRxB, M_RXCIEx);
|
|
393
|
+ #endif
|
327
|
394
|
|
328
|
|
- // When below 10% of RX buffer capacity, send XON before
|
329
|
|
- // running out of RX buffer bytes
|
330
|
|
- if (rx_count < (RX_BUFFER_SIZE) / 10) {
|
|
395
|
+ #if ENABLED(SERIAL_XON_XOFF)
|
|
396
|
+ // If the XOFF char was sent, or about to be sent...
|
|
397
|
+ if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
|
398
|
+ // Get count of bytes in the RX buffer
|
|
399
|
+ const ring_buffer_pos_t rx_count = (ring_buffer_pos_t)(h - t) & (ring_buffer_pos_t)(RX_BUFFER_SIZE - 1);
|
|
400
|
+ if (rx_count < (RX_BUFFER_SIZE) / 10) {
|
|
401
|
+ #if TX_BUFFER_SIZE > 0
|
|
402
|
+ // Signal we want an XON character to be sent.
|
|
403
|
+ xon_xoff_state = XON_CHAR;
|
|
404
|
+ // Enable TX isr. Non atomic, but it will eventually enable them
|
|
405
|
+ SBI(M_UCSRxB, M_UDRIEx);
|
|
406
|
+ #else
|
|
407
|
+ // If not using TX interrupts, we must send the XON char now
|
331
|
408
|
xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
332
|
|
- write(XON_CHAR);
|
333
|
|
- return v;
|
334
|
|
- }
|
|
409
|
+ while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
|
|
410
|
+ M_UDRx = XON_CHAR;
|
|
411
|
+ #endif
|
335
|
412
|
}
|
336
|
|
- #endif
|
337
|
|
- }
|
|
413
|
+ }
|
|
414
|
+ #endif
|
338
|
415
|
|
339
|
416
|
return v;
|
340
|
417
|
}
|
|
@@ -367,9 +444,19 @@
|
367
|
444
|
#endif
|
368
|
445
|
|
369
|
446
|
#if ENABLED(SERIAL_XON_XOFF)
|
|
447
|
+ // If the XOFF char was sent, or about to be sent...
|
370
|
448
|
if ((xon_xoff_state & XON_XOFF_CHAR_MASK) == XOFF_CHAR) {
|
371
|
|
- xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
372
|
|
- write(XON_CHAR);
|
|
449
|
+ #if TX_BUFFER_SIZE > 0
|
|
450
|
+ // Signal we want an XON character to be sent.
|
|
451
|
+ xon_xoff_state = XON_CHAR;
|
|
452
|
+ // Enable TX isr. Non atomic, but it will eventually enable it.
|
|
453
|
+ SBI(M_UCSRxB, M_UDRIEx);
|
|
454
|
+ #else
|
|
455
|
+ // If not using TX interrupts, we must send the XON char now
|
|
456
|
+ xon_xoff_state = XON_CHAR | XON_XOFF_CHAR_SENT;
|
|
457
|
+ while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
|
|
458
|
+ M_UDRx = XON_CHAR;
|
|
459
|
+ #endif
|
373
|
460
|
}
|
374
|
461
|
#endif
|
375
|
462
|
}
|
|
@@ -383,6 +470,8 @@
|
383
|
470
|
// be done. This shortcut helps significantly improve the
|
384
|
471
|
// effective datarate at high (>500kbit/s) bitrates, where
|
385
|
472
|
// interrupt overhead becomes a slowdown.
|
|
473
|
+ // Yes, there is a race condition between the sending of the
|
|
474
|
+ // XOFF char at the RX isr, but it is properly handled there
|
386
|
475
|
if (!TEST(M_UCSRxB, M_UDRIEx) && TEST(M_UCSRxA, M_UDREx)) {
|
387
|
476
|
M_UDRx = c;
|
388
|
477
|
|
|
@@ -395,61 +484,79 @@
|
395
|
484
|
|
396
|
485
|
const uint8_t i = (tx_buffer.head + 1) & (TX_BUFFER_SIZE - 1);
|
397
|
486
|
|
398
|
|
- // If the output buffer is full, there's nothing for it other than to
|
399
|
|
- // wait for the interrupt handler to empty it a bit
|
400
|
|
- while (i == tx_buffer.tail) {
|
401
|
|
- if (!ISRS_ENABLED()) {
|
402
|
|
- // Interrupts are disabled, so we'll have to poll the data
|
403
|
|
- // register empty flag ourselves. If it is set, pretend an
|
404
|
|
- // interrupt has happened and call the handler to free up
|
405
|
|
- // space for us.
|
406
|
|
- if (TEST(M_UCSRxA, M_UDREx))
|
407
|
|
- _tx_udr_empty_irq();
|
408
|
|
- }
|
409
|
|
- // (else , the interrupt handler will free up space for us)
|
|
487
|
+ // If global interrupts are disabled (as the result of being called from an ISR)...
|
|
488
|
+ if (!ISRS_ENABLED()) {
|
|
489
|
+
|
|
490
|
+ // Make room by polling if it is possible to transmit, and do so!
|
|
491
|
+ while (i == tx_buffer.tail) {
|
410
|
492
|
|
411
|
|
- // Make sure compiler rereads tx_buffer.tail
|
412
|
|
- sw_barrier();
|
|
493
|
+ // If we can transmit another byte, do it.
|
|
494
|
+ if (TEST(M_UCSRxA, M_UDREx)) _tx_udr_empty_irq();
|
|
495
|
+
|
|
496
|
+ // Make sure compiler rereads tx_buffer.tail
|
|
497
|
+ sw_barrier();
|
|
498
|
+ }
|
|
499
|
+ }
|
|
500
|
+ else {
|
|
501
|
+ // Interrupts are enabled, just wait until there is space
|
|
502
|
+ while (i == tx_buffer.tail) { sw_barrier(); }
|
413
|
503
|
}
|
414
|
504
|
|
415
|
505
|
// Store new char. head is always safe to move
|
416
|
506
|
tx_buffer.buffer[tx_buffer.head] = c;
|
417
|
507
|
tx_buffer.head = i;
|
418
|
508
|
|
419
|
|
- // Enable TX isr
|
|
509
|
+ // Enable TX isr - Non atomic, but it will eventually enable TX isr
|
420
|
510
|
SBI(M_UCSRxB, M_UDRIEx);
|
421
|
|
- return;
|
422
|
511
|
}
|
423
|
512
|
|
424
|
513
|
void MarlinSerial::flushTX(void) {
|
425
|
|
- // TX
|
426
|
|
- // If we have never written a byte, no need to flush. This special
|
427
|
|
- // case is needed since there is no way to force the TXC (transmit
|
428
|
|
- // complete) bit to 1 during initialization
|
429
|
|
- if (!_written)
|
430
|
|
- return;
|
|
514
|
+ // No bytes written, no need to flush. This special case is needed since there's
|
|
515
|
+ // no way to force the TXC (transmit complete) bit to 1 during initialization.
|
|
516
|
+ if (!_written) return;
|
|
517
|
+
|
|
518
|
+ // If global interrupts are disabled (as the result of being called from an ISR)...
|
|
519
|
+ if (!ISRS_ENABLED()) {
|
431
|
520
|
|
432
|
|
- while (TEST(M_UCSRxB, M_UDRIEx) || !TEST(M_UCSRxA, M_TXCx)) {
|
433
|
|
- if (!ISRS_ENABLED()) {
|
434
|
|
- // Interrupts are globally disabled, but the DR empty
|
435
|
|
- // interrupt should be enabled, so poll the DR empty flag to
|
436
|
|
- // prevent deadlock
|
|
521
|
+ // Wait until everything was transmitted - We must do polling, as interrupts are disabled
|
|
522
|
+ while (tx_buffer.head != tx_buffer.tail || !TEST(M_UCSRxA, M_TXCx)) {
|
|
523
|
+
|
|
524
|
+ // If there is more space, send an extra character
|
437
|
525
|
if (TEST(M_UCSRxA, M_UDREx))
|
438
|
526
|
_tx_udr_empty_irq();
|
|
527
|
+
|
|
528
|
+ sw_barrier();
|
439
|
529
|
}
|
440
|
|
- sw_barrier();
|
|
530
|
+
|
|
531
|
+ }
|
|
532
|
+ else {
|
|
533
|
+ // Wait until everything was transmitted
|
|
534
|
+ while (tx_buffer.head != tx_buffer.tail || !TEST(M_UCSRxA, M_TXCx)) sw_barrier();
|
441
|
535
|
}
|
442
|
|
- // If we get here, nothing is queued anymore (DRIE is disabled) and
|
|
536
|
+
|
|
537
|
+ // At this point nothing is queued anymore (DRIE is disabled) and
|
443
|
538
|
// the hardware finished transmission (TXC is set).
|
444
|
539
|
}
|
445
|
540
|
|
446
|
541
|
#else // TX_BUFFER_SIZE == 0
|
447
|
542
|
|
448
|
543
|
void MarlinSerial::write(const uint8_t c) {
|
|
544
|
+ _written = true;
|
449
|
545
|
while (!TEST(M_UCSRxA, M_UDREx)) sw_barrier();
|
450
|
546
|
M_UDRx = c;
|
451
|
547
|
}
|
452
|
548
|
|
|
549
|
+ void MarlinSerial::flushTX(void) {
|
|
550
|
+ // No bytes written, no need to flush. This special case is needed since there's
|
|
551
|
+ // no way to force the TXC (transmit complete) bit to 1 during initialization.
|
|
552
|
+ if (!_written) return;
|
|
553
|
+
|
|
554
|
+ // Wait until everything was transmitted
|
|
555
|
+ while (!TEST(M_UCSRxA, M_TXCx)) sw_barrier();
|
|
556
|
+
|
|
557
|
+ // At this point nothing is queued anymore (DRIE is disabled) and
|
|
558
|
+ // the hardware finished transmission (TXC is set).
|
|
559
|
+ }
|
453
|
560
|
#endif // TX_BUFFER_SIZE == 0
|
454
|
561
|
|
455
|
562
|
/**
|
|
@@ -473,13 +580,9 @@
|
473
|
580
|
}
|
474
|
581
|
|
475
|
582
|
void MarlinSerial::print(long n, int base) {
|
476
|
|
- if (base == 0)
|
477
|
|
- write(n);
|
|
583
|
+ if (base == 0) write(n);
|
478
|
584
|
else if (base == 10) {
|
479
|
|
- if (n < 0) {
|
480
|
|
- print('-');
|
481
|
|
- n = -n;
|
482
|
|
- }
|
|
585
|
+ if (n < 0) { print('-'); n = -n; }
|
483
|
586
|
printNumber(n, 10);
|
484
|
587
|
}
|
485
|
588
|
else
|