CARTESIO_UI has lcd contrast

Use Z_RAISE_BETWEEN_PROBINGS with MBL

Combine Z raise before/after options

Ensure a minimum height before XY move in probe_pt

Fix up delays in ST7920_SWSPI_SND_8BIT

by shitfing the left shift into the high phase.

```
2	cbi 0x2,1 ;set CLK                      //
1	in r18,__SREG__                         //1
1-3	sbrc r24,7                              //2-4
2	rjmp .L19                               //4
1	cli                  .L19:              //5
2	lds r25,258          lds r25,258        //7
1	andi r25,lo8(-2)     ori r25,lo8(1)     //8
2	sts 258,r25          sts 258,r25        //10
1	out __SREG__,r18     out __SREG__,r18   //11
2	.L3:                 rjmp .L3           //13     //2
2	sbi 0x2,1 ;reset CLK //                 //13-15  //2-4
1	lsl r24	 ;  val      //1
1	nop                  //2
2	cbi 0x2,1 ;set CLK   //4
...
```

and saving ~1k memory
by limiting the `#pragma GCC optimize (3)` optimisation to `ultralcd_st7920_u8glib_rrd.h`. These optimisation was and is not done for all the other displays, is the reason for the big additionally use of memory, because the complete 'ultralcd.cpp' and 'dogm_lcd_implementation.h' was optimised (sadly i did not observe a change in speed).

Unrolling the loop in `ST7920_SWSPI_SND_8BIT()`, what i expected the optimiser to do, by hand, saved some speed by eliminating the loop variable (i) compares and increases. Every CPU cycle in this loop costs at least 0.5ms per display update because it's executed more than 1k times/s.

The delays are now pre-filled with the calculated values for 4.5V driven ST7920.
A way to simply add __your__ timing into the configuration was made.

At 4.5V
1.) The CLK signal needs to be at least 200ns high and 200ns low.
2.) The DAT pin needs to be set at least 40ns before CLK goes high and must stay at this value until 40ns after CLK went high.

A nop takes one processor cycle.
For 16MHz one nop lasts 62.5ns.
For 20MHz one not lasts 50ns.

To fulfill condition 1.) we need 200/62.5 = 3.2 => 4 cycles (200/50 = 4 => 4). For the low phase, setting the pin takes much longer. For the high phase we (theoretically) have to throw in 2 nops, because changing the CLK takes only 2 cycles.

Condition 2.) is always fulfilled because the processor needs two cycles (100 - 125ns) for switching the CLK pin.


Needs tests and feedback.
Especially i cant test 20MHz, 3DRAG and displays supplied wit less than 5V.
Are the delays right? Please experiment with longer or shorter delays. And give feedback.

Already tested are 5 displays with 4.9V - 5.1V at 16MHz where no delays are needed.

Fix debug output in probe_pt

MBL: Add support for max z endstop

See https://github.com/MarlinFirmware/Marlin/issues/4088

Always do a brief delay in `lcd_quick_feedback`

Single home Axis Delta need simple sync_plan_position

Additional cleanup to probing/leveling

Fixes some compiler warnings

Patch LIN_ADVANCE timing issue

Make probes independent of leveling

Also the extruder stepper ISR has to keep an eye on step_loops count.

Derived from
https://github.com/AnHardt/Marlin/commit/6e8ede8c69
7f8d8e0dd