Fix #10761

- Also implemented real endstop reading on interrupt.

- Fixed the planner incorrectly avoiding optimization of the block following the active one.
- Added extra conditions to terminate planner early and avoid redundant computations.

Allows the Stepper ISR to wait until a given block is free for use. Allows Planner to plan the first move, which is split into two.

Better encapsulation and considerably reduce stepper jitter

Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Alternative to the apparently superfluous double delay

Followup to #10656

`DONT_SWITCH` got lost along the way. Replace it with `DO_SWITCH_EXTRUDER` and adjust the code.

Fix #10699

Fix #10708

As pointed out in #10731

Use macros that explicitly avoid double-evaluation and can be used for any datatype, replacing `min`, `max`, `abs`, `fabs`, `labs`, and `FABS`.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

- Cleanups, fixes for Due HAL code.
- TC_IER is write-only. Use TC_IMR to test ISR state.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Co-Authored-By: Zwaubel

Co-Authored-By: ejtagle <ejtagle@hotmail.com>