Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

- Cleanups, fixes for Due HAL code.
- TC_IER is write-only. Use TC_IMR to test ISR state.

Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.

- Watchdog reset during SD Card initialization.
- Move `DebugMonitor` to `DebugMonitor_Due.cpp`.
- Since the watchdog is enabled on boot do extra resets during init.
- Have `thermalManager` do watchdog reset before its ISR starts to prevent reset.
- Ensure that timers are stopped before reprogramming them to address tone issues.
- Improve SAM3XE reset when reflashed through the native port.

To reduce confusion over the current timer count vs. the compare (aka "top") value. Caution: this re-uses the function name, changing its meaning.

Some also get a `HAL_timer_interrupt_enabled` function.