Co-Authored-By: zarthcode <anthony.clay@zarthcode.com>

Better encapsulation and considerably reduce stepper jitter

Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)

Fix #10708

Use macros that explicitly avoid double-evaluation and can be used for any datatype, replacing `min`, `max`, `abs`, `fabs`, `labs`, and `FABS`.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

on the STM32 platform

Followup to #10516

Response to #10435

* Remove obsolete strings
* Tweak some static consts
* Reset LCD status to fallbacks

Restore necessary and needed loop termination logic.

Fix #10410

…to fit more code on the screen and correct outdated commentary contrasting ABL.

Addressing #10200