My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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system_LPC17xx.c 24KB

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  1. /**************************************************************************//**
  2. * @file system_LPC17xx.c
  3. * @brief CMSIS Cortex-M3 Device System Source File for
  4. * NXP LPC17xx Device Series
  5. * @version V1.11
  6. * @date 21. June 2011
  7. *
  8. * @note
  9. * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
  10. *
  11. * @par
  12. * ARM Limited (ARM) is supplying this software for use with Cortex-M
  13. * processor based microcontrollers. This file can be freely distributed
  14. * within development tools that are supporting such ARM based processors.
  15. *
  16. * @par
  17. * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  18. * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  20. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  21. * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  22. *
  23. ******************************************************************************/
  24. #include <stdint.h>
  25. #include "LPC17xx.h"
  26. /** @addtogroup LPC17xx_System
  27. * @{
  28. */
  29. /*
  30. //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  31. */
  32. /*--------------------- Clock Configuration ----------------------------------
  33. //
  34. // <e> Clock Configuration
  35. // <h> System Controls and Status Register (SCS)
  36. // <o1.4> OSCRANGE: Main Oscillator Range Select
  37. // <0=> 1 MHz to 20 MHz
  38. // <1=> 15 MHz to 25 MHz
  39. // <e1.5> OSCEN: Main Oscillator Enable
  40. // </e>
  41. // </h>
  42. //
  43. // <h> Clock Source Select Register (CLKSRCSEL)
  44. // <o2.0..1> CLKSRC: PLL Clock Source Selection
  45. // <0=> Internal RC oscillator
  46. // <1=> Main oscillator
  47. // <2=> RTC oscillator
  48. // </h>
  49. //
  50. // <e3> PLL0 Configuration (Main PLL)
  51. // <h> PLL0 Configuration Register (PLL0CFG)
  52. // <i> F_cco0 = (2 * M * F_in) / N
  53. // <i> F_in must be in the range of 32 kHz to 50 MHz
  54. // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
  55. // <o4.0..14> MSEL: PLL Multiplier Selection
  56. // <6-32768><#-1>
  57. // <i> M Value
  58. // <o4.16..23> NSEL: PLL Divider Selection
  59. // <1-256><#-1>
  60. // <i> N Value
  61. // </h>
  62. // </e>
  63. //
  64. // <e5> PLL1 Configuration (USB PLL)
  65. // <h> PLL1 Configuration Register (PLL1CFG)
  66. // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
  67. // <i> F_cco1 = F_osc * M * 2 * P
  68. // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
  69. // <o6.0..4> MSEL: PLL Multiplier Selection
  70. // <1-32><#-1>
  71. // <i> M Value (for USB maximum value is 4)
  72. // <o6.5..6> PSEL: PLL Divider Selection
  73. // <0=> 1
  74. // <1=> 2
  75. // <2=> 4
  76. // <3=> 8
  77. // <i> P Value
  78. // </h>
  79. // </e>
  80. //
  81. // <h> CPU Clock Configuration Register (CCLKCFG)
  82. // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
  83. // <1-256><#-1>
  84. // </h>
  85. //
  86. // <h> USB Clock Configuration Register (USBCLKCFG)
  87. // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
  88. // <0-15>
  89. // <i> Divide is USBSEL + 1
  90. // </h>
  91. //
  92. // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
  93. // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
  94. // <0=> Pclk = Cclk / 4
  95. // <1=> Pclk = Cclk
  96. // <2=> Pclk = Cclk / 2
  97. // <3=> Pclk = Hclk / 8
  98. // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
  99. // <0=> Pclk = Cclk / 4
  100. // <1=> Pclk = Cclk
  101. // <2=> Pclk = Cclk / 2
  102. // <3=> Pclk = Hclk / 8
  103. // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
  104. // <0=> Pclk = Cclk / 4
  105. // <1=> Pclk = Cclk
  106. // <2=> Pclk = Cclk / 2
  107. // <3=> Pclk = Hclk / 8
  108. // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
  109. // <0=> Pclk = Cclk / 4
  110. // <1=> Pclk = Cclk
  111. // <2=> Pclk = Cclk / 2
  112. // <3=> Pclk = Hclk / 8
  113. // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
  114. // <0=> Pclk = Cclk / 4
  115. // <1=> Pclk = Cclk
  116. // <2=> Pclk = Cclk / 2
  117. // <3=> Pclk = Hclk / 8
  118. // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
  119. // <0=> Pclk = Cclk / 4
  120. // <1=> Pclk = Cclk
  121. // <2=> Pclk = Cclk / 2
  122. // <3=> Pclk = Hclk / 8
  123. // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
  124. // <0=> Pclk = Cclk / 4
  125. // <1=> Pclk = Cclk
  126. // <2=> Pclk = Cclk / 2
  127. // <3=> Pclk = Hclk / 8
  128. // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
  129. // <0=> Pclk = Cclk / 4
  130. // <1=> Pclk = Cclk
  131. // <2=> Pclk = Cclk / 2
  132. // <3=> Pclk = Hclk / 8
  133. // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
  134. // <0=> Pclk = Cclk / 4
  135. // <1=> Pclk = Cclk
  136. // <2=> Pclk = Cclk / 2
  137. // <3=> Pclk = Hclk / 8
  138. // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
  139. // <0=> Pclk = Cclk / 4
  140. // <1=> Pclk = Cclk
  141. // <2=> Pclk = Cclk / 2
  142. // <3=> Pclk = Hclk / 8
  143. // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
  144. // <0=> Pclk = Cclk / 4
  145. // <1=> Pclk = Cclk
  146. // <2=> Pclk = Cclk / 2
  147. // <3=> Pclk = Hclk / 8
  148. // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
  149. // <0=> Pclk = Cclk / 4
  150. // <1=> Pclk = Cclk
  151. // <2=> Pclk = Cclk / 2
  152. // <3=> Pclk = Hclk / 6
  153. // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
  154. // <0=> Pclk = Cclk / 4
  155. // <1=> Pclk = Cclk
  156. // <2=> Pclk = Cclk / 2
  157. // <3=> Pclk = Hclk / 6
  158. // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
  159. // <0=> Pclk = Cclk / 4
  160. // <1=> Pclk = Cclk
  161. // <2=> Pclk = Cclk / 2
  162. // <3=> Pclk = Hclk / 6
  163. // </h>
  164. //
  165. // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
  166. // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
  167. // <0=> Pclk = Cclk / 4
  168. // <1=> Pclk = Cclk
  169. // <2=> Pclk = Cclk / 2
  170. // <3=> Pclk = Hclk / 8
  171. // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
  172. // <0=> Pclk = Cclk / 4
  173. // <1=> Pclk = Cclk
  174. // <2=> Pclk = Cclk / 2
  175. // <3=> Pclk = Hclk / 8
  176. // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
  177. // <0=> Pclk = Cclk / 4
  178. // <1=> Pclk = Cclk
  179. // <2=> Pclk = Cclk / 2
  180. // <3=> Pclk = Hclk / 8
  181. // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
  182. // <0=> Pclk = Cclk / 4
  183. // <1=> Pclk = Cclk
  184. // <2=> Pclk = Cclk / 2
  185. // <3=> Pclk = Hclk / 8
  186. // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
  187. // <0=> Pclk = Cclk / 4
  188. // <1=> Pclk = Cclk
  189. // <2=> Pclk = Cclk / 2
  190. // <3=> Pclk = Hclk / 8
  191. // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
  192. // <0=> Pclk = Cclk / 4
  193. // <1=> Pclk = Cclk
  194. // <2=> Pclk = Cclk / 2
  195. // <3=> Pclk = Hclk / 8
  196. // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
  197. // <0=> Pclk = Cclk / 4
  198. // <1=> Pclk = Cclk
  199. // <2=> Pclk = Cclk / 2
  200. // <3=> Pclk = Hclk / 8
  201. // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
  202. // <0=> Pclk = Cclk / 4
  203. // <1=> Pclk = Cclk
  204. // <2=> Pclk = Cclk / 2
  205. // <3=> Pclk = Hclk / 8
  206. // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
  207. // <0=> Pclk = Cclk / 4
  208. // <1=> Pclk = Cclk
  209. // <2=> Pclk = Cclk / 2
  210. // <3=> Pclk = Hclk / 8
  211. // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
  212. // <0=> Pclk = Cclk / 4
  213. // <1=> Pclk = Cclk
  214. // <2=> Pclk = Cclk / 2
  215. // <3=> Pclk = Hclk / 8
  216. // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
  217. // <0=> Pclk = Cclk / 4
  218. // <1=> Pclk = Cclk
  219. // <2=> Pclk = Cclk / 2
  220. // <3=> Pclk = Hclk / 8
  221. // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
  222. // <0=> Pclk = Cclk / 4
  223. // <1=> Pclk = Cclk
  224. // <2=> Pclk = Cclk / 2
  225. // <3=> Pclk = Hclk / 8
  226. // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
  227. // <0=> Pclk = Cclk / 4
  228. // <1=> Pclk = Cclk
  229. // <2=> Pclk = Cclk / 2
  230. // <3=> Pclk = Hclk / 8
  231. // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
  232. // <0=> Pclk = Cclk / 4
  233. // <1=> Pclk = Cclk
  234. // <2=> Pclk = Cclk / 2
  235. // <3=> Pclk = Hclk / 8
  236. // </h>
  237. //
  238. // <h> Power Control for Peripherals Register (PCONP)
  239. // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
  240. // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
  241. // <o11.3> PCUART0: UART 0 power/clock enable
  242. // <o11.4> PCUART1: UART 1 power/clock enable
  243. // <o11.6> PCPWM1: PWM 1 power/clock enable
  244. // <o11.7> PCI2C0: I2C interface 0 power/clock enable
  245. // <o11.8> PCSPI: SPI interface power/clock enable
  246. // <o11.9> PCRTC: RTC power/clock enable
  247. // <o11.10> PCSSP1: SSP interface 1 power/clock enable
  248. // <o11.12> PCAD: A/D converter power/clock enable
  249. // <o11.13> PCCAN1: CAN controller 1 power/clock enable
  250. // <o11.14> PCCAN2: CAN controller 2 power/clock enable
  251. // <o11.15> PCGPIO: GPIOs power/clock enable
  252. // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
  253. // <o11.17> PCMC: Motor control PWM power/clock enable
  254. // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
  255. // <o11.19> PCI2C1: I2C interface 1 power/clock enable
  256. // <o11.21> PCSSP0: SSP interface 0 power/clock enable
  257. // <o11.22> PCTIM2: Timer 2 power/clock enable
  258. // <o11.23> PCTIM3: Timer 3 power/clock enable
  259. // <o11.24> PCUART2: UART 2 power/clock enable
  260. // <o11.25> PCUART3: UART 3 power/clock enable
  261. // <o11.26> PCI2C2: I2C interface 2 power/clock enable
  262. // <o11.27> PCI2S: I2S interface power/clock enable
  263. // <o11.29> PCGPDMA: GP DMA function power/clock enable
  264. // <o11.30> PCENET: Ethernet block power/clock enable
  265. // <o11.31> PCUSB: USB interface power/clock enable
  266. // </h>
  267. //
  268. // <h> Clock Output Configuration Register (CLKOUTCFG)
  269. // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
  270. // <0=> CPU clock
  271. // <1=> Main oscillator
  272. // <2=> Internal RC oscillator
  273. // <3=> USB clock
  274. // <4=> RTC oscillator
  275. // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
  276. // <1-16><#-1>
  277. // <o12.8> CLKOUT_EN: CLKOUT enable control
  278. // </h>
  279. //
  280. // </e>
  281. */
  282. /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines
  283. @{
  284. */
  285. #define CLOCK_SETUP 1
  286. #define SCS_Val 0x00000020
  287. #define CLKSRCSEL_Val 0x00000001
  288. #define PLL0_SETUP 1 // WARNING: NOT USED, see SystemInit() below
  289. # define PLL0CFG_Val 0x0000000B // WARNING: NOT USED, see SystemInit() below
  290. # define PLL1_SETUP 0 // WARNING: NOT USED, see SystemInit() below
  291. # define PLL1CFG_Val 0x00000000 // WARNING: NOT USED, see SystemInit() below
  292. # define CCLKCFG_Val 0x00000002 // WARNING: NOT USED, see SystemInit() below
  293. # define USBCLKCFG_Val 0x00000005 // WARNING: NOT USED, see SystemInit() below
  294. #define PCLKSEL0_Val 0x00000000
  295. #define PCLKSEL1_Val 0x00000000
  296. #define PCONP_Val 0x042887DE
  297. #define CLKOUTCFG_Val 0x00000000
  298. /*--------------------- Flash Accelerator Configuration ----------------------
  299. //
  300. // <e> Flash Accelerator Configuration
  301. // <o1.12..15> FLASHTIM: Flash Access Time
  302. // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
  303. // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
  304. // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
  305. // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
  306. // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
  307. // <5=> 6 CPU clocks (for any CPU clock)
  308. // </e>
  309. */
  310. #define FLASH_SETUP 1
  311. #define FLASHCFG_Val 0x0000303A
  312. /*
  313. //-------- <<< end of configuration section >>> ------------------------------
  314. */
  315. /*----------------------------------------------------------------------------
  316. Check the register settings
  317. *----------------------------------------------------------------------------*/
  318. #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
  319. #define CHECK_RSVD(val, mask) (val & mask)
  320. /* Clock Configuration -------------------------------------------------------*/
  321. #if (CHECK_RSVD((SCS_Val), ~0x00000030))
  322. #error "SCS: Invalid values of reserved bits!"
  323. #endif
  324. #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
  325. #error "CLKSRCSEL: Value out of range!"
  326. #endif
  327. #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
  328. #error "PLL0CFG: Invalid values of reserved bits!"
  329. #endif
  330. #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
  331. #error "PLL1CFG: Invalid values of reserved bits!"
  332. #endif
  333. #if (PLL0_SETUP) /* if PLL0 is used */
  334. #if (CCLKCFG_Val < 2) /* CCLKSEL must be greater then 1 */
  335. #error "CCLKCFG: CCLKSEL must be greater then 1 if PLL0 is used!"
  336. #endif
  337. #endif
  338. #if (CHECK_RANGE((CCLKCFG_Val), 2, 255))
  339. #error "CCLKCFG: Value out of range!"
  340. #endif
  341. #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
  342. #error "USBCLKCFG: Invalid values of reserved bits!"
  343. #endif
  344. #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
  345. #error "PCLKSEL0: Invalid values of reserved bits!"
  346. #endif
  347. #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
  348. #error "PCLKSEL1: Invalid values of reserved bits!"
  349. #endif
  350. #if (CHECK_RSVD((PCONP_Val), 0x10100821))
  351. #error "PCONP: Invalid values of reserved bits!"
  352. #endif
  353. #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
  354. #error "CLKOUTCFG: Invalid values of reserved bits!"
  355. #endif
  356. /* Flash Accelerator Configuration -------------------------------------------*/
  357. #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
  358. #error "FLASHCFG: Invalid values of reserved bits!"
  359. #endif
  360. /*----------------------------------------------------------------------------
  361. DEFINES
  362. *----------------------------------------------------------------------------*/
  363. /*----------------------------------------------------------------------------
  364. Define clocks
  365. *----------------------------------------------------------------------------*/
  366. #define XTAL (12000000UL) /* Oscillator frequency */
  367. #define OSC_CLK ( XTAL) /* Main oscillator frequency */
  368. #define RTC_CLK ( 32000UL) /* RTC oscillator frequency */
  369. #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
  370. /* F_cco0 = (2 * M * F_in) / N */
  371. #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
  372. #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
  373. #define __FCCO(__F_IN) ((2ULL * __M * __F_IN) / __N)
  374. #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
  375. /* Determine core clock frequency according to settings */
  376. #if (PLL0_SETUP)
  377. #if ((CLKSRCSEL_Val & 0x03) == 1)
  378. #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
  379. #elif ((CLKSRCSEL_Val & 0x03) == 2)
  380. #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
  381. #else
  382. #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
  383. #endif
  384. #else
  385. #if ((CLKSRCSEL_Val & 0x03) == 1)
  386. #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
  387. #elif ((CLKSRCSEL_Val & 0x03) == 2)
  388. #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
  389. #else
  390. #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
  391. #endif
  392. #endif
  393. /**
  394. * @}
  395. */
  396. /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables
  397. @{
  398. */
  399. /*----------------------------------------------------------------------------
  400. Clock Variable definitions
  401. *----------------------------------------------------------------------------*/
  402. uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
  403. /**
  404. * @}
  405. */
  406. /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions
  407. @{
  408. */
  409. /**
  410. * Update SystemCoreClock variable
  411. *
  412. * @param none
  413. * @return none
  414. *
  415. * @brief Updates the SystemCoreClock with current core Clock
  416. * retrieved from cpu registers.
  417. */
  418. void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
  419. {
  420. /* Determine clock frequency according to clock register values */
  421. if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
  422. switch (LPC_SC->CLKSRCSEL & 0x03) {
  423. case 0: /* Int. RC oscillator => PLL0 */
  424. case 3: /* Reserved, default to Int. RC */
  425. SystemCoreClock = (IRC_OSC *
  426. ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
  427. (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
  428. ((LPC_SC->CCLKCFG & 0xFF)+ 1));
  429. break;
  430. case 1: /* Main oscillator => PLL0 */
  431. SystemCoreClock = (OSC_CLK *
  432. ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
  433. (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
  434. ((LPC_SC->CCLKCFG & 0xFF)+ 1));
  435. break;
  436. case 2: /* RTC oscillator => PLL0 */
  437. SystemCoreClock = (RTC_CLK *
  438. ((2ULL * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
  439. (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
  440. ((LPC_SC->CCLKCFG & 0xFF)+ 1));
  441. break;
  442. }
  443. } else {
  444. switch (LPC_SC->CLKSRCSEL & 0x03) {
  445. case 0: /* Int. RC oscillator => PLL0 */
  446. case 3: /* Reserved, default to Int. RC */
  447. SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
  448. break;
  449. case 1: /* Main oscillator => PLL0 */
  450. SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
  451. break;
  452. case 2: /* RTC oscillator => PLL0 */
  453. SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
  454. break;
  455. }
  456. }
  457. }
  458. // detect 17x[4-8] (100MHz) or 17x9 (120MHz)
  459. int isLPC1769() {
  460. #define IAP_LOCATION 0x1FFF1FF1
  461. uint32_t command[1];
  462. uint32_t result[5];
  463. typedef void (*IAP)(uint32_t*, uint32_t*);
  464. IAP iap = (IAP) IAP_LOCATION;
  465. command[0] = 54;
  466. iap(command, result);
  467. return result[1] & 0x00100000;
  468. }
  469. /**
  470. * Initialize the system
  471. *
  472. * @param none
  473. * @return none
  474. *
  475. * @brief Setup the microcontroller system.
  476. * Initialize the System.
  477. */
  478. void SystemInit (void)
  479. {
  480. #if (CLOCK_SETUP) /* Clock Setup */
  481. LPC_SC->SCS = SCS_Val;
  482. if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
  483. while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
  484. }
  485. /* Periphral clock must be selected before PLL0 enabling and connecting
  486. * - according errata.lpc1768-16.March.2010 -
  487. */
  488. LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
  489. LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
  490. /*
  491. * PLL0 MUST be 275 - 550MHz
  492. *
  493. * PLL0 = Fin * M * 2 / N
  494. *
  495. * Fcpu = PLL0 / D
  496. *
  497. * PLL0CFG = (M - 1) + ((N - 1) << 16)
  498. * CCLKCFG = D - 1
  499. *
  500. * Common combinations (assuming 12MHz crystal):
  501. *
  502. * | Fcpu |--| Fin | M | N | PLL0 | D | PLL0CFG | CCLKCFG |
  503. * 96MHz :2* 12MHz * 12 / 1 = 288MHz / 3 0x0000B 0x2
  504. * 100MHz :2* 12MHz * 25 / 2 = 300MHz / 3 0x10018 0x2
  505. * 120MHz :2* 12MHz * 15 / 1 = 360MHz / 3 0x0000E 0x2
  506. *
  507. */
  508. LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
  509. LPC_SC->CCLKCFG = 0x00000002; /* Setup CPU Clock Divider */
  510. if(isLPC1769()) {
  511. LPC_SC->PLL0CFG = 0x0000000E; /* configure PLL0 */
  512. LPC_SC->PLL0FEED = 0xAA;
  513. LPC_SC->PLL0FEED = 0x55;
  514. } else {
  515. LPC_SC->PLL0CFG = 0x00010018; // 100MHz
  516. LPC_SC->PLL0FEED = 0xAA;
  517. LPC_SC->PLL0FEED = 0x55;
  518. }
  519. LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
  520. LPC_SC->PLL0FEED = 0xAA;
  521. LPC_SC->PLL0FEED = 0x55;
  522. while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
  523. LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
  524. LPC_SC->PLL0FEED = 0xAA;
  525. LPC_SC->PLL0FEED = 0x55;
  526. while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
  527. /*
  528. * USBCLK = Fin * M, where M is (1..32)
  529. *
  530. * we need a USBCLK of 48MHz, so given a 12MHz crystal, M must be 4
  531. *
  532. * PLL1 = USBCLK * 2 * P, where P is one of (1, 2, 4, 8)
  533. *
  534. * PLL1 MUST be 156 to 320MHz.
  535. * P=2 gives 192MHz, the only valid value within range
  536. *
  537. * PLL1CFG = (log2(P) << 5) + (M - 1)
  538. * = (1 << 5) + 3
  539. * = 0x23 for a 12MHz crystal
  540. */
  541. LPC_SC->PLL1CFG = 0x00000023;
  542. LPC_SC->PLL1FEED = 0xAA;
  543. LPC_SC->PLL1FEED = 0x55;
  544. LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
  545. LPC_SC->PLL1FEED = 0xAA;
  546. LPC_SC->PLL1FEED = 0x55;
  547. while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
  548. LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
  549. LPC_SC->PLL1FEED = 0xAA;
  550. LPC_SC->PLL1FEED = 0x55;
  551. while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
  552. // this sets up {global uint32 SystemCoreClock} with the new speed
  553. SystemCoreClockUpdate();
  554. LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
  555. LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
  556. #endif
  557. #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
  558. LPC_SC->FLASHCFG = (LPC_SC->FLASHCFG & ~0x0000F000) | FLASHCFG_Val;
  559. #endif
  560. }
  561. /**
  562. * @}
  563. */
  564. /**
  565. * @}
  566. */