My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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HAL_timers_SAMD51.cpp 4.6KB

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  1. /**
  2. * Marlin 3D Printer Firmware
  3. *
  4. * Copyright (C) 2019 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
  5. * SAMD51 HAL developed by Giuliano Zaro (AKA GMagician)
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation, either version 3 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  19. *
  20. */
  21. #ifdef __SAMD51__
  22. // --------------------------------------------------------------------------
  23. // Includes
  24. // --------------------------------------------------------------------------
  25. #include "../../inc/MarlinConfig.h"
  26. #include "HAL_timers_SAMD51.h"
  27. // --------------------------------------------------------------------------
  28. // Local defines
  29. // --------------------------------------------------------------------------
  30. #define NUM_HARDWARE_TIMERS 8
  31. // --------------------------------------------------------------------------
  32. // Private Variables
  33. // --------------------------------------------------------------------------
  34. const tTimerConfig TimerConfig[NUM_HARDWARE_TIMERS] = {
  35. { TC0, TC0_IRQn, TC_PRIORITY(0) },
  36. { TC1, TC1_IRQn, TC_PRIORITY(1) },
  37. { TC2, TC2_IRQn, TC_PRIORITY(2) },
  38. { TC3, TC3_IRQn, TC_PRIORITY(3) },
  39. { TC4, TC4_IRQn, TC_PRIORITY(4) },
  40. { TC5, TC5_IRQn, TC_PRIORITY(5) },
  41. { TC6, TC6_IRQn, TC_PRIORITY(6) },
  42. { TC7, TC7_IRQn, TC_PRIORITY(7) }
  43. };
  44. // --------------------------------------------------------------------------
  45. // Private functions
  46. // --------------------------------------------------------------------------
  47. FORCE_INLINE void Disable_Irq(IRQn_Type irq) {
  48. NVIC_DisableIRQ(irq);
  49. // We NEED memory barriers to ensure Interrupts are actually disabled!
  50. // ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
  51. __DSB();
  52. __ISB();
  53. }
  54. // --------------------------------------------------------------------------
  55. // Public functions
  56. // --------------------------------------------------------------------------
  57. void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
  58. Tc * const tc = TimerConfig[timer_num].pTimer;
  59. IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
  60. // Disable interrupt, just in case it was already enabled
  61. Disable_Irq(irq);
  62. // Disable timer interrupt
  63. tc->COUNT32.INTENCLR.reg = TC_INTENCLR_OVF; // disable overflow interrupt
  64. // TCn clock setup
  65. const uint8_t clockID = GCLK_CLKCTRL_IDs[TCC_INST_NUM + timer_num];
  66. GCLK->PCHCTRL[clockID].bit.CHEN = false;
  67. SYNC(GCLK->PCHCTRL[clockID].bit.CHEN);
  68. GCLK->PCHCTRL[clockID].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN; // 120MHz startup code programmed
  69. SYNC(!GCLK->PCHCTRL[clockID].bit.CHEN);
  70. // Stop timer, just in case, to be able to reconfigure it
  71. tc->COUNT32.CTRLA.bit.ENABLE = false;
  72. SYNC(tc->COUNT32.SYNCBUSY.bit.ENABLE);
  73. // Reset timer
  74. tc->COUNT32.CTRLA.bit.SWRST = true;
  75. SYNC(tc->COUNT32.SYNCBUSY.bit.SWRST);
  76. NVIC_SetPriority(irq, TimerConfig[timer_num].priority);
  77. // Wave mode, reset counter on overflow on 0 (I use count down to prevent double buffer use)
  78. tc->COUNT32.WAVE.reg = TC_WAVE_WAVEGEN_MFRQ;
  79. tc->COUNT32.CTRLA.reg = TC_CTRLA_MODE_COUNT32 | TC_CTRLA_PRESCALER_DIV1;
  80. tc->COUNT32.CTRLBSET.reg = TC_CTRLBCLR_DIR;
  81. SYNC(tc->COUNT32.SYNCBUSY.bit.CTRLB);
  82. // Set compare value
  83. tc->COUNT32.COUNT.reg = tc->COUNT32.CC[0].reg = HAL_TIMER_RATE / frequency;
  84. // And start timer
  85. tc->COUNT32.CTRLA.bit.ENABLE = true;
  86. SYNC(tc->COUNT32.SYNCBUSY.bit.ENABLE);
  87. // Enable interrupt on RC compare
  88. tc->COUNT32.INTENSET.reg = TC_INTENCLR_OVF; // enable overflow interrupt
  89. // Finally, enable IRQ
  90. NVIC_EnableIRQ(irq);
  91. }
  92. void HAL_timer_enable_interrupt(const uint8_t timer_num) {
  93. IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
  94. NVIC_EnableIRQ(irq);
  95. }
  96. void HAL_timer_disable_interrupt(const uint8_t timer_num) {
  97. IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
  98. Disable_Irq(irq);
  99. }
  100. // missing from CMSIS: Check if interrupt is enabled or not
  101. static bool NVIC_GetEnabledIRQ(IRQn_Type IRQn) {
  102. return (NVIC->ISER[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F))) != 0;
  103. }
  104. bool HAL_timer_interrupt_enabled(const uint8_t timer_num) {
  105. IRQn_Type irq = TimerConfig[timer_num].IRQ_Id;
  106. return NVIC_GetEnabledIRQ(irq);
  107. }
  108. #endif // __SAMD51__