My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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variant.cpp 7.5KB

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  1. /*
  2. *******************************************************************************
  3. * Copyright (c) 2017, STMicroelectronics
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice,
  10. * this list of conditions and the following disclaimer.
  11. * 2. Redistributions in binary form must reproduce the above copyright notice,
  12. * this list of conditions and the following disclaimer in the documentation
  13. * and/or other materials provided with the distribution.
  14. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  15. * may be used to endorse or promote products derived from this software
  16. * without specific prior written permission.
  17. *
  18. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  19. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  21. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  22. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  24. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  25. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  26. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28. *******************************************************************************
  29. */
  30. #include "pins_arduino.h"
  31. #ifdef __cplusplus
  32. extern "C" {
  33. #endif
  34. const PinName digitalPin[] = {
  35. PB_12,
  36. PB_13,
  37. PB_14,
  38. PB_15,
  39. PD_8,
  40. PD_9,
  41. PD_10,
  42. PD_11,
  43. PD_12,
  44. PD_13,
  45. PD_14,
  46. PD_15,
  47. PG_2,
  48. PG_3,
  49. PG_4,
  50. PG_5,
  51. PG_6,
  52. PG_7,
  53. PG_8,
  54. PC_6,
  55. PC_7,
  56. PC_8,
  57. PC_9,
  58. PA_8,
  59. PA_9,
  60. PA_10,
  61. PA_11,
  62. PA_12,
  63. PA_13,
  64. PA_14,
  65. PA_15,
  66. PC_10,
  67. PC_11,
  68. PC_12,
  69. PD_0,
  70. PD_1,
  71. PD_2,
  72. PD_3,
  73. PD_4,
  74. PD_5,
  75. PD_6,
  76. PD_7,
  77. PG_9,
  78. PG_10,
  79. PG_11,
  80. PG_12,
  81. PG_13,
  82. PG_14,
  83. PG_15,
  84. PB_3,
  85. PB_4,
  86. PB_5,
  87. PB_6,
  88. PB_7,
  89. PB_8,
  90. PB_9,
  91. PB_10,
  92. PB_11,
  93. PE_14,
  94. PE_15,
  95. PE_12,
  96. PE_13,
  97. PE_10,
  98. PE_11,
  99. PE_8,
  100. PE_9,
  101. PG_1,
  102. PE_7,
  103. PF_15,
  104. PG_0,
  105. PF_13,
  106. PF_14,
  107. PF_11,
  108. PF_12,
  109. PB_2,
  110. PB_1,
  111. PC_5,
  112. PB_0,
  113. PA_7,
  114. PC_4,
  115. PA_5,
  116. PA_6,
  117. PA_3,
  118. PA_4,
  119. PA_1,
  120. PA_2,
  121. PC_3,
  122. PA_0,
  123. PC_1,
  124. PC_2,
  125. PC_0,
  126. PF_8,
  127. PF_6,
  128. PF_7,
  129. PF_9,
  130. PF_10,
  131. PF_4,
  132. PF_5,
  133. PF_2,
  134. PF_3,
  135. PF_0,
  136. PF_1,
  137. PE_6,
  138. PC_13,
  139. PE_4,
  140. PE_5,
  141. PE_2,
  142. PE_3,
  143. PE_0,
  144. PE_1,
  145. PC_14,
  146. PC_15,
  147. };
  148. #ifdef __cplusplus
  149. }
  150. #endif
  151. // ----------------------------------------------------------------------------
  152. #ifdef __cplusplus
  153. extern "C" {
  154. #endif
  155. #define __fatal_error(X)
  156. /**
  157. * @brief System Clock Configuration
  158. *
  159. * The system Clock is configured for F4/F7 as follows:
  160. * System Clock source = PLL (HSE)
  161. * SYSCLK(Hz) = 168000000
  162. * HCLK(Hz) = 168000000
  163. * AHB Prescaler = 1
  164. * APB1 Prescaler = 4
  165. * APB2 Prescaler = 2
  166. * HSE Frequency(Hz) = HSE_VALUE
  167. * PLL_M = HSE_VALUE/1000000
  168. * PLL_N = 336
  169. * PLL_P = 2
  170. * PLL_Q = 7
  171. * VDD(V) = 3.3
  172. * Main regulator output voltage = Scale1 mode
  173. * Flash Latency(WS) = 5
  174. *
  175. * The system Clock is configured for L4 as follows:
  176. * System Clock source = PLL (MSI)
  177. * SYSCLK(Hz) = 80000000
  178. * HCLK(Hz) = 80000000
  179. * AHB Prescaler = 1
  180. * APB1 Prescaler = 1
  181. * APB2 Prescaler = 1
  182. * MSI Frequency(Hz) = MSI_VALUE (4000000)
  183. * LSE Frequency(Hz) = 32768
  184. * PLL_M = 1
  185. * PLL_N = 40
  186. * PLL_P = 7
  187. * PLL_Q = 2
  188. * PLL_R = 2 <= This is the source for SysClk, not as on F4/7 PLL_P
  189. * Flash Latency(WS) = 4
  190. * @param None
  191. * @retval None
  192. *
  193. * PLL is configured as follows:
  194. *
  195. * VCO_IN
  196. * F4/F7 = HSE / M
  197. * L4 = MSI / M
  198. * VCO_OUT
  199. * F4/F7 = HSE / M * N
  200. * L4 = MSI / M * N
  201. * PLLCLK
  202. * F4/F7 = HSE / M * N / P
  203. * L4 = MSI / M * N / R
  204. * PLL48CK
  205. * F4/F7 = HSE / M * N / Q
  206. * L4 = MSI / M * N / Q USB Clock is obtained over PLLSAI1
  207. *
  208. * SYSCLK = PLLCLK
  209. * HCLK = SYSCLK / AHB_PRESC
  210. * PCLKx = HCLK / APBx_PRESC
  211. *
  212. * Constraints on parameters:
  213. *
  214. * VCO_IN between 1MHz and 2MHz (2MHz recommended)
  215. * VCO_OUT between 192MHz and 432MHz
  216. * HSE = 8MHz
  217. * M = 2 .. 63 (inclusive)
  218. * N = 192 ... 432 (inclusive)
  219. * P = 2, 4, 6, 8
  220. * Q = 2 .. 15 (inclusive)
  221. *
  222. * AHB_PRESC=1,2,4,8,16,64,128,256,512
  223. * APBx_PRESC=1,2,4,8,16
  224. *
  225. * Output clocks:
  226. *
  227. * CPU SYSCLK max 168MHz
  228. * USB,RNG,SDIO PLL48CK must be 48MHz for USB
  229. * AHB HCLK max 168MHz
  230. * APB1 PCLK1 max 42MHz
  231. * APB2 PCLK2 max 84MHz
  232. *
  233. * Timers run from APBx if APBx_PRESC=1, else 2x APBx
  234. */
  235. void SystemClock_Config(void)
  236. {
  237. RCC_ClkInitTypeDef RCC_ClkInitStruct;
  238. RCC_OscInitTypeDef RCC_OscInitStruct;
  239. __PWR_CLK_ENABLE();
  240. /* The voltage scaling allows optimizing the power consumption when the device is
  241. clocked below the maximum system frequency, to update the voltage scaling value
  242. regarding system frequency refer to product datasheet. */
  243. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
  244. /* Enable HSE Oscillator and activate PLL with HSE as source */
  245. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  246. RCC_OscInitStruct.HSEState = RCC_HSE_ON;
  247. RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
  248. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  249. /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
  250. clocks dividers */
  251. RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
  252. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
  253. RCC_OscInitStruct.PLL.PLLM = 25;
  254. RCC_OscInitStruct.PLL.PLLN = 336;
  255. RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  256. RCC_OscInitStruct.PLL.PLLQ = 7;
  257. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
  258. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
  259. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
  260. if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
  261. __fatal_error("HAL_RCC_OscConfig");
  262. }
  263. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
  264. {
  265. __fatal_error("HAL_RCC_ClockConfig");
  266. }
  267. /**Configure the Systick interrupt time */
  268. HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
  269. /**Configure the Systick */
  270. HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
  271. /* SysTick_IRQn interrupt configuration */
  272. HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0);
  273. }
  274. #ifdef __cplusplus
  275. }
  276. #endif