My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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  1. /*----------------------------------------------------------------------------
  2. * U S B - K e r n e l
  3. *----------------------------------------------------------------------------
  4. * Name: usbreg.h
  5. * Purpose: USB Hardware Layer Definitions for NXP LPC Family MCUs
  6. * Version: V1.20
  7. *----------------------------------------------------------------------------
  8. * This software is supplied "AS IS" without any warranties, express,
  9. * implied or statutory, including but not limited to the implied
  10. * warranties of fitness for purpose, satisfactory quality and
  11. * noninfringement. Keil extends you a royalty-free right to reproduce
  12. * and distribute executable files created using this software for use
  13. * on NXP Semiconductors LPC family microcontroller devices only. Nothing
  14. * else gives you the right to use this software.
  15. *
  16. * Copyright (c) 2009 Keil - An ARM Company. All rights reserved.
  17. *---------------------------------------------------------------------------*/
  18. #ifndef __USBREG_H
  19. #define __USBREG_H
  20. /* Device Interrupt Bit Definitions */
  21. #define FRAME_INT 0x00000001
  22. #define EP_FAST_INT 0x00000002
  23. #define EP_SLOW_INT 0x00000004
  24. #define DEV_STAT_INT 0x00000008
  25. #define CCEMTY_INT 0x00000010
  26. #define CDFULL_INT 0x00000020
  27. #define RxENDPKT_INT 0x00000040
  28. #define TxENDPKT_INT 0x00000080
  29. #define EP_RLZED_INT 0x00000100
  30. #define ERR_INT 0x00000200
  31. /* Rx & Tx Packet Length Definitions */
  32. #define PKT_LNGTH_MASK 0x000003FF
  33. #define PKT_DV 0x00000400
  34. #define PKT_RDY 0x00000800
  35. /* USB Control Definitions */
  36. #define CTRL_RD_EN 0x00000001
  37. #define CTRL_WR_EN 0x00000002
  38. /* Command Codes */
  39. #define CMD_SET_ADDR 0x00D00500
  40. #define CMD_CFG_DEV 0x00D80500
  41. #define CMD_SET_MODE 0x00F30500
  42. #define CMD_RD_FRAME 0x00F50500
  43. #define DAT_RD_FRAME 0x00F50200
  44. #define CMD_RD_TEST 0x00FD0500
  45. #define DAT_RD_TEST 0x00FD0200
  46. #define CMD_SET_DEV_STAT 0x00FE0500
  47. #define CMD_GET_DEV_STAT 0x00FE0500
  48. #define DAT_GET_DEV_STAT 0x00FE0200
  49. #define CMD_GET_ERR_CODE 0x00FF0500
  50. #define DAT_GET_ERR_CODE 0x00FF0200
  51. #define CMD_RD_ERR_STAT 0x00FB0500
  52. #define DAT_RD_ERR_STAT 0x00FB0200
  53. #define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
  54. #define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
  55. #define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
  56. #define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
  57. #define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
  58. #define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
  59. #define CMD_CLR_BUF 0x00F20500
  60. #define DAT_CLR_BUF 0x00F20200
  61. #define CMD_VALID_BUF 0x00FA0500
  62. /* Device Address Register Definitions */
  63. #define DEV_ADDR_MASK 0x7F
  64. #define DEV_EN 0x80
  65. /* Device Configure Register Definitions */
  66. #define CONF_DVICE 0x01
  67. /* Device Mode Register Definitions */
  68. #define AP_CLK 0x01
  69. #define INAK_CI 0x02
  70. #define INAK_CO 0x04
  71. #define INAK_II 0x08
  72. #define INAK_IO 0x10
  73. #define INAK_BI 0x20
  74. #define INAK_BO 0x40
  75. /* Device Status Register Definitions */
  76. #define DEV_CON 0x01
  77. #define DEV_CON_CH 0x02
  78. #define DEV_SUS 0x04
  79. #define DEV_SUS_CH 0x08
  80. #define DEV_RST 0x10
  81. /* Error Code Register Definitions */
  82. #define ERR_EC_MASK 0x0F
  83. #define ERR_EA 0x10
  84. /* Error Status Register Definitions */
  85. #define ERR_PID 0x01
  86. #define ERR_UEPKT 0x02
  87. #define ERR_DCRC 0x04
  88. #define ERR_TIMOUT 0x08
  89. #define ERR_EOP 0x10
  90. #define ERR_B_OVRN 0x20
  91. #define ERR_BTSTF 0x40
  92. #define ERR_TGL 0x80
  93. /* Endpoint Select Register Definitions */
  94. #define EP_SEL_F 0x01
  95. #define EP_SEL_ST 0x02
  96. #define EP_SEL_STP 0x04
  97. #define EP_SEL_PO 0x08
  98. #define EP_SEL_EPN 0x10
  99. #define EP_SEL_B_1_FULL 0x20
  100. #define EP_SEL_B_2_FULL 0x40
  101. /* Endpoint Status Register Definitions */
  102. #define EP_STAT_ST 0x01
  103. #define EP_STAT_DA 0x20
  104. #define EP_STAT_RF_MO 0x40
  105. #define EP_STAT_CND_ST 0x80
  106. /* Clear Buffer Register Definitions */
  107. #define CLR_BUF_PO 0x01
  108. /* DMA Interrupt Bit Definitions */
  109. #define EOT_INT 0x01
  110. #define NDD_REQ_INT 0x02
  111. #define SYS_ERR_INT 0x04
  112. #endif /* __USBREG_H */