My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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  1. /**************************************************************************//**
  2. * @file LPC17xx.h
  3. * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
  4. * NXP LPC17xx Device Series
  5. * @version: V1.09
  6. * @date: 25. July. 2011
  7. *
  8. * @note
  9. * Copyright (C) 2009 ARM Limited. All rights reserved.
  10. *
  11. * @par
  12. * ARM Limited (ARM) is supplying this software for use with Cortex-M
  13. * processor based microcontrollers. This file can be freely distributed
  14. * within development tools that are supporting such ARM based processors.
  15. *
  16. * @par
  17. * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  18. * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  20. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  21. * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  22. *
  23. ******************************************************************************/
  24. #ifndef __LPC17xx_H__
  25. #define __LPC17xx_H__
  26. /*
  27. * ==========================================================================
  28. * ---------- Interrupt Number Definition -----------------------------------
  29. * ==========================================================================
  30. */
  31. /** @addtogroup LPC17xx_System
  32. * @{
  33. */
  34. /** @brief IRQ interrupt source definition */
  35. typedef enum IRQn
  36. {
  37. /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
  38. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  39. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
  40. BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
  41. UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
  42. SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
  43. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
  44. PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
  45. SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
  46. /****** LPC17xx Specific Interrupt Numbers *******************************************************/
  47. WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
  48. TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
  49. TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
  50. TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
  51. TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
  52. UART0_IRQn = 5, /*!< UART0 Interrupt */
  53. UART1_IRQn = 6, /*!< UART1 Interrupt */
  54. UART2_IRQn = 7, /*!< UART2 Interrupt */
  55. UART3_IRQn = 8, /*!< UART3 Interrupt */
  56. PWM1_IRQn = 9, /*!< PWM1 Interrupt */
  57. I2C0_IRQn = 10, /*!< I2C0 Interrupt */
  58. I2C1_IRQn = 11, /*!< I2C1 Interrupt */
  59. I2C2_IRQn = 12, /*!< I2C2 Interrupt */
  60. SPI_IRQn = 13, /*!< SPI Interrupt */
  61. SSP0_IRQn = 14, /*!< SSP0 Interrupt */
  62. SSP1_IRQn = 15, /*!< SSP1 Interrupt */
  63. PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
  64. RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
  65. EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
  66. EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
  67. EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
  68. EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
  69. ADC_IRQn = 22, /*!< A/D Converter Interrupt */
  70. BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
  71. USB_IRQn = 24, /*!< USB Interrupt */
  72. CAN_IRQn = 25, /*!< CAN Interrupt */
  73. DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
  74. I2S_IRQn = 27, /*!< I2S Interrupt */
  75. ENET_IRQn = 28, /*!< Ethernet Interrupt */
  76. RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
  77. MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
  78. QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
  79. PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
  80. USBActivity_IRQn = 33, /*!< USB Activity Interrupt */
  81. CANActivity_IRQn = 34 /*!< CAN Activity Interrupt */
  82. } IRQn_Type;
  83. /*
  84. * ==========================================================================
  85. * ----------- Processor and Core Peripheral Section ------------------------
  86. * ==========================================================================
  87. */
  88. /* Configuration of the Cortex-M3 Processor and Core Peripherals */
  89. #define __MPU_PRESENT 1 /*!< MPU present or not */
  90. #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
  91. #define __Vendor_SysTickConfig 1 /*!< Set to 1 if different SysTick Config is used */
  92. #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
  93. #include "system_LPC17xx.h" /* System Header */
  94. /******************************************************************************/
  95. /* Device Specific Peripheral registers structures */
  96. /******************************************************************************/
  97. #if defined ( __CC_ARM )
  98. #pragma anon_unions
  99. #endif
  100. /*------------- System Control (SC) ------------------------------------------*/
  101. /** @brief System Control (SC) register structure definition */
  102. typedef struct
  103. {
  104. __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
  105. uint32_t RESERVED0[31];
  106. __IO uint32_t PLL0CON; /* Clocking and Power Control */
  107. __IO uint32_t PLL0CFG;
  108. __I uint32_t PLL0STAT;
  109. __O uint32_t PLL0FEED;
  110. uint32_t RESERVED1[4];
  111. __IO uint32_t PLL1CON;
  112. __IO uint32_t PLL1CFG;
  113. __I uint32_t PLL1STAT;
  114. __O uint32_t PLL1FEED;
  115. uint32_t RESERVED2[4];
  116. __IO uint32_t PCON;
  117. __IO uint32_t PCONP;
  118. uint32_t RESERVED3[15];
  119. __IO uint32_t CCLKCFG;
  120. __IO uint32_t USBCLKCFG;
  121. __IO uint32_t CLKSRCSEL;
  122. __IO uint32_t CANSLEEPCLR;
  123. __IO uint32_t CANWAKEFLAGS;
  124. uint32_t RESERVED4[10];
  125. __IO uint32_t EXTINT; /* External Interrupts */
  126. uint32_t RESERVED5;
  127. __IO uint32_t EXTMODE;
  128. __IO uint32_t EXTPOLAR;
  129. uint32_t RESERVED6[12];
  130. __IO uint32_t RSID; /* Reset */
  131. uint32_t RESERVED7[7];
  132. __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
  133. __IO uint32_t IRCTRIM; /* Clock Dividers */
  134. __IO uint32_t PCLKSEL0;
  135. __IO uint32_t PCLKSEL1;
  136. uint32_t RESERVED8[4];
  137. __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
  138. __IO uint32_t DMAREQSEL;
  139. __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
  140. } LPC_SC_TypeDef;
  141. /*------------- Pin Connect Block (PINCON) -----------------------------------*/
  142. /** @brief Pin Connect Block (PINCON) register structure definition */
  143. typedef struct
  144. {
  145. __IO uint32_t PINSEL0;
  146. __IO uint32_t PINSEL1;
  147. __IO uint32_t PINSEL2;
  148. __IO uint32_t PINSEL3;
  149. __IO uint32_t PINSEL4;
  150. __IO uint32_t PINSEL5;
  151. __IO uint32_t PINSEL6;
  152. __IO uint32_t PINSEL7;
  153. __IO uint32_t PINSEL8;
  154. __IO uint32_t PINSEL9;
  155. __IO uint32_t PINSEL10;
  156. uint32_t RESERVED0[5];
  157. __IO uint32_t PINMODE0;
  158. __IO uint32_t PINMODE1;
  159. __IO uint32_t PINMODE2;
  160. __IO uint32_t PINMODE3;
  161. __IO uint32_t PINMODE4;
  162. __IO uint32_t PINMODE5;
  163. __IO uint32_t PINMODE6;
  164. __IO uint32_t PINMODE7;
  165. __IO uint32_t PINMODE8;
  166. __IO uint32_t PINMODE9;
  167. __IO uint32_t PINMODE_OD0;
  168. __IO uint32_t PINMODE_OD1;
  169. __IO uint32_t PINMODE_OD2;
  170. __IO uint32_t PINMODE_OD3;
  171. __IO uint32_t PINMODE_OD4;
  172. __IO uint32_t I2CPADCFG;
  173. } LPC_PINCON_TypeDef;
  174. /*------------- General Purpose Input/Output (GPIO) --------------------------*/
  175. /** @brief General Purpose Input/Output (GPIO) register structure definition */
  176. typedef struct
  177. {
  178. union {
  179. __IO uint32_t FIODIR;
  180. struct {
  181. __IO uint16_t FIODIRL;
  182. __IO uint16_t FIODIRH;
  183. };
  184. struct {
  185. __IO uint8_t FIODIR0;
  186. __IO uint8_t FIODIR1;
  187. __IO uint8_t FIODIR2;
  188. __IO uint8_t FIODIR3;
  189. };
  190. };
  191. uint32_t RESERVED0[3];
  192. union {
  193. __IO uint32_t FIOMASK;
  194. struct {
  195. __IO uint16_t FIOMASKL;
  196. __IO uint16_t FIOMASKH;
  197. };
  198. struct {
  199. __IO uint8_t FIOMASK0;
  200. __IO uint8_t FIOMASK1;
  201. __IO uint8_t FIOMASK2;
  202. __IO uint8_t FIOMASK3;
  203. };
  204. };
  205. union {
  206. __IO uint32_t FIOPIN;
  207. struct {
  208. __IO uint16_t FIOPINL;
  209. __IO uint16_t FIOPINH;
  210. };
  211. struct {
  212. __IO uint8_t FIOPIN0;
  213. __IO uint8_t FIOPIN1;
  214. __IO uint8_t FIOPIN2;
  215. __IO uint8_t FIOPIN3;
  216. };
  217. };
  218. union {
  219. __IO uint32_t FIOSET;
  220. struct {
  221. __IO uint16_t FIOSETL;
  222. __IO uint16_t FIOSETH;
  223. };
  224. struct {
  225. __IO uint8_t FIOSET0;
  226. __IO uint8_t FIOSET1;
  227. __IO uint8_t FIOSET2;
  228. __IO uint8_t FIOSET3;
  229. };
  230. };
  231. union {
  232. __O uint32_t FIOCLR;
  233. struct {
  234. __O uint16_t FIOCLRL;
  235. __O uint16_t FIOCLRH;
  236. };
  237. struct {
  238. __O uint8_t FIOCLR0;
  239. __O uint8_t FIOCLR1;
  240. __O uint8_t FIOCLR2;
  241. __O uint8_t FIOCLR3;
  242. };
  243. };
  244. } LPC_GPIO_TypeDef;
  245. /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
  246. typedef struct
  247. {
  248. __I uint32_t IntStatus;
  249. __I uint32_t IO0IntStatR;
  250. __I uint32_t IO0IntStatF;
  251. __O uint32_t IO0IntClr;
  252. __IO uint32_t IO0IntEnR;
  253. __IO uint32_t IO0IntEnF;
  254. uint32_t RESERVED0[3];
  255. __I uint32_t IO2IntStatR;
  256. __I uint32_t IO2IntStatF;
  257. __O uint32_t IO2IntClr;
  258. __IO uint32_t IO2IntEnR;
  259. __IO uint32_t IO2IntEnF;
  260. } LPC_GPIOINT_TypeDef;
  261. /*------------- Timer (TIM) --------------------------------------------------*/
  262. /** @brief Timer (TIM) register structure definition */
  263. typedef struct
  264. {
  265. __IO uint32_t IR;
  266. __IO uint32_t TCR;
  267. __IO uint32_t TC;
  268. __IO uint32_t PR;
  269. __IO uint32_t PC;
  270. __IO uint32_t MCR;
  271. __IO uint32_t MR0;
  272. __IO uint32_t MR1;
  273. __IO uint32_t MR2;
  274. __IO uint32_t MR3;
  275. __IO uint32_t CCR;
  276. __I uint32_t CR0;
  277. __I uint32_t CR1;
  278. uint32_t RESERVED0[2];
  279. __IO uint32_t EMR;
  280. uint32_t RESERVED1[12];
  281. __IO uint32_t CTCR;
  282. } LPC_TIM_TypeDef;
  283. /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
  284. /** @brief Pulse-Width Modulation (PWM) register structure definition */
  285. typedef struct
  286. {
  287. __IO uint32_t IR;
  288. __IO uint32_t TCR;
  289. __IO uint32_t TC;
  290. __IO uint32_t PR;
  291. __IO uint32_t PC;
  292. __IO uint32_t MCR;
  293. __IO uint32_t MR0;
  294. __IO uint32_t MR1;
  295. __IO uint32_t MR2;
  296. __IO uint32_t MR3;
  297. __IO uint32_t CCR;
  298. __I uint32_t CR0;
  299. __I uint32_t CR1;
  300. __I uint32_t CR2;
  301. __I uint32_t CR3;
  302. uint32_t RESERVED0;
  303. __IO uint32_t MR4;
  304. __IO uint32_t MR5;
  305. __IO uint32_t MR6;
  306. __IO uint32_t PCR;
  307. __IO uint32_t LER;
  308. uint32_t RESERVED1[7];
  309. __IO uint32_t CTCR;
  310. } LPC_PWM_TypeDef;
  311. /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
  312. /** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
  313. typedef struct
  314. {
  315. union {
  316. __I uint8_t RBR;
  317. __O uint8_t THR;
  318. __IO uint8_t DLL;
  319. uint32_t RESERVED0;
  320. };
  321. union {
  322. __IO uint8_t DLM;
  323. __IO uint32_t IER;
  324. };
  325. union {
  326. __I uint32_t IIR;
  327. __O uint8_t FCR;
  328. };
  329. __IO uint8_t LCR;
  330. uint8_t RESERVED1[7];
  331. __I uint8_t LSR;
  332. uint8_t RESERVED2[7];
  333. __IO uint8_t SCR;
  334. uint8_t RESERVED3[3];
  335. __IO uint32_t ACR;
  336. __IO uint8_t ICR;
  337. uint8_t RESERVED4[3];
  338. __IO uint8_t FDR;
  339. uint8_t RESERVED5[7];
  340. __IO uint8_t TER;
  341. uint8_t RESERVED6[39];
  342. __I uint8_t FIFOLVL;
  343. } LPC_UART_TypeDef;
  344. /** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
  345. typedef struct
  346. {
  347. union {
  348. __I uint8_t RBR;
  349. __O uint8_t THR;
  350. __IO uint8_t DLL;
  351. uint32_t RESERVED0;
  352. };
  353. union {
  354. __IO uint8_t DLM;
  355. __IO uint32_t IER;
  356. };
  357. union {
  358. __I uint32_t IIR;
  359. __O uint8_t FCR;
  360. };
  361. __IO uint8_t LCR;
  362. uint8_t RESERVED1[7];
  363. __I uint8_t LSR;
  364. uint8_t RESERVED2[7];
  365. __IO uint8_t SCR;
  366. uint8_t RESERVED3[3];
  367. __IO uint32_t ACR;
  368. __IO uint8_t ICR;
  369. uint8_t RESERVED4[3];
  370. __IO uint8_t FDR;
  371. uint8_t RESERVED5[7];
  372. __IO uint8_t TER;
  373. uint8_t RESERVED6[39];
  374. __I uint8_t FIFOLVL;
  375. } LPC_UART0_TypeDef;
  376. /** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
  377. typedef struct
  378. {
  379. union {
  380. __I uint8_t RBR;
  381. __O uint8_t THR;
  382. __IO uint8_t DLL;
  383. uint32_t RESERVED0;
  384. };
  385. union {
  386. __IO uint8_t DLM;
  387. __IO uint32_t IER;
  388. };
  389. union {
  390. __I uint32_t IIR;
  391. __O uint8_t FCR;
  392. };
  393. __IO uint8_t LCR;
  394. uint8_t RESERVED1[3];
  395. __IO uint8_t MCR;
  396. uint8_t RESERVED2[3];
  397. __I uint8_t LSR;
  398. uint8_t RESERVED3[3];
  399. __I uint8_t MSR;
  400. uint8_t RESERVED4[3];
  401. __IO uint8_t SCR;
  402. uint8_t RESERVED5[3];
  403. __IO uint32_t ACR;
  404. uint32_t RESERVED6;
  405. __IO uint32_t FDR;
  406. uint32_t RESERVED7;
  407. __IO uint8_t TER;
  408. uint8_t RESERVED8[27];
  409. __IO uint8_t RS485CTRL;
  410. uint8_t RESERVED9[3];
  411. __IO uint8_t ADRMATCH;
  412. uint8_t RESERVED10[3];
  413. __IO uint8_t RS485DLY;
  414. uint8_t RESERVED11[3];
  415. __I uint8_t FIFOLVL;
  416. } LPC_UART1_TypeDef;
  417. /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
  418. /** @brief Serial Peripheral Interface (SPI) register structure definition */
  419. typedef struct
  420. {
  421. __IO uint32_t SPCR;
  422. __I uint32_t SPSR;
  423. __IO uint32_t SPDR;
  424. __IO uint32_t SPCCR;
  425. uint32_t RESERVED0[3];
  426. __IO uint32_t SPINT;
  427. } LPC_SPI_TypeDef;
  428. /*------------- Synchronous Serial Communication (SSP) -----------------------*/
  429. /** @brief Synchronous Serial Communication (SSP) register structure definition */
  430. typedef struct
  431. {
  432. __IO uint32_t CR0;
  433. __IO uint32_t CR1;
  434. __IO uint32_t DR;
  435. __I uint32_t SR;
  436. __IO uint32_t CPSR;
  437. __IO uint32_t IMSC;
  438. __IO uint32_t RIS;
  439. __IO uint32_t MIS;
  440. __IO uint32_t ICR;
  441. __IO uint32_t DMACR;
  442. } LPC_SSP_TypeDef;
  443. /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
  444. /** @brief Inter-Integrated Circuit (I2C) register structure definition */
  445. typedef struct
  446. {
  447. __IO uint32_t I2CONSET;
  448. __I uint32_t I2STAT;
  449. __IO uint32_t I2DAT;
  450. __IO uint32_t I2ADR0;
  451. __IO uint32_t I2SCLH;
  452. __IO uint32_t I2SCLL;
  453. __O uint32_t I2CONCLR;
  454. __IO uint32_t MMCTRL;
  455. __IO uint32_t I2ADR1;
  456. __IO uint32_t I2ADR2;
  457. __IO uint32_t I2ADR3;
  458. __I uint32_t I2DATA_BUFFER;
  459. __IO uint32_t I2MASK0;
  460. __IO uint32_t I2MASK1;
  461. __IO uint32_t I2MASK2;
  462. __IO uint32_t I2MASK3;
  463. } LPC_I2C_TypeDef;
  464. /*------------- Inter IC Sound (I2S) -----------------------------------------*/
  465. /** @brief Inter IC Sound (I2S) register structure definition */
  466. typedef struct
  467. {
  468. __IO uint32_t I2SDAO;
  469. __IO uint32_t I2SDAI;
  470. __O uint32_t I2STXFIFO;
  471. __I uint32_t I2SRXFIFO;
  472. __I uint32_t I2SSTATE;
  473. __IO uint32_t I2SDMA1;
  474. __IO uint32_t I2SDMA2;
  475. __IO uint32_t I2SIRQ;
  476. __IO uint32_t I2STXRATE;
  477. __IO uint32_t I2SRXRATE;
  478. __IO uint32_t I2STXBITRATE;
  479. __IO uint32_t I2SRXBITRATE;
  480. __IO uint32_t I2STXMODE;
  481. __IO uint32_t I2SRXMODE;
  482. } LPC_I2S_TypeDef;
  483. /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
  484. /** @brief Repetitive Interrupt Timer (RIT) register structure definition */
  485. typedef struct
  486. {
  487. __IO uint32_t RICOMPVAL;
  488. __IO uint32_t RIMASK;
  489. __IO uint8_t RICTRL;
  490. uint8_t RESERVED0[3];
  491. __IO uint32_t RICOUNTER;
  492. } LPC_RIT_TypeDef;
  493. /*------------- Real-Time Clock (RTC) ----------------------------------------*/
  494. /** @brief Real-Time Clock (RTC) register structure definition */
  495. typedef struct
  496. {
  497. __IO uint8_t ILR;
  498. uint8_t RESERVED0[7];
  499. __IO uint8_t CCR;
  500. uint8_t RESERVED1[3];
  501. __IO uint8_t CIIR;
  502. uint8_t RESERVED2[3];
  503. __IO uint8_t AMR;
  504. uint8_t RESERVED3[3];
  505. __I uint32_t CTIME0;
  506. __I uint32_t CTIME1;
  507. __I uint32_t CTIME2;
  508. __IO uint8_t SEC;
  509. uint8_t RESERVED4[3];
  510. __IO uint8_t MIN;
  511. uint8_t RESERVED5[3];
  512. __IO uint8_t HOUR;
  513. uint8_t RESERVED6[3];
  514. __IO uint8_t DOM;
  515. uint8_t RESERVED7[3];
  516. __IO uint8_t DOW;
  517. uint8_t RESERVED8[3];
  518. __IO uint16_t DOY;
  519. uint16_t RESERVED9;
  520. __IO uint8_t MONTH;
  521. uint8_t RESERVED10[3];
  522. __IO uint16_t YEAR;
  523. uint16_t RESERVED11;
  524. __IO uint32_t CALIBRATION;
  525. __IO uint32_t GPREG0;
  526. __IO uint32_t GPREG1;
  527. __IO uint32_t GPREG2;
  528. __IO uint32_t GPREG3;
  529. __IO uint32_t GPREG4;
  530. __IO uint8_t RTC_AUXEN;
  531. uint8_t RESERVED12[3];
  532. __IO uint8_t RTC_AUX;
  533. uint8_t RESERVED13[3];
  534. __IO uint8_t ALSEC;
  535. uint8_t RESERVED14[3];
  536. __IO uint8_t ALMIN;
  537. uint8_t RESERVED15[3];
  538. __IO uint8_t ALHOUR;
  539. uint8_t RESERVED16[3];
  540. __IO uint8_t ALDOM;
  541. uint8_t RESERVED17[3];
  542. __IO uint8_t ALDOW;
  543. uint8_t RESERVED18[3];
  544. __IO uint16_t ALDOY;
  545. uint16_t RESERVED19;
  546. __IO uint8_t ALMON;
  547. uint8_t RESERVED20[3];
  548. __IO uint16_t ALYEAR;
  549. uint16_t RESERVED21;
  550. } LPC_RTC_TypeDef;
  551. /*------------- Watchdog Timer (WDT) -----------------------------------------*/
  552. /** @brief Watchdog Timer (WDT) register structure definition */
  553. typedef struct
  554. {
  555. __IO uint8_t WDMOD;
  556. uint8_t RESERVED0[3];
  557. __IO uint32_t WDTC;
  558. __O uint8_t WDFEED;
  559. uint8_t RESERVED1[3];
  560. __I uint32_t WDTV;
  561. __IO uint32_t WDCLKSEL;
  562. } LPC_WDT_TypeDef;
  563. /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
  564. /** @brief Analog-to-Digital Converter (ADC) register structure definition */
  565. typedef struct
  566. {
  567. __IO uint32_t ADCR;
  568. __IO uint32_t ADGDR;
  569. uint32_t RESERVED0;
  570. __IO uint32_t ADINTEN;
  571. __I uint32_t ADDR0;
  572. __I uint32_t ADDR1;
  573. __I uint32_t ADDR2;
  574. __I uint32_t ADDR3;
  575. __I uint32_t ADDR4;
  576. __I uint32_t ADDR5;
  577. __I uint32_t ADDR6;
  578. __I uint32_t ADDR7;
  579. __I uint32_t ADSTAT;
  580. __IO uint32_t ADTRM;
  581. } LPC_ADC_TypeDef;
  582. /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
  583. /** @brief Digital-to-Analog Converter (DAC) register structure definition */
  584. typedef struct
  585. {
  586. __IO uint32_t DACR;
  587. __IO uint32_t DACCTRL;
  588. __IO uint16_t DACCNTVAL;
  589. } LPC_DAC_TypeDef;
  590. /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
  591. /** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
  592. typedef struct
  593. {
  594. __I uint32_t MCCON;
  595. __O uint32_t MCCON_SET;
  596. __O uint32_t MCCON_CLR;
  597. __I uint32_t MCCAPCON;
  598. __O uint32_t MCCAPCON_SET;
  599. __O uint32_t MCCAPCON_CLR;
  600. __IO uint32_t MCTIM0;
  601. __IO uint32_t MCTIM1;
  602. __IO uint32_t MCTIM2;
  603. __IO uint32_t MCPER0;
  604. __IO uint32_t MCPER1;
  605. __IO uint32_t MCPER2;
  606. __IO uint32_t MCPW0;
  607. __IO uint32_t MCPW1;
  608. __IO uint32_t MCPW2;
  609. __IO uint32_t MCDEADTIME;
  610. __IO uint32_t MCCCP;
  611. __IO uint32_t MCCR0;
  612. __IO uint32_t MCCR1;
  613. __IO uint32_t MCCR2;
  614. __I uint32_t MCINTEN;
  615. __O uint32_t MCINTEN_SET;
  616. __O uint32_t MCINTEN_CLR;
  617. __I uint32_t MCCNTCON;
  618. __O uint32_t MCCNTCON_SET;
  619. __O uint32_t MCCNTCON_CLR;
  620. __I uint32_t MCINTFLAG;
  621. __O uint32_t MCINTFLAG_SET;
  622. __O uint32_t MCINTFLAG_CLR;
  623. __O uint32_t MCCAP_CLR;
  624. } LPC_MCPWM_TypeDef;
  625. /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
  626. /** @brief Quadrature Encoder Interface (QEI) register structure definition */
  627. typedef struct
  628. {
  629. __O uint32_t QEICON;
  630. __I uint32_t QEISTAT;
  631. __IO uint32_t QEICONF;
  632. __I uint32_t QEIPOS;
  633. __IO uint32_t QEIMAXPOS;
  634. __IO uint32_t CMPOS0;
  635. __IO uint32_t CMPOS1;
  636. __IO uint32_t CMPOS2;
  637. __I uint32_t INXCNT;
  638. __IO uint32_t INXCMP;
  639. __IO uint32_t QEILOAD;
  640. __I uint32_t QEITIME;
  641. __I uint32_t QEIVEL;
  642. __I uint32_t QEICAP;
  643. __IO uint32_t VELCOMP;
  644. __IO uint32_t FILTER;
  645. uint32_t RESERVED0[998];
  646. __O uint32_t QEIIEC;
  647. __O uint32_t QEIIES;
  648. __I uint32_t QEIINTSTAT;
  649. __I uint32_t QEIIE;
  650. __O uint32_t QEICLR;
  651. __O uint32_t QEISET;
  652. } LPC_QEI_TypeDef;
  653. /*------------- Controller Area Network (CAN) --------------------------------*/
  654. /** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
  655. typedef struct
  656. {
  657. __IO uint32_t mask[512]; /* ID Masks */
  658. } LPC_CANAF_RAM_TypeDef;
  659. /** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
  660. typedef struct /* Acceptance Filter Registers */
  661. {
  662. __IO uint32_t AFMR;
  663. __IO uint32_t SFF_sa;
  664. __IO uint32_t SFF_GRP_sa;
  665. __IO uint32_t EFF_sa;
  666. __IO uint32_t EFF_GRP_sa;
  667. __IO uint32_t ENDofTable;
  668. __I uint32_t LUTerrAd;
  669. __I uint32_t LUTerr;
  670. __IO uint32_t FCANIE;
  671. __IO uint32_t FCANIC0;
  672. __IO uint32_t FCANIC1;
  673. } LPC_CANAF_TypeDef;
  674. /** @brief Controller Area Network Central (CANCR) register structure definition */
  675. typedef struct /* Central Registers */
  676. {
  677. __I uint32_t CANTxSR;
  678. __I uint32_t CANRxSR;
  679. __I uint32_t CANMSR;
  680. } LPC_CANCR_TypeDef;
  681. /** @brief Controller Area Network Controller (CAN) register structure definition */
  682. typedef struct /* Controller Registers */
  683. {
  684. __IO uint32_t MOD;
  685. __O uint32_t CMR;
  686. __IO uint32_t GSR;
  687. __I uint32_t ICR;
  688. __IO uint32_t IER;
  689. __IO uint32_t BTR;
  690. __IO uint32_t EWL;
  691. __I uint32_t SR;
  692. __IO uint32_t RFS;
  693. __IO uint32_t RID;
  694. __IO uint32_t RDA;
  695. __IO uint32_t RDB;
  696. __IO uint32_t TFI1;
  697. __IO uint32_t TID1;
  698. __IO uint32_t TDA1;
  699. __IO uint32_t TDB1;
  700. __IO uint32_t TFI2;
  701. __IO uint32_t TID2;
  702. __IO uint32_t TDA2;
  703. __IO uint32_t TDB2;
  704. __IO uint32_t TFI3;
  705. __IO uint32_t TID3;
  706. __IO uint32_t TDA3;
  707. __IO uint32_t TDB3;
  708. } LPC_CAN_TypeDef;
  709. /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
  710. /** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
  711. typedef struct /* Common Registers */
  712. {
  713. __I uint32_t DMACIntStat;
  714. __I uint32_t DMACIntTCStat;
  715. __O uint32_t DMACIntTCClear;
  716. __I uint32_t DMACIntErrStat;
  717. __O uint32_t DMACIntErrClr;
  718. __I uint32_t DMACRawIntTCStat;
  719. __I uint32_t DMACRawIntErrStat;
  720. __I uint32_t DMACEnbldChns;
  721. __IO uint32_t DMACSoftBReq;
  722. __IO uint32_t DMACSoftSReq;
  723. __IO uint32_t DMACSoftLBReq;
  724. __IO uint32_t DMACSoftLSReq;
  725. __IO uint32_t DMACConfig;
  726. __IO uint32_t DMACSync;
  727. } LPC_GPDMA_TypeDef;
  728. /** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
  729. typedef struct /* Channel Registers */
  730. {
  731. __IO uint32_t DMACCSrcAddr;
  732. __IO uint32_t DMACCDestAddr;
  733. __IO uint32_t DMACCLLI;
  734. __IO uint32_t DMACCControl;
  735. __IO uint32_t DMACCConfig;
  736. } LPC_GPDMACH_TypeDef;
  737. /*------------- Universal Serial Bus (USB) -----------------------------------*/
  738. /** @brief Universal Serial Bus (USB) register structure definition */
  739. typedef struct
  740. {
  741. __I uint32_t HcRevision; /* USB Host Registers */
  742. __IO uint32_t HcControl;
  743. __IO uint32_t HcCommandStatus;
  744. __IO uint32_t HcInterruptStatus;
  745. __IO uint32_t HcInterruptEnable;
  746. __IO uint32_t HcInterruptDisable;
  747. __IO uint32_t HcHCCA;
  748. __I uint32_t HcPeriodCurrentED;
  749. __IO uint32_t HcControlHeadED;
  750. __IO uint32_t HcControlCurrentED;
  751. __IO uint32_t HcBulkHeadED;
  752. __IO uint32_t HcBulkCurrentED;
  753. __I uint32_t HcDoneHead;
  754. __IO uint32_t HcFmInterval;
  755. __I uint32_t HcFmRemaining;
  756. __I uint32_t HcFmNumber;
  757. __IO uint32_t HcPeriodicStart;
  758. __IO uint32_t HcLSTreshold;
  759. __IO uint32_t HcRhDescriptorA;
  760. __IO uint32_t HcRhDescriptorB;
  761. __IO uint32_t HcRhStatus;
  762. __IO uint32_t HcRhPortStatus1;
  763. __IO uint32_t HcRhPortStatus2;
  764. uint32_t RESERVED0[40];
  765. __I uint32_t Module_ID;
  766. __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
  767. __IO uint32_t OTGIntEn;
  768. __O uint32_t OTGIntSet;
  769. __O uint32_t OTGIntClr;
  770. __IO uint32_t OTGStCtrl;
  771. __IO uint32_t OTGTmr;
  772. uint32_t RESERVED1[58];
  773. __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
  774. __IO uint32_t USBDevIntEn;
  775. __O uint32_t USBDevIntClr;
  776. __O uint32_t USBDevIntSet;
  777. __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
  778. __I uint32_t USBCmdData;
  779. __I uint32_t USBRxData; /* USB Device Transfer Registers */
  780. __O uint32_t USBTxData;
  781. __I uint32_t USBRxPLen;
  782. __O uint32_t USBTxPLen;
  783. __IO uint32_t USBCtrl;
  784. __O uint32_t USBDevIntPri;
  785. __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
  786. __IO uint32_t USBEpIntEn;
  787. __O uint32_t USBEpIntClr;
  788. __O uint32_t USBEpIntSet;
  789. __O uint32_t USBEpIntPri;
  790. __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
  791. __O uint32_t USBEpInd;
  792. __IO uint32_t USBMaxPSize;
  793. __I uint32_t USBDMARSt; /* USB Device DMA Registers */
  794. __O uint32_t USBDMARClr;
  795. __O uint32_t USBDMARSet;
  796. uint32_t RESERVED2[9];
  797. __IO uint32_t USBUDCAH;
  798. __I uint32_t USBEpDMASt;
  799. __O uint32_t USBEpDMAEn;
  800. __O uint32_t USBEpDMADis;
  801. __I uint32_t USBDMAIntSt;
  802. __IO uint32_t USBDMAIntEn;
  803. uint32_t RESERVED3[2];
  804. __I uint32_t USBEoTIntSt;
  805. __O uint32_t USBEoTIntClr;
  806. __O uint32_t USBEoTIntSet;
  807. __I uint32_t USBNDDRIntSt;
  808. __O uint32_t USBNDDRIntClr;
  809. __O uint32_t USBNDDRIntSet;
  810. __I uint32_t USBSysErrIntSt;
  811. __O uint32_t USBSysErrIntClr;
  812. __O uint32_t USBSysErrIntSet;
  813. uint32_t RESERVED4[15];
  814. union {
  815. __I uint32_t I2C_RX; /* USB OTG I2C Registers */
  816. __O uint32_t I2C_TX;
  817. };
  818. __I uint32_t I2C_STS;
  819. __IO uint32_t I2C_CTL;
  820. __IO uint32_t I2C_CLKHI;
  821. __O uint32_t I2C_CLKLO;
  822. uint32_t RESERVED5[824];
  823. union {
  824. __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
  825. __IO uint32_t OTGClkCtrl;
  826. };
  827. union {
  828. __I uint32_t USBClkSt;
  829. __I uint32_t OTGClkSt;
  830. };
  831. } LPC_USB_TypeDef;
  832. /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
  833. /** @brief Ethernet Media Access Controller (EMAC) register structure definition */
  834. typedef struct
  835. {
  836. __IO uint32_t MAC1; /* MAC Registers */
  837. __IO uint32_t MAC2;
  838. __IO uint32_t IPGT;
  839. __IO uint32_t IPGR;
  840. __IO uint32_t CLRT;
  841. __IO uint32_t MAXF;
  842. __IO uint32_t SUPP;
  843. __IO uint32_t TEST;
  844. __IO uint32_t MCFG;
  845. __IO uint32_t MCMD;
  846. __IO uint32_t MADR;
  847. __O uint32_t MWTD;
  848. __I uint32_t MRDD;
  849. __I uint32_t MIND;
  850. uint32_t RESERVED0[2];
  851. __IO uint32_t SA0;
  852. __IO uint32_t SA1;
  853. __IO uint32_t SA2;
  854. uint32_t RESERVED1[45];
  855. __IO uint32_t Command; /* Control Registers */
  856. __I uint32_t Status;
  857. __IO uint32_t RxDescriptor;
  858. __IO uint32_t RxStatus;
  859. __IO uint32_t RxDescriptorNumber;
  860. __I uint32_t RxProduceIndex;
  861. __IO uint32_t RxConsumeIndex;
  862. __IO uint32_t TxDescriptor;
  863. __IO uint32_t TxStatus;
  864. __IO uint32_t TxDescriptorNumber;
  865. __IO uint32_t TxProduceIndex;
  866. __I uint32_t TxConsumeIndex;
  867. uint32_t RESERVED2[10];
  868. __I uint32_t TSV0;
  869. __I uint32_t TSV1;
  870. __I uint32_t RSV;
  871. uint32_t RESERVED3[3];
  872. __IO uint32_t FlowControlCounter;
  873. __I uint32_t FlowControlStatus;
  874. uint32_t RESERVED4[34];
  875. __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
  876. __IO uint32_t RxFilterWoLStatus;
  877. __IO uint32_t RxFilterWoLClear;
  878. uint32_t RESERVED5;
  879. __IO uint32_t HashFilterL;
  880. __IO uint32_t HashFilterH;
  881. uint32_t RESERVED6[882];
  882. __I uint32_t IntStatus; /* Module Control Registers */
  883. __IO uint32_t IntEnable;
  884. __O uint32_t IntClear;
  885. __O uint32_t IntSet;
  886. uint32_t RESERVED7;
  887. __IO uint32_t PowerDown;
  888. uint32_t RESERVED8;
  889. __IO uint32_t Module_ID;
  890. } LPC_EMAC_TypeDef;
  891. #if defined ( __CC_ARM )
  892. #pragma no_anon_unions
  893. #endif
  894. /******************************************************************************/
  895. /* Peripheral memory map */
  896. /******************************************************************************/
  897. /* Base addresses */
  898. #define LPC_FLASH_BASE (0x00000000UL)
  899. #define LPC_RAM_BASE (0x10000000UL)
  900. #ifdef __LPC17XX_REV00
  901. #define LPC_AHBRAM0_BASE (0x20000000UL)
  902. #define LPC_AHBRAM1_BASE (0x20004000UL)
  903. #else
  904. #define LPC_AHBRAM0_BASE (0x2007C000UL)
  905. #define LPC_AHBRAM1_BASE (0x20080000UL)
  906. #endif
  907. #define LPC_GPIO_BASE (0x2009C000UL)
  908. #define LPC_APB0_BASE (0x40000000UL)
  909. #define LPC_APB1_BASE (0x40080000UL)
  910. #define LPC_AHB_BASE (0x50000000UL)
  911. #define LPC_CM3_BASE (0xE0000000UL)
  912. /* APB0 peripherals */
  913. #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
  914. #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
  915. #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
  916. #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
  917. #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
  918. #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
  919. #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
  920. #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
  921. #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
  922. #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
  923. #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
  924. #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
  925. #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
  926. #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
  927. #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
  928. #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
  929. #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
  930. #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
  931. #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
  932. /* APB1 peripherals */
  933. #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
  934. #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
  935. #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
  936. #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
  937. #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
  938. #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
  939. #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
  940. #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
  941. #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
  942. #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
  943. #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
  944. #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
  945. /* AHB peripherals */
  946. #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
  947. #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
  948. #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
  949. #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
  950. #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
  951. #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
  952. #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
  953. #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
  954. #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
  955. #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
  956. #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
  957. /* GPIOs */
  958. #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
  959. #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
  960. #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
  961. #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
  962. #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
  963. /******************************************************************************/
  964. /* Peripheral declaration */
  965. /******************************************************************************/
  966. #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
  967. #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
  968. #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
  969. #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
  970. #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
  971. #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
  972. #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
  973. #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
  974. #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
  975. #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
  976. #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
  977. #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
  978. #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
  979. #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
  980. #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
  981. #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
  982. #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
  983. #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
  984. #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
  985. #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
  986. #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
  987. #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
  988. #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
  989. #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
  990. #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
  991. #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
  992. #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
  993. #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
  994. #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
  995. #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
  996. #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
  997. #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
  998. #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
  999. #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
  1000. #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
  1001. #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
  1002. #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
  1003. #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
  1004. #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
  1005. #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
  1006. #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
  1007. #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
  1008. #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
  1009. #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
  1010. #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
  1011. #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
  1012. #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
  1013. /**
  1014. * @}
  1015. */
  1016. #endif // __LPC17xx_H__