My Marlin configs for Fabrikator Mini and CTC i3 Pro B
Vous ne pouvez pas sélectionner plus de 25 sujets Les noms de sujets doivent commencer par une lettre ou un nombre, peuvent contenir des tirets ('-') et peuvent comporter jusqu'à 35 caractères.

lpc17xx_spi.h 12KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328
  1. /**********************************************************************
  2. * $Id$ lpc17xx_spi.h 2010-05-21
  3. *//**
  4. * @file lpc17xx_spi.h
  5. * @brief Contains all macro definitions and function prototypes
  6. * support for SPI firmware library on LPC17xx
  7. * @version 2.0
  8. * @date 21. May. 2010
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2010, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @defgroup SPI SPI (Serial Peripheral Interface)
  34. * @ingroup LPC1700CMSIS_FwLib_Drivers
  35. * @{
  36. */
  37. #ifndef LPC17XX_SPI_H_
  38. #define LPC17XX_SPI_H_
  39. /* Includes ------------------------------------------------------------------- */
  40. #include "LPC17xx.h"
  41. #include "lpc_types.h"
  42. #ifdef __cplusplus
  43. extern "C"
  44. {
  45. #endif
  46. /* Public Macros -------------------------------------------------------------- */
  47. /** @defgroup SPI_Public_Macros SPI Public Macros
  48. * @{
  49. */
  50. /*********************************************************************//**
  51. * SPI configuration parameter defines
  52. **********************************************************************/
  53. /** Clock phase control bit */
  54. #define SPI_CPHA_FIRST ((uint32_t)(0))
  55. #define SPI_CPHA_SECOND ((uint32_t)(1<<3))
  56. /** Clock polarity control bit */
  57. #define SPI_CPOL_HI ((uint32_t)(0))
  58. #define SPI_CPOL_LO ((uint32_t)(1<<4))
  59. /** SPI master mode enable */
  60. #define SPI_SLAVE_MODE ((uint32_t)(0))
  61. #define SPI_MASTER_MODE ((uint32_t)(1<<5))
  62. /** LSB enable bit */
  63. #define SPI_DATA_MSB_FIRST ((uint32_t)(0))
  64. #define SPI_DATA_LSB_FIRST ((uint32_t)(1<<6))
  65. /** SPI data bit number defines */
  66. #define SPI_DATABIT_16 SPI_SPCR_BITS(0) /*!< Databit number = 16 */
  67. #define SPI_DATABIT_8 SPI_SPCR_BITS(0x08) /*!< Databit number = 8 */
  68. #define SPI_DATABIT_9 SPI_SPCR_BITS(0x09) /*!< Databit number = 9 */
  69. #define SPI_DATABIT_10 SPI_SPCR_BITS(0x0A) /*!< Databit number = 10 */
  70. #define SPI_DATABIT_11 SPI_SPCR_BITS(0x0B) /*!< Databit number = 11 */
  71. #define SPI_DATABIT_12 SPI_SPCR_BITS(0x0C) /*!< Databit number = 12 */
  72. #define SPI_DATABIT_13 SPI_SPCR_BITS(0x0D) /*!< Databit number = 13 */
  73. #define SPI_DATABIT_14 SPI_SPCR_BITS(0x0E) /*!< Databit number = 14 */
  74. #define SPI_DATABIT_15 SPI_SPCR_BITS(0x0F) /*!< Databit number = 15 */
  75. /*********************************************************************//**
  76. * SPI Status Flag defines
  77. **********************************************************************/
  78. /** Slave abort */
  79. #define SPI_STAT_ABRT SPI_SPSR_ABRT
  80. /** Mode fault */
  81. #define SPI_STAT_MODF SPI_SPSR_MODF
  82. /** Read overrun */
  83. #define SPI_STAT_ROVR SPI_SPSR_ROVR
  84. /** Write collision */
  85. #define SPI_STAT_WCOL SPI_SPSR_WCOL
  86. /** SPI transfer complete flag */
  87. #define SPI_STAT_SPIF SPI_SPSR_SPIF
  88. /* SPI Status Implementation definitions */
  89. #define SPI_STAT_DONE (1UL<<8) /**< Done */
  90. #define SPI_STAT_ERROR (1UL<<9) /**< Error */
  91. /**
  92. * @}
  93. */
  94. /* Private Macros ------------------------------------------------------------- */
  95. /** @defgroup SPI_Private_Macros SPI Private Macros
  96. * @{
  97. */
  98. /* --------------------- BIT DEFINITIONS -------------------------------------- */
  99. /*********************************************************************//**
  100. * Macro defines for SPI Control Register
  101. **********************************************************************/
  102. /** Bit enable, the SPI controller sends and receives the number
  103. * of bits selected by bits 11:8 */
  104. #define SPI_SPCR_BIT_EN ((uint32_t)(1<<2))
  105. /** Clock phase control bit */
  106. #define SPI_SPCR_CPHA_SECOND ((uint32_t)(1<<3))
  107. /** Clock polarity control bit */
  108. #define SPI_SPCR_CPOL_LOW ((uint32_t)(1<<4))
  109. /** SPI master mode enable */
  110. #define SPI_SPCR_MSTR ((uint32_t)(1<<5))
  111. /** LSB enable bit */
  112. #define SPI_SPCR_LSBF ((uint32_t)(1<<6))
  113. /** SPI interrupt enable bit */
  114. #define SPI_SPCR_SPIE ((uint32_t)(1<<7))
  115. /** When bit 2 of this register is 1, this field controls the
  116. number of bits per transfer */
  117. #define SPI_SPCR_BITS(n) ((n==0) ? ((uint32_t)0) : ((uint32_t)((n&0x0F)<<8)))
  118. /** SPI Control bit mask */
  119. #define SPI_SPCR_BITMASK ((uint32_t)(0xFFC))
  120. /*********************************************************************//**
  121. * Macro defines for SPI Status Register
  122. **********************************************************************/
  123. /** Slave abort */
  124. #define SPI_SPSR_ABRT ((uint32_t)(1<<3))
  125. /** Mode fault */
  126. #define SPI_SPSR_MODF ((uint32_t)(1<<4))
  127. /** Read overrun */
  128. #define SPI_SPSR_ROVR ((uint32_t)(1<<5))
  129. /** Write collision */
  130. #define SPI_SPSR_WCOL ((uint32_t)(1<<6))
  131. /** SPI transfer complete flag */
  132. #define SPI_SPSR_SPIF ((uint32_t)(1<<7))
  133. /** SPI Status bit mask */
  134. #define SPI_SPSR_BITMASK ((uint32_t)(0xF8))
  135. /*********************************************************************//**
  136. * Macro defines for SPI Data Register
  137. **********************************************************************/
  138. /** SPI Data low bit-mask */
  139. #define SPI_SPDR_LO_MASK ((uint32_t)(0xFF))
  140. /** SPI Data high bit-mask */
  141. #define SPI_SPDR_HI_MASK ((uint32_t)(0xFF00))
  142. /** SPI Data bit-mask */
  143. #define SPI_SPDR_BITMASK ((uint32_t)(0xFFFF))
  144. /*********************************************************************//**
  145. * Macro defines for SPI Clock Counter Register
  146. **********************************************************************/
  147. /** SPI clock counter setting */
  148. #define SPI_SPCCR_COUNTER(n) ((uint32_t)(n&0xFF))
  149. /** SPI clock counter bit-mask */
  150. #define SPI_SPCCR_BITMASK ((uint32_t)(0xFF))
  151. /***********************************************************************
  152. * Macro defines for SPI Test Control Register
  153. **********************************************************************/
  154. /** SPI Test bit */
  155. #define SPI_SPTCR_TEST_MASK ((uint32_t)(0xFE))
  156. /** SPI Test register bit mask */
  157. #define SPI_SPTCR_BITMASK ((uint32_t)(0xFE))
  158. /*********************************************************************//**
  159. * Macro defines for SPI Test Status Register
  160. **********************************************************************/
  161. /** Slave abort */
  162. #define SPI_SPTSR_ABRT ((uint32_t)(1<<3))
  163. /** Mode fault */
  164. #define SPI_SPTSR_MODF ((uint32_t)(1<<4))
  165. /** Read overrun */
  166. #define SPI_SPTSR_ROVR ((uint32_t)(1<<5))
  167. /** Write collision */
  168. #define SPI_SPTSR_WCOL ((uint32_t)(1<<6))
  169. /** SPI transfer complete flag */
  170. #define SPI_SPTSR_SPIF ((uint32_t)(1<<7))
  171. /** SPI Status bit mask */
  172. #define SPI_SPTSR_MASKBIT ((uint32_t)(0xF8))
  173. /*********************************************************************//**
  174. * Macro defines for SPI Interrupt Register
  175. **********************************************************************/
  176. /** SPI interrupt flag */
  177. #define SPI_SPINT_INTFLAG ((uint32_t)(1<<0))
  178. /** SPI interrupt register bit mask */
  179. #define SPI_SPINT_BITMASK ((uint32_t)(0x01))
  180. /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
  181. /** Macro to determine if it is valid SPI port number */
  182. #define PARAM_SPIx(n) (((uint32_t *)n)==((uint32_t *)LPC_SPI))
  183. /** Macro check Clock phase control mode */
  184. #define PARAM_SPI_CPHA(n) ((n==SPI_CPHA_FIRST) || (n==SPI_CPHA_SECOND))
  185. /** Macro check Clock polarity control mode */
  186. #define PARAM_SPI_CPOL(n) ((n==SPI_CPOL_HI) || (n==SPI_CPOL_LO))
  187. /** Macro check master/slave mode */
  188. #define PARAM_SPI_MODE(n) ((n==SPI_SLAVE_MODE) || (n==SPI_MASTER_MODE))
  189. /** Macro check LSB/MSB mode */
  190. #define PARAM_SPI_DATA_ORDER(n) ((n==SPI_DATA_MSB_FIRST) || (n==SPI_DATA_LSB_FIRST))
  191. /** Macro check databit value */
  192. #define PARAM_SPI_DATABIT(n) ((n==SPI_DATABIT_16) || (n==SPI_DATABIT_8) \
  193. || (n==SPI_DATABIT_9) || (n==SPI_DATABIT_10) \
  194. || (n==SPI_DATABIT_11) || (n==SPI_DATABIT_12) \
  195. || (n==SPI_DATABIT_13) || (n==SPI_DATABIT_14) \
  196. || (n==SPI_DATABIT_15))
  197. /** Macro check status flag */
  198. #define PARAM_SPI_STAT(n) ((n==SPI_STAT_ABRT) || (n==SPI_STAT_MODF) \
  199. || (n==SPI_STAT_ROVR) || (n==SPI_STAT_WCOL) \
  200. || (n==SPI_STAT_SPIF))
  201. /**
  202. * @}
  203. */
  204. /* Public Types --------------------------------------------------------------- */
  205. /** @defgroup SPI_Public_Types SPI Public Types
  206. * @{
  207. */
  208. /** @brief SPI configuration structure */
  209. typedef struct {
  210. uint32_t Databit; /** Databit number, should be SPI_DATABIT_x,
  211. where x is in range from 8 - 16 */
  212. uint32_t CPHA; /** Clock phase, should be:
  213. - SPI_CPHA_FIRST: first clock edge
  214. - SPI_CPHA_SECOND: second clock edge */
  215. uint32_t CPOL; /** Clock polarity, should be:
  216. - SPI_CPOL_HI: high level
  217. - SPI_CPOL_LO: low level */
  218. uint32_t Mode; /** SPI mode, should be:
  219. - SPI_MASTER_MODE: Master mode
  220. - SPI_SLAVE_MODE: Slave mode */
  221. uint32_t DataOrder; /** Data order, should be:
  222. - SPI_DATA_MSB_FIRST: MSB first
  223. - SPI_DATA_LSB_FIRST: LSB first */
  224. uint32_t ClockRate; /** Clock rate,in Hz, should not exceed
  225. (SPI peripheral clock)/8 */
  226. } SPI_CFG_Type;
  227. /**
  228. * @brief SPI Transfer Type definitions
  229. */
  230. typedef enum {
  231. SPI_TRANSFER_POLLING = 0, /**< Polling transfer */
  232. SPI_TRANSFER_INTERRUPT /**< Interrupt transfer */
  233. } SPI_TRANSFER_Type;
  234. /**
  235. * @brief SPI Data configuration structure definitions
  236. */
  237. typedef struct {
  238. void *tx_data; /**< Pointer to transmit data */
  239. void *rx_data; /**< Pointer to transmit data */
  240. uint32_t length; /**< Length of transfer data */
  241. uint32_t counter; /**< Data counter index */
  242. uint32_t status; /**< Current status of SPI activity */
  243. } SPI_DATA_SETUP_Type;
  244. /**
  245. * @}
  246. */
  247. /* Public Functions ----------------------------------------------------------- */
  248. /** @defgroup SPI_Public_Functions SPI Public Functions
  249. * @{
  250. */
  251. /* SPI Init/DeInit functions ---------*/
  252. void SPI_Init(LPC_SPI_TypeDef *SPIx, SPI_CFG_Type *SPI_ConfigStruct);
  253. void SPI_DeInit(LPC_SPI_TypeDef *SPIx);
  254. void SPI_SetClock (LPC_SPI_TypeDef *SPIx, uint32_t target_clock);
  255. void SPI_ConfigStructInit(SPI_CFG_Type *SPI_InitStruct);
  256. /* SPI transfer functions ------------*/
  257. void SPI_SendData(LPC_SPI_TypeDef *SPIx, uint16_t Data);
  258. uint16_t SPI_ReceiveData(LPC_SPI_TypeDef *SPIx);
  259. int32_t SPI_ReadWrite (LPC_SPI_TypeDef *SPIx, SPI_DATA_SETUP_Type *dataCfg, SPI_TRANSFER_Type xfType);
  260. /* SPI Interrupt functions ---------*/
  261. void SPI_IntCmd(LPC_SPI_TypeDef *SPIx, FunctionalState NewState);
  262. IntStatus SPI_GetIntStatus (LPC_SPI_TypeDef *SPIx);
  263. void SPI_ClearIntPending(LPC_SPI_TypeDef *SPIx);
  264. /* SPI get information functions-----*/
  265. uint8_t SPI_GetDataSize (LPC_SPI_TypeDef *SPIx);
  266. uint32_t SPI_GetStatus(LPC_SPI_TypeDef *SPIx);
  267. FlagStatus SPI_CheckStatus (uint32_t inputSPIStatus, uint8_t SPIStatus);
  268. /**
  269. * @}
  270. */
  271. #ifdef __cplusplus
  272. }
  273. #endif
  274. #endif /* LPC17XX_SPI_H_ */
  275. /**
  276. * @}
  277. */
  278. /* --------------------------------- End Of File ------------------------------ */