My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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  1. /**
  2. ******************************************************************************
  3. * @file startup_stm32f401xc.s
  4. * @author MCD Application Team
  5. * @version V2.4.2
  6. * @date 13-November-2015
  7. * @brief STM32F401xCxx Devices vector table for GCC based toolchains.
  8. * This module performs:
  9. * - Set the initial SP
  10. * - Set the initial PC == Reset_Handler,
  11. * - Set the vector table entries with the exceptions ISR address
  12. * - Branches to main in the C library (which eventually
  13. * calls main()).
  14. * After Reset the Cortex-M4 processor is in Thread mode,
  15. * priority is Privileged, and the Stack is set to Main.
  16. ******************************************************************************
  17. * @attention
  18. *
  19. * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
  20. *
  21. * Redistribution and use in source and binary forms, with or without modification,
  22. * are permitted provided that the following conditions are met:
  23. * 1. Redistributions of source code must retain the above copyright notice,
  24. * this list of conditions and the following disclaimer.
  25. * 2. Redistributions in binary form must reproduce the above copyright notice,
  26. * this list of conditions and the following disclaimer in the documentation
  27. * and/or other materials provided with the distribution.
  28. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  29. * may be used to endorse or promote products derived from this software
  30. * without specific prior written permission.
  31. *
  32. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  33. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  34. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  36. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  37. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  38. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  39. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  40. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  41. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *
  43. ******************************************************************************
  44. */
  45. .syntax unified
  46. .cpu cortex-m4
  47. .fpu softvfp
  48. .thumb
  49. /**
  50. * @brief This is the code that gets called when the processor first
  51. * starts execution following a reset event. Only the absolutely
  52. * necessary set is performed, after which the application
  53. * supplied main() routine is called.
  54. * @param None
  55. * @retval : None
  56. */
  57. .section .text.Reset_Handler
  58. .globl Reset_Handler
  59. .type Reset_Handler, %function
  60. Reset_Handler:
  61. /* Check for magic code at the end of SRAM to detemine whether to jump to DFU */
  62. ldr r0, =0x2000FFF0 // End of SRAM for your CPU
  63. ldr r1, =0xDEADBEEF
  64. ldr r2, [r0, #0]
  65. str r0, [r0, #0] // Invalidate
  66. cmp r2, r1
  67. beq Jump_To_DFU
  68. /* Original Reset_Handler code */
  69. ldr sp, =_estack /* set stack pointer */
  70. /* Copy the data segment initializers from flash to SRAM */
  71. movs r1, #0
  72. b LoopCopyDataInit
  73. CopyDataInit:
  74. ldr r3, =_sidata
  75. ldr r3, [r3, r1]
  76. str r3, [r0, r1]
  77. adds r1, r1, #4
  78. LoopCopyDataInit:
  79. ldr r0, =_sdata
  80. ldr r3, =_edata
  81. adds r2, r0, r1
  82. cmp r2, r3
  83. bcc CopyDataInit
  84. ldr r2, =_sbss
  85. b LoopFillZerobss
  86. /* Zero fill the bss segment. */
  87. FillZerobss:
  88. movs r3, #0
  89. str r3, [r2], #4
  90. LoopFillZerobss:
  91. ldr r3, = _ebss
  92. cmp r2, r3
  93. bcc FillZerobss
  94. /* Call the clock system intitialization function.*/
  95. bl SystemInit
  96. /* Call static constructors */
  97. bl __libc_init_array
  98. /* Call the application's entry point.*/
  99. bl main
  100. bx lr
  101. Jump_To_DFU:
  102. ldr r0, =0x40023844 // RCC_APB2ENR
  103. ldr r1, =0x00004000 // ENABLE SYSCFG CLOCK
  104. str r1, [r0, #0]
  105. ldr r0, =0x40013800 // SYSCFG_MEMRMP
  106. ldr r1, =0x00000001 // MAP ROM AT ZERO
  107. str r1, [r0, #0]
  108. ldr r0, =0x1FFF0000 // ROM BASE
  109. ldr sp, [r0, #0] // SP @ +0
  110. ldr r0, [r0, #4] // PC @ +4
  111. bx r0
  112. .size Reset_Handler, .-Reset_Handler
  113. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/