My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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lpc17xx_emac.h 39KB

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  1. /**********************************************************************
  2. * $Id$ lpc17xx_emac.h 2010-05-21
  3. *//**
  4. * @file lpc17xx_emac.h
  5. * @brief Contains all macro definitions and function prototypes
  6. * support for Ethernet MAC firmware library on LPC17xx
  7. * @version 2.0
  8. * @date 21. May. 2010
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2010, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
  34. * @ingroup LPC1700CMSIS_FwLib_Drivers
  35. * @{
  36. */
  37. #ifndef LPC17XX_EMAC_H_
  38. #define LPC17XX_EMAC_H_
  39. /* Includes ------------------------------------------------------------------- */
  40. #include "LPC17xx.h"
  41. #include "lpc_types.h"
  42. #ifdef __cplusplus
  43. extern "C"
  44. {
  45. #endif
  46. #define MCB_LPC_1768
  47. //#define IAR_LPC_1768
  48. /* Public Macros -------------------------------------------------------------- */
  49. /** @defgroup EMAC_Public_Macros EMAC Public Macros
  50. * @{
  51. */
  52. /* EMAC PHY status type definitions */
  53. #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
  54. #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
  55. #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
  56. /* EMAC PHY device Speed definitions */
  57. #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
  58. #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
  59. #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
  60. #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
  61. #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
  62. /**
  63. * @}
  64. */
  65. /* Private Macros ------------------------------------------------------------- */
  66. /** @defgroup EMAC_Private_Macros EMAC Private Macros
  67. * @{
  68. */
  69. /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
  70. #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
  71. #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
  72. #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
  73. #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
  74. /* --------------------- BIT DEFINITIONS -------------------------------------- */
  75. /*********************************************************************//**
  76. * Macro defines for MAC Configuration Register 1
  77. **********************************************************************/
  78. #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
  79. #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
  80. #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
  81. #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
  82. #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
  83. #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
  84. #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
  85. #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
  86. #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
  87. #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
  88. #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
  89. /*********************************************************************//**
  90. * Macro defines for MAC Configuration Register 2
  91. **********************************************************************/
  92. #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
  93. #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
  94. #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
  95. #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
  96. #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
  97. #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
  98. #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
  99. #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
  100. #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
  101. #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
  102. #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
  103. #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
  104. #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
  105. /*********************************************************************//**
  106. * Macro defines for Back-to-Back Inter-Packet-Gap Register
  107. **********************************************************************/
  108. /** Programmable field representing the nibble time offset of the minimum possible period
  109. * between the end of any transmitted packet to the beginning of the next */
  110. #define EMAC_IPGT_BBIPG(n) (n&0x7F)
  111. /** Recommended value for Full Duplex of Programmable field representing the nibble time
  112. * offset of the minimum possible period between the end of any transmitted packet to the
  113. * beginning of the next */
  114. #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
  115. /** Recommended value for Half Duplex of Programmable field representing the nibble time
  116. * offset of the minimum possible period between the end of any transmitted packet to the
  117. * beginning of the next */
  118. #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
  119. /*********************************************************************//**
  120. * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
  121. **********************************************************************/
  122. /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
  123. #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
  124. /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
  125. #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
  126. /** Programmable field representing the optional carrierSense window referenced in
  127. * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
  128. #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
  129. /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
  130. #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
  131. /*********************************************************************//**
  132. * Macro defines for Collision Window/Retry Register
  133. **********************************************************************/
  134. /** Programmable field specifying the number of retransmission attempts following a collision before
  135. * aborting the packet due to excessive collisions */
  136. #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
  137. /** Programmable field representing the slot time or collision window during which collisions occur
  138. * in properly configured networks */
  139. #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
  140. /** Default value for Collision Window / Retry register */
  141. #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
  142. /*********************************************************************//**
  143. * Macro defines for Maximum Frame Register
  144. **********************************************************************/
  145. /** Represents a maximum receive frame of 1536 octets */
  146. #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
  147. /*********************************************************************//**
  148. * Macro defines for PHY Support Register
  149. **********************************************************************/
  150. #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
  151. //#define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
  152. /*********************************************************************//**
  153. * Macro defines for Test Register
  154. **********************************************************************/
  155. #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
  156. #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
  157. #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
  158. /*********************************************************************//**
  159. * Macro defines for MII Management Configuration Register
  160. **********************************************************************/
  161. #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
  162. #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
  163. #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
  164. #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
  165. #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
  166. /*********************************************************************//**
  167. * Macro defines for MII Management Command Register
  168. **********************************************************************/
  169. #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
  170. #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
  171. #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
  172. #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
  173. /*********************************************************************//**
  174. * Macro defines for MII Management Address Register
  175. **********************************************************************/
  176. #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
  177. #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
  178. /*********************************************************************//**
  179. * Macro defines for MII Management Write Data Register
  180. **********************************************************************/
  181. #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
  182. /*********************************************************************//**
  183. * Macro defines for MII Management Read Data Register
  184. **********************************************************************/
  185. #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
  186. /*********************************************************************//**
  187. * Macro defines for MII Management Indicators Register
  188. **********************************************************************/
  189. #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
  190. #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
  191. #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
  192. #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
  193. /* Station Address 0 Register */
  194. /* Station Address 1 Register */
  195. /* Station Address 2 Register */
  196. /* Control register definitions --------------------------------------------------------------------------- */
  197. /*********************************************************************//**
  198. * Macro defines for Command Register
  199. **********************************************************************/
  200. #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
  201. #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
  202. #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
  203. #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
  204. #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
  205. #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
  206. #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
  207. #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
  208. #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
  209. #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
  210. /*********************************************************************//**
  211. * Macro defines for Status Register
  212. **********************************************************************/
  213. #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
  214. #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
  215. /*********************************************************************//**
  216. * Macro defines for Transmit Status Vector 0 Register
  217. **********************************************************************/
  218. #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
  219. #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
  220. #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
  221. #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
  222. #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
  223. #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
  224. #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
  225. #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
  226. #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
  227. #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
  228. #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
  229. #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
  230. #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
  231. #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
  232. #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
  233. #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
  234. #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
  235. /*********************************************************************//**
  236. * Macro defines for Transmit Status Vector 1 Register
  237. **********************************************************************/
  238. #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
  239. #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
  240. /*********************************************************************//**
  241. * Macro defines for Receive Status Vector Register
  242. **********************************************************************/
  243. #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
  244. #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
  245. #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
  246. #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
  247. #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
  248. #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
  249. #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
  250. #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
  251. #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
  252. #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
  253. #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
  254. #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
  255. #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
  256. #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
  257. #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
  258. #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
  259. /*********************************************************************//**
  260. * Macro defines for Flow Control Counter Register
  261. **********************************************************************/
  262. #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
  263. #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
  264. /*********************************************************************//**
  265. * Macro defines for Flow Control Status Register
  266. **********************************************************************/
  267. #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
  268. /* Receive filter register definitions -------------------------------------------------------- */
  269. /*********************************************************************//**
  270. * Macro defines for Receive Filter Control Register
  271. **********************************************************************/
  272. #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
  273. #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
  274. #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
  275. #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
  276. #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
  277. #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
  278. #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
  279. #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
  280. /*********************************************************************//**
  281. * Macro defines for Receive Filter WoL Status/Clear Registers
  282. **********************************************************************/
  283. #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
  284. #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
  285. #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
  286. #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
  287. #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
  288. #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
  289. #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
  290. #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
  291. #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
  292. /* Module control register definitions ---------------------------------------------------- */
  293. /*********************************************************************//**
  294. * Macro defines for Interrupt Status/Enable/Clear/Set Registers
  295. **********************************************************************/
  296. #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
  297. #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
  298. #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
  299. #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
  300. #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
  301. #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
  302. #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
  303. #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
  304. #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
  305. #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
  306. /*********************************************************************//**
  307. * Macro defines for Power Down Register
  308. **********************************************************************/
  309. #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
  310. /* Descriptor and status formats ---------------------------------------------------- */
  311. /*********************************************************************//**
  312. * Macro defines for RX Descriptor Control Word
  313. **********************************************************************/
  314. #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
  315. #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
  316. /*********************************************************************//**
  317. * Macro defines for RX Status Hash CRC Word
  318. **********************************************************************/
  319. #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
  320. #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
  321. /*********************************************************************//**
  322. * Macro defines for RX Status Information Word
  323. **********************************************************************/
  324. #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
  325. #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
  326. #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
  327. #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
  328. #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
  329. #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
  330. #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
  331. #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
  332. #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
  333. #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
  334. #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
  335. #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
  336. #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
  337. #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
  338. #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
  339. #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
  340. EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
  341. /*********************************************************************//**
  342. * Macro defines for TX Descriptor Control Word
  343. **********************************************************************/
  344. #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
  345. #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
  346. #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
  347. #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
  348. #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
  349. #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
  350. #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
  351. /*********************************************************************//**
  352. * Macro defines for TX Status Information Word
  353. **********************************************************************/
  354. #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
  355. #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
  356. #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
  357. #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
  358. #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
  359. #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
  360. #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
  361. #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
  362. #ifdef MCB_LPC_1768
  363. /* DP83848C PHY definition ------------------------------------------------------------ */
  364. /** PHY device reset time out definition */
  365. #define EMAC_PHY_RESP_TOUT 0x100000UL
  366. /* ENET Device Revision ID */
  367. #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
  368. /*********************************************************************//**
  369. * Macro defines for DP83848C PHY Registers
  370. **********************************************************************/
  371. #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
  372. #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
  373. #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
  374. #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
  375. #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
  376. #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
  377. #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
  378. #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
  379. #define EMAC_PHY_REG_LPNPA 0x08
  380. /*********************************************************************//**
  381. * Macro defines for PHY Extended Registers
  382. **********************************************************************/
  383. #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
  384. #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
  385. #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
  386. #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
  387. #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
  388. #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
  389. #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
  390. #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
  391. #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
  392. #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
  393. #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
  394. #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
  395. /*********************************************************************//**
  396. * Macro defines for PHY Basic Mode Control Register
  397. **********************************************************************/
  398. #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
  399. #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
  400. #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
  401. #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
  402. #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
  403. #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
  404. #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
  405. #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
  406. /*********************************************************************//**
  407. * Macro defines for PHY Basic Mode Status Status Register
  408. **********************************************************************/
  409. #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
  410. #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
  411. #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
  412. #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
  413. #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
  414. #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
  415. #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
  416. #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
  417. #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
  418. #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
  419. /*********************************************************************//**
  420. * Macro defines for PHY Status Register
  421. **********************************************************************/
  422. #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
  423. #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
  424. #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
  425. #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
  426. #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
  427. #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
  428. #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
  429. #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
  430. #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
  431. #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
  432. #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
  433. #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
  434. #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
  435. #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
  436. #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
  437. #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
  438. #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
  439. #elif defined(IAR_LPC_1768)
  440. /* KSZ8721BL PHY definition ------------------------------------------------------------ */
  441. /** PHY device reset time out definition */
  442. #define EMAC_PHY_RESP_TOUT 0x100000UL
  443. /* ENET Device Revision ID */
  444. #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
  445. /*********************************************************************//**
  446. * Macro defines for KSZ8721BL PHY Registers
  447. **********************************************************************/
  448. #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
  449. #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
  450. #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
  451. #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
  452. #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
  453. #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
  454. #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
  455. #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
  456. #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
  457. #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
  458. #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
  459. #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
  460. /*********************************************************************//**
  461. * Macro defines for PHY Basic Mode Control Register
  462. **********************************************************************/
  463. #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
  464. #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
  465. #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
  466. #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
  467. #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
  468. #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
  469. #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
  470. #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
  471. #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
  472. #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
  473. /*********************************************************************//**
  474. * Macro defines for PHY Basic Mode Status Register
  475. **********************************************************************/
  476. #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
  477. #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
  478. #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
  479. #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
  480. #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
  481. #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
  482. #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
  483. #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
  484. #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
  485. #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
  486. #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
  487. #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
  488. /*********************************************************************//**
  489. * Macro defines for PHY Identifier
  490. **********************************************************************/
  491. /* PHY Identifier 1 bitmap definitions */
  492. #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
  493. /* PHY Identifier 2 bitmap definitions */
  494. #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
  495. /*********************************************************************//**
  496. * Macro defines for Auto-Negotiation Advertisement
  497. **********************************************************************/
  498. #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
  499. #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
  500. #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
  501. #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
  502. #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
  503. #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
  504. #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
  505. #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
  506. #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
  507. #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
  508. #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
  509. #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
  510. #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
  511. #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
  512. #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
  513. #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
  514. #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
  515. #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
  516. #endif
  517. /**
  518. * @}
  519. */
  520. /* Public Types --------------------------------------------------------------- */
  521. /** @defgroup EMAC_Public_Types EMAC Public Types
  522. * @{
  523. */
  524. /* Descriptor and status formats ---------------------------------------------- */
  525. /**
  526. * @brief RX Descriptor structure type definition
  527. */
  528. typedef struct {
  529. uint32_t Packet; /**< Receive Packet Descriptor */
  530. uint32_t Ctrl; /**< Receive Control Descriptor */
  531. } RX_Desc;
  532. /**
  533. * @brief RX Status structure type definition
  534. */
  535. typedef struct {
  536. uint32_t Info; /**< Receive Information Status */
  537. uint32_t HashCRC; /**< Receive Hash CRC Status */
  538. } RX_Stat;
  539. /**
  540. * @brief TX Descriptor structure type definition
  541. */
  542. typedef struct {
  543. uint32_t Packet; /**< Transmit Packet Descriptor */
  544. uint32_t Ctrl; /**< Transmit Control Descriptor */
  545. } TX_Desc;
  546. /**
  547. * @brief TX Status structure type definition
  548. */
  549. typedef struct {
  550. uint32_t Info; /**< Transmit Information Status */
  551. } TX_Stat;
  552. /**
  553. * @brief TX Data Buffer structure definition
  554. */
  555. typedef struct {
  556. uint32_t ulDataLen; /**< Data length */
  557. uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
  558. } EMAC_PACKETBUF_Type;
  559. /**
  560. * @brief EMAC configuration structure definition
  561. */
  562. typedef struct {
  563. uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
  564. - EMAC_MODE_AUTO
  565. - EMAC_MODE_10M_FULL
  566. - EMAC_MODE_10M_HALF
  567. - EMAC_MODE_100M_FULL
  568. - EMAC_MODE_100M_HALF
  569. */
  570. uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
  571. of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
  572. */
  573. } EMAC_CFG_Type;
  574. /**
  575. * @}
  576. */
  577. /* Public Functions ----------------------------------------------------------- */
  578. /** @defgroup EMAC_Public_Functions EMAC Public Functions
  579. * @{
  580. */
  581. /* Init/DeInit EMAC peripheral */
  582. Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
  583. void EMAC_DeInit(void);
  584. /* PHY functions --------------*/
  585. int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
  586. int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
  587. int32_t EMAC_UpdatePHYStatus(void);
  588. /* Filter functions ----------*/
  589. void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
  590. void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);
  591. /* EMAC Packet Buffer functions */
  592. void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
  593. void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);
  594. /* EMAC Interrupt functions -------*/
  595. void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
  596. IntStatus EMAC_IntGetStatus(uint32_t ulIntType);
  597. /* EMAC Index functions -----------*/
  598. Bool EMAC_CheckReceiveIndex(void);
  599. Bool EMAC_CheckTransmitIndex(void);
  600. void EMAC_UpdateRxConsumeIndex(void);
  601. void EMAC_UpdateTxProduceIndex(void);
  602. FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
  603. uint32_t EMAC_GetReceiveDataSize(void);
  604. FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);
  605. /**
  606. * @}
  607. */
  608. #ifdef __cplusplus
  609. }
  610. #endif
  611. #endif /* LPC17XX_EMAC_H_ */
  612. /**
  613. * @}
  614. */
  615. /* --------------------------------- End Of File ------------------------------ */