My Marlin configs for Fabrikator Mini and CTC i3 Pro B
Você não pode selecionar mais de 25 tópicos Os tópicos devem começar com uma letra ou um número, podem incluir traços ('-') e podem ter até 35 caracteres.

lpc17xx_gpdma.h 19KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429
  1. /**********************************************************************
  2. * $Id$ lpc17xx_gpdma.h 2010-05-21
  3. *//**
  4. * @file lpc17xx_gpdma.h
  5. * @brief Contains all macro definitions and function prototypes
  6. * support for GPDMA firmware library on LPC17xx
  7. * @version 2.0
  8. * @date 21. May. 2010
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2010, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @defgroup GPDMA GPDMA (General Purpose Direct Memory Access)
  34. * @ingroup LPC1700CMSIS_FwLib_Drivers
  35. * @{
  36. */
  37. #ifndef LPC17XX_GPDMA_H_
  38. #define LPC17XX_GPDMA_H_
  39. /* Includes ------------------------------------------------------------------- */
  40. #include "LPC17xx.h"
  41. #include "lpc_types.h"
  42. #ifdef __cplusplus
  43. extern "C"
  44. {
  45. #endif
  46. /* Public Macros -------------------------------------------------------------- */
  47. /** @defgroup GPDMA_Public_Macros GPDMA Public Macros
  48. * @{
  49. */
  50. /** DMA Connection number definitions */
  51. #define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */
  52. #define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */
  53. #define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */
  54. #define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */
  55. #define GPDMA_CONN_ADC ((4UL)) /**< ADC */
  56. #define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */
  57. #define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */
  58. #define GPDMA_CONN_DAC ((7UL)) /**< DAC */
  59. #define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */
  60. #define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */
  61. #define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */
  62. #define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */
  63. #define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */
  64. #define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */
  65. #define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */
  66. #define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */
  67. #define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */
  68. #define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */
  69. #define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */
  70. #define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */
  71. #define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */
  72. #define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */
  73. #define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */
  74. #define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */
  75. /** GPDMA Transfer type definitions */
  76. #define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */
  77. #define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */
  78. #define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */
  79. #define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */
  80. /** Burst size in Source and Destination definitions */
  81. #define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
  82. #define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
  83. #define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
  84. #define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
  85. #define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
  86. #define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
  87. #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
  88. #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
  89. /** Width in Source transfer width and Destination transfer width definitions */
  90. #define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
  91. #define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
  92. #define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
  93. /** DMA Request Select Mode definitions */
  94. #define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */
  95. #define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */
  96. /**
  97. * @}
  98. */
  99. /* Private Macros ------------------------------------------------------------- */
  100. /** @defgroup GPDMA_Private_Macros GPDMA Private Macros
  101. * @{
  102. */
  103. /* --------------------- BIT DEFINITIONS -------------------------------------- */
  104. /*********************************************************************//**
  105. * Macro defines for DMA Interrupt Status register
  106. **********************************************************************/
  107. #define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
  108. #define GPDMA_DMACIntStat_BITMASK ((0xFF))
  109. /*********************************************************************//**
  110. * Macro defines for DMA Interrupt Terminal Count Request Status register
  111. **********************************************************************/
  112. #define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
  113. #define GPDMA_DMACIntTCStat_BITMASK ((0xFF))
  114. /*********************************************************************//**
  115. * Macro defines for DMA Interrupt Terminal Count Request Clear register
  116. **********************************************************************/
  117. #define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
  118. #define GPDMA_DMACIntTCClear_BITMASK ((0xFF))
  119. /*********************************************************************//**
  120. * Macro defines for DMA Interrupt Error Status register
  121. **********************************************************************/
  122. #define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
  123. #define GPDMA_DMACIntErrStat_BITMASK ((0xFF))
  124. /*********************************************************************//**
  125. * Macro defines for DMA Interrupt Error Clear register
  126. **********************************************************************/
  127. #define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
  128. #define GPDMA_DMACIntErrClr_BITMASK ((0xFF))
  129. /*********************************************************************//**
  130. * Macro defines for DMA Raw Interrupt Terminal Count Status register
  131. **********************************************************************/
  132. #define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
  133. #define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF))
  134. /*********************************************************************//**
  135. * Macro defines for DMA Raw Error Interrupt Status register
  136. **********************************************************************/
  137. #define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
  138. #define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF))
  139. /*********************************************************************//**
  140. * Macro defines for DMA Enabled Channel register
  141. **********************************************************************/
  142. #define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
  143. #define GPDMA_DMACEnbldChns_BITMASK ((0xFF))
  144. /*********************************************************************//**
  145. * Macro defines for DMA Software Burst Request register
  146. **********************************************************************/
  147. #define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
  148. #define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF))
  149. /*********************************************************************//**
  150. * Macro defines for DMA Software Single Request register
  151. **********************************************************************/
  152. #define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
  153. #define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF))
  154. /*********************************************************************//**
  155. * Macro defines for DMA Software Last Burst Request register
  156. **********************************************************************/
  157. #define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
  158. #define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF))
  159. /*********************************************************************//**
  160. * Macro defines for DMA Software Last Single Request register
  161. **********************************************************************/
  162. #define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
  163. #define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF))
  164. /*********************************************************************//**
  165. * Macro defines for DMA Configuration register
  166. **********************************************************************/
  167. #define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/
  168. #define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/
  169. #define GPDMA_DMACConfig_BITMASK ((0x03))
  170. /*********************************************************************//**
  171. * Macro defines for DMA Synchronization register
  172. **********************************************************************/
  173. #define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
  174. #define GPDMA_DMACSync_BITMASK ((0xFFFF))
  175. /*********************************************************************//**
  176. * Macro defines for DMA Request Select register
  177. **********************************************************************/
  178. #define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
  179. #define GPDMA_DMAReqSel_BITMASK ((0xFF))
  180. /*********************************************************************//**
  181. * Macro defines for DMA Channel Linked List Item registers
  182. **********************************************************************/
  183. /** DMA Channel Linked List Item registers bit mask*/
  184. #define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
  185. /*********************************************************************//**
  186. * Macro defines for DMA channel control registers
  187. **********************************************************************/
  188. #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/
  189. #define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/
  190. #define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/
  191. #define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/
  192. #define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/
  193. #define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/
  194. #define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/
  195. #define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/
  196. #define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/
  197. #define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/
  198. #define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */
  199. /** DMA channel control registers bit mask */
  200. #define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF))
  201. /*********************************************************************//**
  202. * Macro defines for DMA Channel Configuration registers
  203. **********************************************************************/
  204. #define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/
  205. #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/
  206. #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/
  207. #define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/
  208. #define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/
  209. #define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/
  210. #define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/
  211. #define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/
  212. #define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/
  213. /** DMA Channel Configuration registers bit mask */
  214. #define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF))
  215. /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
  216. /* Macros check GPDMA channel */
  217. #define PARAM_GPDMA_CHANNEL(n) (n<=7)
  218. /* Macros check GPDMA connection type */
  219. #define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \
  220. || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \
  221. || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \
  222. || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \
  223. || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \
  224. || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \
  225. || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \
  226. || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \
  227. || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \
  228. || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \
  229. || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \
  230. || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1))
  231. /* Macros check GPDMA burst size type */
  232. #define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \
  233. || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \
  234. || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \
  235. || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256))
  236. /* Macros check GPDMA width type */
  237. #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \
  238. || (n==GPDMA_WIDTH_WORD))
  239. /* Macros check GPDMA status type */
  240. #define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \
  241. || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \
  242. || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH))
  243. /* Macros check GPDMA transfer type */
  244. #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \
  245. ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P))
  246. /* Macros check GPDMA state clear type */
  247. #define PARAM_GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR))
  248. /* Macros check GPDMA request select type */
  249. #define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER))
  250. /**
  251. * @}
  252. */
  253. /* Public Types --------------------------------------------------------------- */
  254. /** @defgroup GPDMA_Public_Types GPDMA Public Types
  255. * @{
  256. */
  257. /**
  258. * @brief GPDMA Status enumeration
  259. */
  260. typedef enum {
  261. GPDMA_STAT_INT, /**< GPDMA Interrupt Status */
  262. GPDMA_STAT_INTTC, /**< GPDMA Interrupt Terminal Count Request Status */
  263. GPDMA_STAT_INTERR, /**< GPDMA Interrupt Error Status */
  264. GPDMA_STAT_RAWINTTC, /**< GPDMA Raw Interrupt Terminal Count Status */
  265. GPDMA_STAT_RAWINTERR, /**< GPDMA Raw Error Interrupt Status */
  266. GPDMA_STAT_ENABLED_CH /**< GPDMA Enabled Channel Status */
  267. } GPDMA_Status_Type;
  268. /**
  269. * @brief GPDMA Interrupt clear status enumeration
  270. */
  271. typedef enum{
  272. GPDMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
  273. GPDMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
  274. }GPDMA_StateClear_Type;
  275. /**
  276. * @brief GPDMA Channel configuration structure type definition
  277. */
  278. typedef struct {
  279. uint32_t ChannelNum; /**< DMA channel number, should be in
  280. range from 0 to 7.
  281. Note: DMA channel 0 has the highest priority
  282. and DMA channel 7 the lowest priority.
  283. */
  284. uint32_t TransferSize; /**< Length/Size of transfer */
  285. uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */
  286. uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as
  287. GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */
  288. uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as
  289. GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */
  290. uint32_t TransferType; /**< Transfer Type, should be one of the following:
  291. - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control
  292. - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control
  293. - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control
  294. - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control
  295. */
  296. uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as
  297. GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of
  298. following:
  299. - GPDMA_CONN_SSP0_Tx: SSP0, Tx
  300. - GPDMA_CONN_SSP0_Rx: SSP0, Rx
  301. - GPDMA_CONN_SSP1_Tx: SSP1, Tx
  302. - GPDMA_CONN_SSP1_Rx: SSP1, Rx
  303. - GPDMA_CONN_ADC: ADC
  304. - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
  305. - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
  306. - GPDMA_CONN_DAC: DAC
  307. - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
  308. - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
  309. - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
  310. - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
  311. - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
  312. - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
  313. - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
  314. - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
  315. */
  316. uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as
  317. GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of
  318. following:
  319. - GPDMA_CONN_SSP0_Tx: SSP0, Tx
  320. - GPDMA_CONN_SSP0_Rx: SSP0, Rx
  321. - GPDMA_CONN_SSP1_Tx: SSP1, Tx
  322. - GPDMA_CONN_SSP1_Rx: SSP1, Rx
  323. - GPDMA_CONN_ADC: ADC
  324. - GPDMA_CONN_I2S_Channel_0: I2S Channel 0
  325. - GPDMA_CONN_I2S_Channel_1: I2S Channel 1
  326. - GPDMA_CONN_DAC: DAC
  327. - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0
  328. - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1
  329. - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0
  330. - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1
  331. - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0
  332. - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1
  333. - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0
  334. - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1
  335. */
  336. uint32_t DMALLI; /**< Linker List Item structure data address
  337. if there's no Linker List, set as '0'
  338. */
  339. } GPDMA_Channel_CFG_Type;
  340. /**
  341. * @brief GPDMA Linker List Item structure type definition
  342. */
  343. typedef struct {
  344. uint32_t SrcAddr; /**< Source Address */
  345. uint32_t DstAddr; /**< Destination address */
  346. uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */
  347. uint32_t Control; /**< GPDMA Control of this LLI */
  348. } GPDMA_LLI_Type;
  349. /**
  350. * @}
  351. */
  352. /* Public Functions ----------------------------------------------------------- */
  353. /** @defgroup GPDMA_Public_Functions GPDMA Public Functions
  354. * @{
  355. */
  356. void GPDMA_Init(void);
  357. //Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs);
  358. Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig);
  359. IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel);
  360. void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel);
  361. void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState);
  362. //void GPDMA_IntHandler(void);
  363. /**
  364. * @}
  365. */
  366. #ifdef __cplusplus
  367. }
  368. #endif
  369. #endif /* LPC17XX_GPDMA_H_ */
  370. /**
  371. * @}
  372. */
  373. /* --------------------------------- End Of File ------------------------------ */