My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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lpc17xx_i2c.h 15KB

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  1. /**********************************************************************
  2. * $Id$ lpc17xx_i2c.h 2010-05-21
  3. *//**
  4. * @file lpc17xx_i2c.h
  5. * @brief Contains all macro definitions and function prototypes
  6. * support for I2C firmware library on LPC17xx
  7. * @version 2.0
  8. * @date 21. May. 2010
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2010, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @defgroup I2C I2C (Inter-IC Control bus)
  34. * @ingroup LPC1700CMSIS_FwLib_Drivers
  35. * @{
  36. */
  37. #ifndef LPC17XX_I2C_H_
  38. #define LPC17XX_I2C_H_
  39. /* Includes ------------------------------------------------------------------- */
  40. #include "LPC17xx.h"
  41. #include "lpc_types.h"
  42. #ifdef __cplusplus
  43. extern "C"
  44. {
  45. #endif
  46. /* Private Macros ------------------------------------------------------------- */
  47. /** @defgroup I2C_Private_Macros I2C Private Macros
  48. * @{
  49. */
  50. /* --------------------- BIT DEFINITIONS -------------------------------------- */
  51. /*******************************************************************//**
  52. * I2C Control Set register description
  53. *********************************************************************/
  54. #define I2C_I2CONSET_AA ((0x04)) /*!< Assert acknowledge flag */
  55. #define I2C_I2CONSET_SI ((0x08)) /*!< I2C interrupt flag */
  56. #define I2C_I2CONSET_STO ((0x10)) /*!< STOP flag */
  57. #define I2C_I2CONSET_STA ((0x20)) /*!< START flag */
  58. #define I2C_I2CONSET_I2EN ((0x40)) /*!< I2C interface enable */
  59. /*******************************************************************//**
  60. * I2C Control Clear register description
  61. *********************************************************************/
  62. /** Assert acknowledge Clear bit */
  63. #define I2C_I2CONCLR_AAC ((1<<2))
  64. /** I2C interrupt Clear bit */
  65. #define I2C_I2CONCLR_SIC ((1<<3))
  66. /** I2C STOP Clear bit */
  67. #define I2C_I2CONCLR_STOC ((1<<4))
  68. /** START flag Clear bit */
  69. #define I2C_I2CONCLR_STAC ((1<<5))
  70. /** I2C interface Disable bit */
  71. #define I2C_I2CONCLR_I2ENC ((1<<6))
  72. /********************************************************************//**
  73. * I2C Status Code definition (I2C Status register)
  74. *********************************************************************/
  75. /* Return Code in I2C status register */
  76. #define I2C_STAT_CODE_BITMASK ((0xF8))
  77. /* I2C return status code definitions ----------------------------- */
  78. /** No relevant information */
  79. #define I2C_I2STAT_NO_INF ((0xF8))
  80. /** Bus Error */
  81. #define I2C_I2STAT_BUS_ERROR ((0x00))
  82. /* Master transmit mode -------------------------------------------- */
  83. /** A start condition has been transmitted */
  84. #define I2C_I2STAT_M_TX_START ((0x08))
  85. /** A repeat start condition has been transmitted */
  86. #define I2C_I2STAT_M_TX_RESTART ((0x10))
  87. /** SLA+W has been transmitted, ACK has been received */
  88. #define I2C_I2STAT_M_TX_SLAW_ACK ((0x18))
  89. /** SLA+W has been transmitted, NACK has been received */
  90. #define I2C_I2STAT_M_TX_SLAW_NACK ((0x20))
  91. /** Data has been transmitted, ACK has been received */
  92. #define I2C_I2STAT_M_TX_DAT_ACK ((0x28))
  93. /** Data has been transmitted, NACK has been received */
  94. #define I2C_I2STAT_M_TX_DAT_NACK ((0x30))
  95. /** Arbitration lost in SLA+R/W or Data bytes */
  96. #define I2C_I2STAT_M_TX_ARB_LOST ((0x38))
  97. /* Master receive mode -------------------------------------------- */
  98. /** A start condition has been transmitted */
  99. #define I2C_I2STAT_M_RX_START ((0x08))
  100. /** A repeat start condition has been transmitted */
  101. #define I2C_I2STAT_M_RX_RESTART ((0x10))
  102. /** Arbitration lost */
  103. #define I2C_I2STAT_M_RX_ARB_LOST ((0x38))
  104. /** SLA+R has been transmitted, ACK has been received */
  105. #define I2C_I2STAT_M_RX_SLAR_ACK ((0x40))
  106. /** SLA+R has been transmitted, NACK has been received */
  107. #define I2C_I2STAT_M_RX_SLAR_NACK ((0x48))
  108. /** Data has been received, ACK has been returned */
  109. #define I2C_I2STAT_M_RX_DAT_ACK ((0x50))
  110. /** Data has been received, NACK has been return */
  111. #define I2C_I2STAT_M_RX_DAT_NACK ((0x58))
  112. /* Slave receive mode -------------------------------------------- */
  113. /** Own slave address has been received, ACK has been returned */
  114. #define I2C_I2STAT_S_RX_SLAW_ACK ((0x60))
  115. /** Arbitration lost in SLA+R/W as master */
  116. #define I2C_I2STAT_S_RX_ARB_LOST_M_SLA ((0x68))
  117. /** General call address has been received, ACK has been returned */
  118. #define I2C_I2STAT_S_RX_GENCALL_ACK ((0x70))
  119. /** Arbitration lost in SLA+R/W (GENERAL CALL) as master */
  120. #define I2C_I2STAT_S_RX_ARB_LOST_M_GENCALL ((0x78))
  121. /** Previously addressed with own SLV address;
  122. * Data has been received, ACK has been return */
  123. #define I2C_I2STAT_S_RX_PRE_SLA_DAT_ACK ((0x80))
  124. /** Previously addressed with own SLA;
  125. * Data has been received and NOT ACK has been return */
  126. #define I2C_I2STAT_S_RX_PRE_SLA_DAT_NACK ((0x88))
  127. /** Previously addressed with General Call;
  128. * Data has been received and ACK has been return */
  129. #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_ACK ((0x90))
  130. /** Previously addressed with General Call;
  131. * Data has been received and NOT ACK has been return */
  132. #define I2C_I2STAT_S_RX_PRE_GENCALL_DAT_NACK ((0x98))
  133. /** A STOP condition or repeated START condition has
  134. * been received while still addressed as SLV/REC
  135. * (Slave Receive) or SLV/TRX (Slave Transmit) */
  136. #define I2C_I2STAT_S_RX_STA_STO_SLVREC_SLVTRX ((0xA0))
  137. /** Slave transmit mode */
  138. /** Own SLA+R has been received, ACK has been returned */
  139. #define I2C_I2STAT_S_TX_SLAR_ACK ((0xA8))
  140. /** Arbitration lost in SLA+R/W as master */
  141. #define I2C_I2STAT_S_TX_ARB_LOST_M_SLA ((0xB0))
  142. /** Data has been transmitted, ACK has been received */
  143. #define I2C_I2STAT_S_TX_DAT_ACK ((0xB8))
  144. /** Data has been transmitted, NACK has been received */
  145. #define I2C_I2STAT_S_TX_DAT_NACK ((0xC0))
  146. /** Last data byte in I2DAT has been transmitted (AA = 0);
  147. ACK has been received */
  148. #define I2C_I2STAT_S_TX_LAST_DAT_ACK ((0xC8))
  149. /** Time out in case of using I2C slave mode */
  150. #define I2C_SLAVE_TIME_OUT 0x10000UL
  151. /********************************************************************//**
  152. * I2C Data register definition
  153. *********************************************************************/
  154. /** Mask for I2DAT register*/
  155. #define I2C_I2DAT_BITMASK ((0xFF))
  156. /** Idle data value will be send out in slave mode in case of the actual
  157. * expecting data requested from the master is greater than its sending data
  158. * length that can be supported */
  159. #define I2C_I2DAT_IDLE_CHAR (0xFF)
  160. /********************************************************************//**
  161. * I2C Monitor mode control register description
  162. *********************************************************************/
  163. #define I2C_I2MMCTRL_MM_ENA ((1<<0)) /**< Monitor mode enable */
  164. #define I2C_I2MMCTRL_ENA_SCL ((1<<1)) /**< SCL output enable */
  165. #define I2C_I2MMCTRL_MATCH_ALL ((1<<2)) /**< Select interrupt register match */
  166. #define I2C_I2MMCTRL_BITMASK ((0x07)) /**< Mask for I2MMCTRL register */
  167. /********************************************************************//**
  168. * I2C Data buffer register description
  169. *********************************************************************/
  170. /** I2C Data buffer register bit mask */
  171. #define I2DATA_BUFFER_BITMASK ((0xFF))
  172. /********************************************************************//**
  173. * I2C Slave Address registers definition
  174. *********************************************************************/
  175. /** General Call enable bit */
  176. #define I2C_I2ADR_GC ((1<<0))
  177. /** I2C Slave Address registers bit mask */
  178. #define I2C_I2ADR_BITMASK ((0xFF))
  179. /********************************************************************//**
  180. * I2C Mask Register definition
  181. *********************************************************************/
  182. /** I2C Mask Register mask field */
  183. #define I2C_I2MASK_MASK(n) ((n&0xFE))
  184. /********************************************************************//**
  185. * I2C SCL HIGH duty cycle Register definition
  186. *********************************************************************/
  187. /** I2C SCL HIGH duty cycle Register bit mask */
  188. #define I2C_I2SCLH_BITMASK ((0xFFFF))
  189. /********************************************************************//**
  190. * I2C SCL LOW duty cycle Register definition
  191. *********************************************************************/
  192. /** I2C SCL LOW duty cycle Register bit mask */
  193. #define I2C_I2SCLL_BITMASK ((0xFFFF))
  194. /* I2C status values */
  195. #define I2C_SETUP_STATUS_ARBF (1<<8) /**< Arbitration false */
  196. #define I2C_SETUP_STATUS_NOACKF (1<<9) /**< No ACK returned */
  197. #define I2C_SETUP_STATUS_DONE (1<<10) /**< Status DONE */
  198. /*********************************************************************//**
  199. * I2C monitor control configuration defines
  200. **********************************************************************/
  201. #define I2C_MONITOR_CFG_SCL_OUTPUT I2C_I2MMCTRL_ENA_SCL /**< SCL output enable */
  202. #define I2C_MONITOR_CFG_MATCHALL I2C_I2MMCTRL_MATCH_ALL /**< Select interrupt register match */
  203. /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
  204. /* Macros check I2C slave address */
  205. #define PARAM_I2C_SLAVEADDR_CH(n) (n<=3)
  206. /** Macro to determine if it is valid SSP port number */
  207. #define PARAM_I2Cx(n) ((((uint32_t *)n)==((uint32_t *)LPC_I2C0)) \
  208. || (((uint32_t *)n)==((uint32_t *)LPC_I2C1)) \
  209. || (((uint32_t *)n)==((uint32_t *)LPC_I2C2)))
  210. /* Macros check I2C monitor configuration type */
  211. #define PARAM_I2C_MONITOR_CFG(n) ((n==I2C_MONITOR_CFG_SCL_OUTPUT) || (I2C_MONITOR_CFG_MATCHALL))
  212. /* I2C state handle return values */
  213. #define I2C_OK 0x00
  214. #define I2C_BYTE_SENT 0x01
  215. #define I2C_BYTE_RECV 0x02
  216. #define I2C_LAST_BYTE_RECV 0x04
  217. #define I2C_SEND_END 0x08
  218. #define I2C_RECV_END 0x10
  219. #define I2C_STA_STO_RECV 0x20
  220. #define I2C_ERR (0x10000000)
  221. #define I2C_NAK_RECV (0x10000000 |0x01)
  222. #define I2C_CheckError(ErrorCode) (ErrorCode & 0x10000000)
  223. /**
  224. * @}
  225. */
  226. /* Public Types --------------------------------------------------------------- */
  227. /** @defgroup I2C_Public_Types I2C Public Types
  228. * @{
  229. */
  230. typedef enum
  231. {
  232. I2C_0 = 0,
  233. I2C_1,
  234. I2C_2
  235. } en_I2C_unitId;
  236. typedef enum
  237. {
  238. I2C_MASTER_MODE,
  239. I2C_SLAVE_MODE,
  240. I2C_GENERAL_MODE,
  241. } en_I2C_Mode;
  242. /**
  243. * @brief I2C Own slave address setting structure
  244. */
  245. typedef struct {
  246. uint8_t SlaveAddrChannel; /**< Slave Address channel in I2C control,
  247. should be in range from 0..3
  248. */
  249. uint8_t SlaveAddr_7bit; /**< Value of 7-bit slave address */
  250. uint8_t GeneralCallState; /**< Enable/Disable General Call Functionality
  251. when I2C control being in Slave mode, should be:
  252. - ENABLE: Enable General Call function.
  253. - DISABLE: Disable General Call function.
  254. */
  255. uint8_t SlaveAddrMaskValue; /**< Any bit in this 8-bit value (bit 7:1)
  256. which is set to '1' will cause an automatic compare on
  257. the corresponding bit of the received address when it
  258. is compared to the SlaveAddr_7bit value associated with this
  259. mask register. In other words, bits in SlaveAddr_7bit value
  260. which are masked are not taken into account in determining
  261. an address match
  262. */
  263. } I2C_OWNSLAVEADDR_CFG_Type;
  264. /**
  265. * @brief Master transfer setup data structure definitions
  266. */
  267. typedef struct
  268. {
  269. uint32_t sl_addr7bit; /**< Slave address in 7bit mode */
  270. __IO uint8_t* tx_data; /**< Pointer to Transmit data - NULL if data transmit
  271. is not used */
  272. uint32_t tx_length; /**< Transmit data length - 0 if data transmit
  273. is not used*/
  274. __IO uint32_t tx_count; /**< Current Transmit data counter */
  275. __IO uint8_t* rx_data; /**< Pointer to Receive data - NULL if data receive
  276. is not used */
  277. uint32_t rx_length; /**< Receive data length - 0 if data receive is
  278. not used */
  279. __IO uint32_t rx_count; /**< Current Receive data counter */
  280. uint32_t retransmissions_max; /**< Max Re-Transmission value */
  281. uint32_t retransmissions_count; /**< Current Re-Transmission counter */
  282. __IO uint32_t status; /**< Current status of I2C activity */
  283. void (*callback)(void); /**< Pointer to Call back function when transmission complete
  284. used in interrupt transfer mode */
  285. } I2C_M_SETUP_Type;
  286. /**
  287. * @brief Slave transfer setup data structure definitions
  288. */
  289. typedef struct
  290. {
  291. __IO uint8_t* tx_data;
  292. uint32_t tx_length;
  293. __IO uint32_t tx_count;
  294. __IO uint8_t* rx_data;
  295. uint32_t rx_length;
  296. __IO uint32_t rx_count;
  297. __IO uint32_t status;
  298. void (*callback)(void);
  299. } I2C_S_SETUP_Type;
  300. /**
  301. * @brief Transfer option type definitions
  302. */
  303. typedef enum {
  304. I2C_TRANSFER_POLLING = 0, /**< Transfer in polling mode */
  305. I2C_TRANSFER_INTERRUPT /**< Transfer in interrupt mode */
  306. } I2C_TRANSFER_OPT_Type;
  307. /**
  308. * @}
  309. */
  310. /* Public Functions ----------------------------------------------------------- */
  311. /** @defgroup I2C_Public_Functions I2C Public Functions
  312. * @{
  313. */
  314. /* I2C Init/DeInit functions ---------- */
  315. void I2C_Init(LPC_I2C_TypeDef *I2Cx, uint32_t clockrate);
  316. void I2C_DeInit(LPC_I2C_TypeDef* I2Cx);
  317. void I2C_Cmd(LPC_I2C_TypeDef* I2Cx, en_I2C_Mode Mode, FunctionalState NewState);
  318. /* I2C transfer data functions -------- */
  319. Status I2C_MasterTransferData(LPC_I2C_TypeDef *I2Cx, \
  320. I2C_M_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
  321. Status I2C_SlaveTransferData(LPC_I2C_TypeDef *I2Cx, \
  322. I2C_S_SETUP_Type *TransferCfg, I2C_TRANSFER_OPT_Type Opt);
  323. uint32_t I2C_MasterTransferComplete(LPC_I2C_TypeDef *I2Cx);
  324. uint32_t I2C_SlaveTransferComplete(LPC_I2C_TypeDef *I2Cx);
  325. void I2C_SetOwnSlaveAddr(LPC_I2C_TypeDef *I2Cx, I2C_OWNSLAVEADDR_CFG_Type *OwnSlaveAddrConfigStruct);
  326. uint8_t I2C_GetLastStatusCode(LPC_I2C_TypeDef* I2Cx);
  327. /* I2C Monitor functions ---------------*/
  328. void I2C_MonitorModeConfig(LPC_I2C_TypeDef *I2Cx, uint32_t MonitorCfgType, FunctionalState NewState);
  329. void I2C_MonitorModeCmd(LPC_I2C_TypeDef *I2Cx, FunctionalState NewState);
  330. uint8_t I2C_MonitorGetDatabuffer(LPC_I2C_TypeDef *I2Cx);
  331. BOOL_8 I2C_MonitorHandler(LPC_I2C_TypeDef *I2Cx, uint8_t *buffer, uint32_t size);
  332. /* I2C Interrupt handler functions ------*/
  333. void I2C_IntCmd (LPC_I2C_TypeDef *I2Cx, Bool NewState);
  334. void I2C_MasterHandler (LPC_I2C_TypeDef *I2Cx);
  335. void I2C_SlaveHandler (LPC_I2C_TypeDef *I2Cx);
  336. /**
  337. * @}
  338. */
  339. #ifdef __cplusplus
  340. }
  341. #endif
  342. #endif /* LPC17XX_I2C_H_ */
  343. /**
  344. * @}
  345. */
  346. /* --------------------------------- End Of File ------------------------------ */