My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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lpc17xx_mcpwm.h 14KB

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  1. /**********************************************************************
  2. * $Id$ lpc17xx_mcpwm.h 2010-05-21
  3. *//**
  4. * @file lpc17xx_mcpwm.h
  5. * @brief Contains all macro definitions and function prototypes
  6. * support for Motor Control PWM firmware library on LPC17xx
  7. * @version 2.0
  8. * @date 21. May. 2010
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2010, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @defgroup MCPWM MCPWM (Motor Control PWM)
  34. * @ingroup LPC1700CMSIS_FwLib_Drivers
  35. * @{
  36. */
  37. #ifndef LPC17XX_MCPWM_H_
  38. #define LPC17XX_MCPWM_H_
  39. /* Includes ------------------------------------------------------------------- */
  40. #include "LPC17xx.h"
  41. #include "lpc_types.h"
  42. #ifdef __cplusplus
  43. extern "C"
  44. {
  45. #endif
  46. /* Public Macros -------------------------------------------------------------- */
  47. /** @defgroup MCPWM_Public_Macros MCPWM Public Macros
  48. * @{
  49. */
  50. /** Edge aligned mode for channel in MCPWM */
  51. #define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
  52. /** Center aligned mode for channel in MCPWM */
  53. #define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
  54. /** Polarity of the MCOA and MCOB pins: Passive state is LOW, active state is HIGH */
  55. #define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
  56. /** Polarity of the MCOA and MCOB pins: Passive state is HIGH, active state is LOW */
  57. #define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
  58. /* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
  59. * the six output pins under the control of the bits in this register */
  60. #define MCPWM_PATENT_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
  61. #define MCPWM_PATENT_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
  62. #define MCPWM_PATENT_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
  63. #define MCPWM_PATENT_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
  64. #define MCPWM_PATENT_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
  65. #define MCPWM_PATENT_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
  66. /* Interrupt type in MCPWM */
  67. /** Limit interrupt for channel (0) */
  68. #define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
  69. /** Match interrupt for channel (0) */
  70. #define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
  71. /** Capture interrupt for channel (0) */
  72. #define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
  73. /** Limit interrupt for channel (1) */
  74. #define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
  75. /** Match interrupt for channel (1) */
  76. #define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
  77. /** Capture interrupt for channel (1) */
  78. #define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
  79. /** Limit interrupt for channel (2) */
  80. #define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
  81. /** Match interrupt for channel (2) */
  82. #define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
  83. /** Capture interrupt for channel (2) */
  84. #define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
  85. /** Fast abort interrupt */
  86. #define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
  87. /**
  88. * @}
  89. */
  90. /* Private Macros ------------------------------------------------------------- */
  91. /** @defgroup MCPWM_Private_Macros MCPWM Private Macros
  92. * @{
  93. */
  94. /*********************************************************************//**
  95. * Macro defines for MCPWM Control register
  96. **********************************************************************/
  97. /* MCPWM Control register, these macro definitions below can be applied for these
  98. * register type:
  99. * - MCPWM Control read address
  100. * - MCPWM Control set address
  101. * - MCPWM Control clear address
  102. */
  103. #define MCPWM_CON_RUN(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+0))) : (0)) /**< Stops/starts timer channel n */
  104. #define MCPWM_CON_CENTER(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+1))) : (0)) /**< Edge/center aligned operation for channel n */
  105. #define MCPWM_CON_POLAR(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+2))) : (0)) /**< Select polarity of the MCOAn and MCOBn pin */
  106. #define MCPWM_CON_DTE(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+3))) : (0)) /**< Control the dead-time feature for channel n */
  107. #define MCPWM_CON_DISUP(n) ((n<=2) ? ((uint32_t)(1<<((n*8)+4))) : (0)) /**< Enable/Disable update of functional register for channel n */
  108. #define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) /**< Control the polarity for all 3 channels */
  109. #define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) /**< 3-phase AC mode select */
  110. #define MCPWM_CON_DCMODE ((uint32_t)(0x80000000)) /**< 3-phase DC mode select */
  111. /*********************************************************************//**
  112. * Macro defines for MCPWM Capture Control register
  113. **********************************************************************/
  114. /* Capture Control register, these macro definitions below can be applied for these
  115. * register type:
  116. * - MCPWM Capture Control read address
  117. * - MCPWM Capture Control set address
  118. * - MCPWM Capture control clear address
  119. */
  120. /** Enables/Disable channel (cap) capture event on a rising edge on MCI(mci) */
  121. #define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
  122. /** Enables/Disable channel (cap) capture event on a falling edge on MCI(mci) */
  123. #define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap<=2)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
  124. /** TC(n) is reset by channel (n) capture event */
  125. #define MCPWM_CAPCON_RT(n) ((n<=2) ? ((uint32_t)(1<<(18+(n)))) : (0))
  126. /** Hardware noise filter: channel (n) capture events are delayed */
  127. #define MCPWM_CAPCON_HNFCAP(n) ((n<=2) ? ((uint32_t)(1<<(21+(n)))) : (0))
  128. /*********************************************************************//**
  129. * Macro defines for MCPWM Interrupt register
  130. **********************************************************************/
  131. /* Interrupt registers, these macro definitions below can be applied for these
  132. * register type:
  133. * - MCPWM Interrupt Enable read address
  134. * - MCPWM Interrupt Enable set address
  135. * - MCPWM Interrupt Enable clear address
  136. * - MCPWM Interrupt Flags read address
  137. * - MCPWM Interrupt Flags set address
  138. * - MCPWM Interrupt Flags clear address
  139. */
  140. /** Limit interrupt for channel (n) */
  141. #define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
  142. /** Match interrupt for channel (n) */
  143. #define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
  144. /** Capture interrupt for channel (n) */
  145. #define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
  146. /** Fast abort interrupt */
  147. #define MCPWM_INT_ABORT ((uint32_t)(1<<15))
  148. /*********************************************************************//**
  149. * Macro defines for MCPWM Count Control register
  150. **********************************************************************/
  151. /* MCPWM Count Control register, these macro definitions below can be applied for these
  152. * register type:
  153. * - MCPWM Count Control read address
  154. * - MCPWM Count Control set address
  155. * - MCPWM Count Control clear address
  156. */
  157. /** Counter(tc) advances on a rising edge on MCI(mci) pin */
  158. #define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
  159. /** Counter(cnt) advances on a falling edge on MCI(mci) pin */
  160. #define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc<=2)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
  161. /** Channel (n) is in counter mode */
  162. #define MCPWM_CNTCON_CNTR(n) ((n<=2) ? ((uint32_t)(1<<(29+n))) : (0))
  163. /*********************************************************************//**
  164. * Macro defines for MCPWM Dead-time register
  165. **********************************************************************/
  166. /** Dead time value x for channel n */
  167. #define MCPWM_DT(n,x) ((n<=2) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
  168. /*********************************************************************//**
  169. * Macro defines for MCPWM Communication Pattern register
  170. **********************************************************************/
  171. #define MCPWM_CP_A0 ((uint32_t)(1<<0)) /**< MCOA0 tracks internal MCOA0 */
  172. #define MCPWM_CP_B0 ((uint32_t)(1<<1)) /**< MCOB0 tracks internal MCOA0 */
  173. #define MCPWM_CP_A1 ((uint32_t)(1<<2)) /**< MCOA1 tracks internal MCOA0 */
  174. #define MCPWM_CP_B1 ((uint32_t)(1<<3)) /**< MCOB1 tracks internal MCOA0 */
  175. #define MCPWM_CP_A2 ((uint32_t)(1<<4)) /**< MCOA2 tracks internal MCOA0 */
  176. #define MCPWM_CP_B2 ((uint32_t)(1<<5)) /**< MCOB2 tracks internal MCOA0 */
  177. /*********************************************************************//**
  178. * Macro defines for MCPWM Capture clear address register
  179. **********************************************************************/
  180. /** Clear the MCCAP (n) register */
  181. #define MCPWM_CAPCLR_CAP(n) ((n<=2) ? ((uint32_t)(1<<n)) : (0))
  182. /**
  183. * @}
  184. */
  185. /* Public Types --------------------------------------------------------------- */
  186. /** @defgroup MCPWM_Public_Types MCPWM Public Types
  187. * @{
  188. */
  189. /**
  190. * @brief Motor Control PWM Channel Configuration structure type definition
  191. */
  192. typedef struct {
  193. uint32_t channelType; /**< Edge/center aligned mode for this channel,
  194. should be:
  195. - MCPWM_CHANNEL_EDGE_MODE: Channel is in Edge mode
  196. - MCPWM_CHANNEL_CENTER_MODE: Channel is in Center mode
  197. */
  198. uint32_t channelPolarity; /**< Polarity of the MCOA and MCOB pins, should be:
  199. - MCPWM_CHANNEL_PASSIVE_LO: Passive state is LOW, active state is HIGH
  200. - MCPWM_CHANNEL_PASSIVE_HI: Passive state is HIGH, active state is LOW
  201. */
  202. uint32_t channelDeadtimeEnable; /**< Enable/Disable DeadTime function for channel, should be:
  203. - ENABLE.
  204. - DISABLE.
  205. */
  206. uint32_t channelDeadtimeValue; /**< DeadTime value, should be less than 0x3FF */
  207. uint32_t channelUpdateEnable; /**< Enable/Disable updates of functional registers,
  208. should be:
  209. - ENABLE.
  210. - DISABLE.
  211. */
  212. uint32_t channelTimercounterValue; /**< MCPWM Timer Counter value */
  213. uint32_t channelPeriodValue; /**< MCPWM Period value */
  214. uint32_t channelPulsewidthValue; /**< MCPWM Pulse Width value */
  215. } MCPWM_CHANNEL_CFG_Type;
  216. /**
  217. * @brief MCPWM Capture Configuration type definition
  218. */
  219. typedef struct {
  220. uint32_t captureChannel; /**< Capture Channel Number, should be in range from 0 to 2 */
  221. uint32_t captureRising; /**< Enable/Disable Capture on Rising Edge event, should be:
  222. - ENABLE.
  223. - DISABLE.
  224. */
  225. uint32_t captureFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
  226. - ENABLE.
  227. - DISABLE.
  228. */
  229. uint32_t timerReset; /**< Enable/Disable Timer reset function an capture, should be:
  230. - ENABLE.
  231. - DISABLE.
  232. */
  233. uint32_t hnfEnable; /**< Enable/Disable Hardware noise filter function, should be:
  234. - ENABLE.
  235. - DISABLE.
  236. */
  237. } MCPWM_CAPTURE_CFG_Type;
  238. /**
  239. * @brief MCPWM Count Control Configuration type definition
  240. */
  241. typedef struct {
  242. uint32_t counterChannel; /**< Counter Channel Number, should be in range from 0 to 2 */
  243. uint32_t countRising; /**< Enable/Disable Capture on Rising Edge event, should be:
  244. - ENABLE.
  245. - DISABLE.
  246. */
  247. uint32_t countFalling; /**< Enable/Disable Capture on Falling Edge event, should be:
  248. - ENABLE.
  249. - DISABLE.
  250. */
  251. } MCPWM_COUNT_CFG_Type;
  252. /**
  253. * @}
  254. */
  255. /* Public Functions ----------------------------------------------------------- */
  256. /** @defgroup MCPWM_Public_Functions MCPWM Public Functions
  257. * @{
  258. */
  259. void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
  260. void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
  261. MCPWM_CHANNEL_CFG_Type * channelSetup);
  262. void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
  263. MCPWM_CHANNEL_CFG_Type *channelSetup);
  264. void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
  265. MCPWM_CAPTURE_CFG_Type *captureConfig);
  266. void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
  267. uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
  268. void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
  269. uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
  270. void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
  271. void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
  272. void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
  273. void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
  274. uint32_t outputInvered, uint32_t outputPattern);
  275. void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
  276. void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
  277. void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
  278. FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
  279. /**
  280. * @}
  281. */
  282. #ifdef __cplusplus
  283. }
  284. #endif
  285. #endif /* LPC17XX_MCPWM_H_ */
  286. /**
  287. * @}
  288. */
  289. /* --------------------------------- End Of File ------------------------------ */