My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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lpc17xx_ssp.h 18KB

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  1. /**********************************************************************
  2. * $Id$ lpc17xx_ssp.h 2010-06-18
  3. *//**
  4. * @file lpc17xx_ssp.h
  5. * @brief Contains all macro definitions and function prototypes
  6. * support for SSP firmware library on LPC17xx
  7. * @version 3.0
  8. * @date 18. June. 2010
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2010, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @defgroup SSP SSP (Synchronous Serial Port)
  34. * @ingroup LPC1700CMSIS_FwLib_Drivers
  35. * @{
  36. */
  37. #ifndef LPC17XX_SSP_H_
  38. #define LPC17XX_SSP_H_
  39. /* Includes ------------------------------------------------------------------- */
  40. #include "LPC17xx.h"
  41. #include "lpc_types.h"
  42. #ifdef __cplusplus
  43. extern "C"
  44. {
  45. #endif
  46. /* Public Macros -------------------------------------------------------------- */
  47. /** @defgroup SSP_Public_Macros SSP Public Macros
  48. * @{
  49. */
  50. /*********************************************************************//**
  51. * SSP configuration parameter defines
  52. **********************************************************************/
  53. /** Clock phase control bit */
  54. #define SSP_CPHA_FIRST ((uint32_t)(0))
  55. #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND
  56. /** Clock polarity control bit */
  57. /* There's no bug here!!!
  58. * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
  59. * That means the active clock is in HI state.
  60. * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
  61. * high between frames. That means the active clock is in LO state.
  62. */
  63. #define SSP_CPOL_HI ((uint32_t)(0))
  64. #define SSP_CPOL_LO SSP_CR0_CPOL_HI
  65. /** SSP master mode enable */
  66. #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN
  67. #define SSP_MASTER_MODE ((uint32_t)(0))
  68. /** SSP data bit number defines */
  69. #define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */
  70. #define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */
  71. #define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */
  72. #define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */
  73. #define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */
  74. #define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */
  75. #define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */
  76. #define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */
  77. #define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */
  78. #define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */
  79. #define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */
  80. #define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */
  81. #define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */
  82. /** SSP Frame Format definition */
  83. /** Motorola SPI mode */
  84. #define SSP_FRAME_SPI SSP_CR0_FRF_SPI
  85. /** TI synchronous serial mode */
  86. #define SSP_FRAME_TI SSP_CR0_FRF_TI
  87. /** National Micro-wire mode */
  88. #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE
  89. /*********************************************************************//**
  90. * SSP Status defines
  91. **********************************************************************/
  92. /** SSP status TX FIFO Empty bit */
  93. #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE
  94. /** SSP status TX FIFO not full bit */
  95. #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF
  96. /** SSP status RX FIFO not empty bit */
  97. #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE
  98. /** SSP status RX FIFO full bit */
  99. #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF
  100. /** SSP status SSP Busy bit */
  101. #define SSP_STAT_BUSY SSP_SR_BSY
  102. /*********************************************************************//**
  103. * SSP Interrupt Configuration defines
  104. **********************************************************************/
  105. /** Receive Overrun */
  106. #define SSP_INTCFG_ROR SSP_IMSC_ROR
  107. /** Receive TimeOut */
  108. #define SSP_INTCFG_RT SSP_IMSC_RT
  109. /** Rx FIFO is at least half full */
  110. #define SSP_INTCFG_RX SSP_IMSC_RX
  111. /** Tx FIFO is at least half empty */
  112. #define SSP_INTCFG_TX SSP_IMSC_TX
  113. /*********************************************************************//**
  114. * SSP Configured Interrupt Status defines
  115. **********************************************************************/
  116. /** Receive Overrun */
  117. #define SSP_INTSTAT_ROR SSP_MIS_ROR
  118. /** Receive TimeOut */
  119. #define SSP_INTSTAT_RT SSP_MIS_RT
  120. /** Rx FIFO is at least half full */
  121. #define SSP_INTSTAT_RX SSP_MIS_RX
  122. /** Tx FIFO is at least half empty */
  123. #define SSP_INTSTAT_TX SSP_MIS_TX
  124. /*********************************************************************//**
  125. * SSP Raw Interrupt Status defines
  126. **********************************************************************/
  127. /** Receive Overrun */
  128. #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR
  129. /** Receive TimeOut */
  130. #define SSP_INTSTAT_RAW_RT SSP_RIS_RT
  131. /** Rx FIFO is at least half full */
  132. #define SSP_INTSTAT_RAW_RX SSP_RIS_RX
  133. /** Tx FIFO is at least half empty */
  134. #define SSP_INTSTAT_RAW_TX SSP_RIS_TX
  135. /*********************************************************************//**
  136. * SSP Interrupt Clear defines
  137. **********************************************************************/
  138. /** Writing a 1 to this bit clears the "frame was received when
  139. * RxFIFO was full" interrupt */
  140. #define SSP_INTCLR_ROR SSP_ICR_ROR
  141. /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
  142. * has not been read for a timeout period" interrupt */
  143. #define SSP_INTCLR_RT SSP_ICR_RT
  144. /*********************************************************************//**
  145. * SSP DMA defines
  146. **********************************************************************/
  147. /** SSP bit for enabling RX DMA */
  148. #define SSP_DMA_RX SSP_DMA_RXDMA_EN
  149. /** SSP bit for enabling TX DMA */
  150. #define SSP_DMA_TX SSP_DMA_TXDMA_EN
  151. /* SSP Status Implementation definitions */
  152. #define SSP_STAT_DONE (1UL<<8) /**< Done */
  153. #define SSP_STAT_ERROR (1UL<<9) /**< Error */
  154. /**
  155. * @}
  156. */
  157. /* Private Macros ------------------------------------------------------------- */
  158. /** @defgroup SSP_Private_Macros SSP Private Macros
  159. * @{
  160. */
  161. /* --------------------- BIT DEFINITIONS -------------------------------------- */
  162. /*********************************************************************//**
  163. * Macro defines for CR0 register
  164. **********************************************************************/
  165. /** SSP data size select, must be 4 bits to 16 bits */
  166. #define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF))
  167. /** SSP control 0 Motorola SPI mode */
  168. #define SSP_CR0_FRF_SPI ((uint32_t)(0<<4))
  169. /** SSP control 0 TI synchronous serial mode */
  170. #define SSP_CR0_FRF_TI ((uint32_t)(1<<4))
  171. /** SSP control 0 National Micro-wire mode */
  172. #define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4))
  173. /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the
  174. bus clock high between frames, (0) = low */
  175. #define SSP_CR0_CPOL_HI ((uint32_t)(1<<6))
  176. /** SPI clock out phase bit (used in SPI mode only), (1) = captures data
  177. on the second clock transition of the frame, (0) = first */
  178. #define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))
  179. /** SSP serial clock rate value load macro, divider rate is
  180. PERIPH_CLK / (cpsr * (SCR + 1)) */
  181. #define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8))
  182. /** SSP CR0 bit mask */
  183. #define SSP_CR0_BITMASK ((uint32_t)(0xFFFF))
  184. /*********************************************************************//**
  185. * Macro defines for CR1 register
  186. **********************************************************************/
  187. /** SSP control 1 loopback mode enable bit */
  188. #define SSP_CR1_LBM_EN ((uint32_t)(1<<0))
  189. /** SSP control 1 enable bit */
  190. #define SSP_CR1_SSP_EN ((uint32_t)(1<<1))
  191. /** SSP control 1 slave enable */
  192. #define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2))
  193. /** SSP control 1 slave out disable bit, disables transmit line in slave
  194. mode */
  195. #define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3))
  196. /** SSP CR1 bit mask */
  197. #define SSP_CR1_BITMASK ((uint32_t)(0x0F))
  198. /*********************************************************************//**
  199. * Macro defines for DR register
  200. **********************************************************************/
  201. /** SSP data bit mask */
  202. #define SSP_DR_BITMASK(n) ((n)&0xFFFF)
  203. /*********************************************************************//**
  204. * Macro defines for SR register
  205. **********************************************************************/
  206. /** SSP status TX FIFO Empty bit */
  207. #define SSP_SR_TFE ((uint32_t)(1<<0))
  208. /** SSP status TX FIFO not full bit */
  209. #define SSP_SR_TNF ((uint32_t)(1<<1))
  210. /** SSP status RX FIFO not empty bit */
  211. #define SSP_SR_RNE ((uint32_t)(1<<2))
  212. /** SSP status RX FIFO full bit */
  213. #define SSP_SR_RFF ((uint32_t)(1<<3))
  214. /** SSP status SSP Busy bit */
  215. #define SSP_SR_BSY ((uint32_t)(1<<4))
  216. /** SSP SR bit mask */
  217. #define SSP_SR_BITMASK ((uint32_t)(0x1F))
  218. /*********************************************************************//**
  219. * Macro defines for CPSR register
  220. **********************************************************************/
  221. /** SSP clock prescaler */
  222. #define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF))
  223. /** SSP CPSR bit mask */
  224. #define SSP_CPSR_BITMASK ((uint32_t)(0xFF))
  225. /*********************************************************************//**
  226. * Macro define for (IMSC) Interrupt Mask Set/Clear registers
  227. **********************************************************************/
  228. /** Receive Overrun */
  229. #define SSP_IMSC_ROR ((uint32_t)(1<<0))
  230. /** Receive TimeOut */
  231. #define SSP_IMSC_RT ((uint32_t)(1<<1))
  232. /** Rx FIFO is at least half full */
  233. #define SSP_IMSC_RX ((uint32_t)(1<<2))
  234. /** Tx FIFO is at least half empty */
  235. #define SSP_IMSC_TX ((uint32_t)(1<<3))
  236. /** IMSC bit mask */
  237. #define SSP_IMSC_BITMASK ((uint32_t)(0x0F))
  238. /*********************************************************************//**
  239. * Macro define for (RIS) Raw Interrupt Status registers
  240. **********************************************************************/
  241. /** Receive Overrun */
  242. #define SSP_RIS_ROR ((uint32_t)(1<<0))
  243. /** Receive TimeOut */
  244. #define SSP_RIS_RT ((uint32_t)(1<<1))
  245. /** Rx FIFO is at least half full */
  246. #define SSP_RIS_RX ((uint32_t)(1<<2))
  247. /** Tx FIFO is at least half empty */
  248. #define SSP_RIS_TX ((uint32_t)(1<<3))
  249. /** RIS bit mask */
  250. #define SSP_RIS_BITMASK ((uint32_t)(0x0F))
  251. /*********************************************************************//**
  252. * Macro define for (MIS) Masked Interrupt Status registers
  253. **********************************************************************/
  254. /** Receive Overrun */
  255. #define SSP_MIS_ROR ((uint32_t)(1<<0))
  256. /** Receive TimeOut */
  257. #define SSP_MIS_RT ((uint32_t)(1<<1))
  258. /** Rx FIFO is at least half full */
  259. #define SSP_MIS_RX ((uint32_t)(1<<2))
  260. /** Tx FIFO is at least half empty */
  261. #define SSP_MIS_TX ((uint32_t)(1<<3))
  262. /** MIS bit mask */
  263. #define SSP_MIS_BITMASK ((uint32_t)(0x0F))
  264. /*********************************************************************//**
  265. * Macro define for (ICR) Interrupt Clear registers
  266. **********************************************************************/
  267. /** Writing a 1 to this bit clears the "frame was received when
  268. * RxFIFO was full" interrupt */
  269. #define SSP_ICR_ROR ((uint32_t)(1<<0))
  270. /** Writing a 1 to this bit clears the "Rx FIFO was not empty and
  271. * has not been read for a timeout period" interrupt */
  272. #define SSP_ICR_RT ((uint32_t)(1<<1))
  273. /** ICR bit mask */
  274. #define SSP_ICR_BITMASK ((uint32_t)(0x03))
  275. /*********************************************************************//**
  276. * Macro defines for DMACR register
  277. **********************************************************************/
  278. /** SSP bit for enabling RX DMA */
  279. #define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0))
  280. /** SSP bit for enabling TX DMA */
  281. #define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1))
  282. /** DMACR bit mask */
  283. #define SSP_DMA_BITMASK ((uint32_t)(0x03))
  284. /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
  285. /** Macro to determine if it is valid SSP port number */
  286. #define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
  287. || (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))
  288. /** Macro check clock phase control mode */
  289. #define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))
  290. /** Macro check clock polarity mode */
  291. #define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))
  292. /* Macro check master/slave mode */
  293. #define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))
  294. /* Macro check databit value */
  295. #define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
  296. || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
  297. || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
  298. || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
  299. || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
  300. || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
  301. || (n==SSP_DATABIT_15))
  302. /* Macro check frame type */
  303. #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
  304. || (n==SSP_FRAME_MICROWIRE))
  305. /* Macro check SSP status */
  306. #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
  307. || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
  308. || (n==SSP_STAT_BUSY))
  309. /* Macro check interrupt configuration */
  310. #define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
  311. || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))
  312. /* Macro check interrupt status value */
  313. #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
  314. || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))
  315. /* Macro check interrupt status raw value */
  316. #define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
  317. || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))
  318. /* Macro check interrupt clear mode */
  319. #define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))
  320. /* Macro check DMA mode */
  321. #define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))
  322. /**
  323. * @}
  324. */
  325. /* Public Types --------------------------------------------------------------- */
  326. /** @defgroup SSP_Public_Types SSP Public Types
  327. * @{
  328. */
  329. /** @brief SSP configuration structure */
  330. typedef struct {
  331. uint32_t Databit; /** Databit number, should be SSP_DATABIT_x,
  332. where x is in range from 4 - 16 */
  333. uint32_t CPHA; /** Clock phase, should be:
  334. - SSP_CPHA_FIRST: first clock edge
  335. - SSP_CPHA_SECOND: second clock edge */
  336. uint32_t CPOL; /** Clock polarity, should be:
  337. - SSP_CPOL_HI: high level
  338. - SSP_CPOL_LO: low level */
  339. uint32_t Mode; /** SSP mode, should be:
  340. - SSP_MASTER_MODE: Master mode
  341. - SSP_SLAVE_MODE: Slave mode */
  342. uint32_t FrameFormat; /** Frame Format:
  343. - SSP_FRAME_SPI: Motorola SPI frame format
  344. - SSP_FRAME_TI: TI frame format
  345. - SSP_FRAME_MICROWIRE: National Microwire frame format */
  346. uint32_t ClockRate; /** Clock rate,in Hz */
  347. } SSP_CFG_Type;
  348. /**
  349. * @brief SSP Transfer Type definitions
  350. */
  351. typedef enum {
  352. SSP_TRANSFER_POLLING = 0, /**< Polling transfer */
  353. SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */
  354. } SSP_TRANSFER_Type;
  355. /**
  356. * @brief SPI Data configuration structure definitions
  357. */
  358. typedef struct {
  359. void *tx_data; /**< Pointer to transmit data */
  360. uint32_t tx_cnt; /**< Transmit counter */
  361. void *rx_data; /**< Pointer to transmit data */
  362. uint32_t rx_cnt; /**< Receive counter */
  363. uint32_t length; /**< Length of transfer data */
  364. uint32_t status; /**< Current status of SSP activity */
  365. } SSP_DATA_SETUP_Type;
  366. /**
  367. * @}
  368. */
  369. /* Public Functions ----------------------------------------------------------- */
  370. /** @defgroup SSP_Public_Functions SSP Public Functions
  371. * @{
  372. */
  373. /* SSP Init/DeInit functions --------------------------------------------------*/
  374. void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
  375. void SSP_DeInit(LPC_SSP_TypeDef* SSPx);
  376. /* SSP configure functions ----------------------------------------------------*/
  377. void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);
  378. /* SSP enable/disable functions -----------------------------------------------*/
  379. void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
  380. void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
  381. void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
  382. void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);
  383. /* SSP get information functions ----------------------------------------------*/
  384. FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
  385. uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
  386. IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
  387. uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
  388. IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);
  389. /* SSP transfer data functions ------------------------------------------------*/
  390. void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
  391. uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
  392. int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
  393. SSP_TRANSFER_Type xfType);
  394. /* SSP IRQ function ------------------------------------------------------------*/
  395. void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
  396. void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);
  397. /**
  398. * @}
  399. */
  400. #ifdef __cplusplus
  401. }
  402. #endif
  403. #endif /* LPC17XX_SSP_H_ */
  404. /**
  405. * @}
  406. */
  407. /* --------------------------------- End Of File ------------------------------ */