My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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lpc17xx_i2s.h 15KB

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  1. /**********************************************************************
  2. * $Id$ lpc17xx_i2s.h 2011-06-06
  3. *//**
  4. * @file lpc17xx_i2s.h
  5. * @brief Contains all macro definitions and function prototypes
  6. * support for I2S firmware library on LPC17xx
  7. * @version 3.1
  8. * @date 06. June. 2011
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2011, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @defgroup I2S I2S (Inter-IC Sound bus)
  34. * @ingroup LPC1700CMSIS_FwLib_Drivers
  35. * @{
  36. */
  37. #ifndef LPC17XX_I2S_H_
  38. #define LPC17XX_I2S_H_
  39. /* Includes ------------------------------------------------------------------- */
  40. #include "LPC17xx.h"
  41. #include "lpc_types.h"
  42. #ifdef __cplusplus
  43. extern "C"
  44. {
  45. #endif
  46. /* Public Macros -------------------------------------------------------------- */
  47. /** @defgroup I2S_Public_Macros I2S Public Macros
  48. * @{
  49. */
  50. /*********************************************************************//**
  51. * I2S configuration parameter defines
  52. **********************************************************************/
  53. /** I2S Wordwidth bit */
  54. #define I2S_WORDWIDTH_8 ((uint32_t)(0))
  55. #define I2S_WORDWIDTH_16 ((uint32_t)(1))
  56. #define I2S_WORDWIDTH_32 ((uint32_t)(3))
  57. /** I2S Channel bit */
  58. #define I2S_STEREO ((uint32_t)(0))
  59. #define I2S_MONO ((uint32_t)(1))
  60. /** I2S Master/Slave mode bit */
  61. #define I2S_MASTER_MODE ((uint8_t)(0))
  62. #define I2S_SLAVE_MODE ((uint8_t)(1))
  63. /** I2S Stop bit */
  64. #define I2S_STOP_ENABLE ((uint8_t)(1))
  65. #define I2S_STOP_DISABLE ((uint8_t)(0))
  66. /** I2S Reset bit */
  67. #define I2S_RESET_ENABLE ((uint8_t)(1))
  68. #define I2S_RESET_DISABLE ((uint8_t)(0))
  69. /** I2S Mute bit */
  70. #define I2S_MUTE_ENABLE ((uint8_t)(1))
  71. #define I2S_MUTE_DISABLE ((uint8_t)(0))
  72. /** I2S Transmit/Receive bit */
  73. #define I2S_TX_MODE ((uint8_t)(0))
  74. #define I2S_RX_MODE ((uint8_t)(1))
  75. /** I2S Clock Select bit */
  76. #define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
  77. #define I2S_CLKSEL_MCLK ((uint8_t)(2))
  78. /** I2S 4-pin Mode bit */
  79. #define I2S_4PIN_ENABLE ((uint8_t)(1))
  80. #define I2S_4PIN_DISABLE ((uint8_t)(0))
  81. /** I2S MCLK Enable bit */
  82. #define I2S_MCLK_ENABLE ((uint8_t)(1))
  83. #define I2S_MCLK_DISABLE ((uint8_t)(0))
  84. /** I2S select DMA bit */
  85. #define I2S_DMA_1 ((uint8_t)(0))
  86. #define I2S_DMA_2 ((uint8_t)(1))
  87. /**
  88. * @}
  89. */
  90. /* Private Macros ------------------------------------------------------------- */
  91. /** @defgroup I2S_Private_Macros I2S Private Macros
  92. * @{
  93. */
  94. /*********************************************************************//**
  95. * Macro defines for DAO-Digital Audio Output register
  96. **********************************************************************/
  97. /** I2S wordwide - the number of bytes in data*/
  98. #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
  99. #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
  100. #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
  101. /** I2S control mono or stereo format */
  102. #define I2S_DAO_MONO ((uint32_t)(1<<2))
  103. /** I2S control stop mode */
  104. #define I2S_DAO_STOP ((uint32_t)(1<<3))
  105. /** I2S control reset mode */
  106. #define I2S_DAO_RESET ((uint32_t)(1<<4))
  107. /** I2S control master/slave mode */
  108. #define I2S_DAO_SLAVE ((uint32_t)(1<<5))
  109. /** I2S word select half period minus one */
  110. #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
  111. /** I2S control mute mode */
  112. #define I2S_DAO_MUTE ((uint32_t)(1<<15))
  113. /*********************************************************************//**
  114. * Macro defines for DAI-Digital Audio Input register
  115. **********************************************************************/
  116. /** I2S wordwide - the number of bytes in data*/
  117. #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
  118. #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
  119. #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
  120. /** I2S control mono or stereo format */
  121. #define I2S_DAI_MONO ((uint32_t)(1<<2))
  122. /** I2S control stop mode */
  123. #define I2S_DAI_STOP ((uint32_t)(1<<3))
  124. /** I2S control reset mode */
  125. #define I2S_DAI_RESET ((uint32_t)(1<<4))
  126. /** I2S control master/slave mode */
  127. #define I2S_DAI_SLAVE ((uint32_t)(1<<5))
  128. /** I2S word select half period minus one (9 bits)*/
  129. #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
  130. /** I2S control mute mode */
  131. #define I2S_DAI_MUTE ((uint32_t)(1<<15))
  132. /*********************************************************************//**
  133. * Macro defines for STAT register (Status Feedback register)
  134. **********************************************************************/
  135. /** I2S Status Receive or Transmit Interrupt */
  136. #define I2S_STATE_IRQ ((uint32_t)(1))
  137. /** I2S Status Receive or Transmit DMA1 */
  138. #define I2S_STATE_DMA1 ((uint32_t)(1<<1))
  139. /** I2S Status Receive or Transmit DMA2 */
  140. #define I2S_STATE_DMA2 ((uint32_t)(1<<2))
  141. /** I2S Status Current level of the Receive FIFO (5 bits)*/
  142. #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
  143. /** I2S Status Current level of the Transmit FIFO (5 bits)*/
  144. #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
  145. /*********************************************************************//**
  146. * Macro defines for DMA1 register (DMA1 Configuration register)
  147. **********************************************************************/
  148. /** I2S control DMA1 for I2S receive */
  149. #define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
  150. /** I2S control DMA1 for I2S transmit */
  151. #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
  152. /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
  153. #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
  154. /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
  155. #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
  156. /*********************************************************************//**
  157. * Macro defines for DMA2 register (DMA2 Configuration register)
  158. **********************************************************************/
  159. /** I2S control DMA2 for I2S receive */
  160. #define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
  161. /** I2S control DMA1 for I2S transmit */
  162. #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
  163. /** I2S set FIFO level that trigger a receive DMA request on DMA1 */
  164. #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
  165. /** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
  166. #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
  167. /*********************************************************************//**
  168. * Macro defines for IRQ register (Interrupt Request Control register)
  169. **********************************************************************/
  170. /** I2S control I2S receive interrupt */
  171. #define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
  172. /** I2S control I2S transmit interrupt */
  173. #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
  174. /** I2S set the FIFO level on which to create an irq request */
  175. #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
  176. /** I2S set the FIFO level on which to create an irq request */
  177. #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
  178. /********************************************************************************//**
  179. * Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
  180. *********************************************************************************/
  181. /** I2S Transmit MCLK rate denominator */
  182. #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
  183. /** I2S Transmit MCLK rate denominator */
  184. #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
  185. /** I2S Receive MCLK rate denominator */
  186. #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
  187. /** I2S Receive MCLK rate denominator */
  188. #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
  189. /*************************************************************************************//**
  190. * Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
  191. **************************************************************************************/
  192. #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
  193. #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
  194. /**********************************************************************************//**
  195. * Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
  196. ************************************************************************************/
  197. /** I2S Transmit select clock source (2 bits)*/
  198. #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
  199. /** I2S Transmit control 4-pin mode */
  200. #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
  201. /** I2S Transmit control the TX_MCLK output */
  202. #define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
  203. /** I2S Receive select clock source */
  204. #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
  205. /** I2S Receive control 4-pin mode */
  206. #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
  207. /** I2S Receive control the TX_MCLK output */
  208. #define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
  209. /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
  210. /** Macro to determine if it is valid I2S peripheral */
  211. #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S))
  212. /** Macro to check Data to send valid */
  213. #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
  214. /* Macro check I2S word width type */
  215. #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
  216. ||(n==I2S_WORDWIDTH_32))
  217. /* Macro check I2S channel type */
  218. #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
  219. /* Macro check I2S master/slave mode */
  220. #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
  221. /* Macro check I2S stop mode */
  222. #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
  223. /* Macro check I2S reset mode */
  224. #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
  225. /* Macro check I2S reset mode */
  226. #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
  227. /* Macro check I2S transmit/receive mode */
  228. #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
  229. /* Macro check I2S clock select mode */
  230. #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
  231. /* Macro check I2S 4-pin mode */
  232. #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
  233. /* Macro check I2S MCLK mode */
  234. #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
  235. /* Macro check I2S DMA mode */
  236. #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
  237. /* Macro check I2S DMA depth value */
  238. #define PARAM_I2S_DMA_DEPTH(n) (n<=31)
  239. /* Macro check I2S irq level value */
  240. #define PARAM_I2S_IRQ_LEVEL(n) (n<=31)
  241. /* Macro check I2S half-period value */
  242. #define PARAM_I2S_HALFPERIOD(n) (n<512)
  243. /* Macro check I2S bit-rate value */
  244. #define PARAM_I2S_BITRATE(n) (n<=63)
  245. /**
  246. * @}
  247. */
  248. /* Public Types --------------------------------------------------------------- */
  249. /** @defgroup I2S_Public_Types I2S Public Types
  250. * @{
  251. */
  252. /**
  253. * @brief I2S configuration structure definition
  254. */
  255. typedef struct {
  256. uint8_t wordwidth; /** the number of bytes in data as follow:
  257. -I2S_WORDWIDTH_8: 8 bit data
  258. -I2S_WORDWIDTH_16: 16 bit data
  259. -I2S_WORDWIDTH_32: 32 bit data */
  260. uint8_t mono; /** Set mono/stereo mode, should be:
  261. - I2S_STEREO: stereo mode
  262. - I2S_MONO: mono mode */
  263. uint8_t stop; /** Disables accesses on FIFOs, should be:
  264. - I2S_STOP_ENABLE: enable stop mode
  265. - I2S_STOP_DISABLE: disable stop mode */
  266. uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
  267. - I2S_RESET_ENABLE: enable reset mode
  268. - I2S_RESET_DISABLE: disable reset mode */
  269. uint8_t ws_sel; /** Set Master/Slave mode, should be:
  270. - I2S_MASTER_MODE: I2S master mode
  271. - I2S_SLAVE_MODE: I2S slave mode */
  272. uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
  273. - I2S_MUTE_ENABLE: enable mute mode
  274. - I2S_MUTE_DISABLE: disable mute mode */
  275. uint8_t Reserved0[2];
  276. } I2S_CFG_Type;
  277. /**
  278. * @brief I2S DMA configuration structure definition
  279. */
  280. typedef struct {
  281. uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
  282. - I2S_DMA_1: DMA1
  283. - I2S_DMA_2: DMA2 */
  284. uint8_t depth; /** FIFO level that triggers a DMA request */
  285. uint8_t Reserved0[2];
  286. }I2S_DMAConf_Type;
  287. /**
  288. * @brief I2S mode configuration structure definition
  289. */
  290. typedef struct{
  291. uint8_t clksel; /** Clock source selection, should be:
  292. - I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
  293. - I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
  294. uint8_t fpin; /** Select four pin mode, should be:
  295. - I2S_4PIN_ENABLE: 4-pin enable
  296. - I2S_4PIN_DISABLE: 4-pin disable */
  297. uint8_t mcena; /** Select MCLK mode, should be:
  298. - I2S_MCLK_ENABLE: MCLK enable for output
  299. - I2S_MCLK_DISABLE: MCLK disable for output */
  300. uint8_t Reserved;
  301. }I2S_MODEConf_Type;
  302. /**
  303. * @}
  304. */
  305. /* Public Functions ----------------------------------------------------------- */
  306. /** @defgroup I2S_Public_Functions I2S Public Functions
  307. * @{
  308. */
  309. /* I2S Init/DeInit functions ---------*/
  310. void I2S_Init(LPC_I2S_TypeDef *I2Sx);
  311. void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
  312. /* I2S configuration functions --------*/
  313. void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
  314. Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
  315. void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
  316. void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
  317. uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
  318. /* I2S operate functions -------------*/
  319. void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
  320. uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
  321. void I2S_Start(LPC_I2S_TypeDef *I2Sx);
  322. void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
  323. void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
  324. void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
  325. /* I2S DMA functions ----------------*/
  326. void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
  327. void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
  328. /* I2S IRQ functions ----------------*/
  329. void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
  330. void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
  331. FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
  332. uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
  333. /**
  334. * @}
  335. */
  336. #ifdef __cplusplus
  337. }
  338. #endif
  339. #endif /* LPC17XX_SSP_H_ */
  340. /**
  341. * @}
  342. */
  343. /* --------------------------------- End Of File ------------------------------ */