My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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timers.cpp 3.8KB

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  1. /**
  2. * Marlin 3D Printer Firmware
  3. * Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
  4. *
  5. * Based on Sprinter and grbl.
  6. * Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
  7. *
  8. * This program is free software: you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation, either version 3 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <https://www.gnu.org/licenses/>.
  20. *
  21. */
  22. /**
  23. * HAL Timers for Teensy 4.0 (IMXRT1062DVL6A) / 4.1 (IMXRT1062DVJ6A)
  24. */
  25. #ifdef __IMXRT1062__
  26. #include "../../inc/MarlinConfig.h"
  27. void HAL_timer_start(const uint8_t timer_num, const uint32_t frequency) {
  28. switch (timer_num) {
  29. case MF_TIMER_STEP:
  30. CCM_CSCMR1 &= ~CCM_CSCMR1_PERCLK_CLK_SEL; // turn off 24mhz mode
  31. CCM_CCGR1 |= CCM_CCGR1_GPT1_BUS(CCM_CCGR_ON);
  32. GPT1_CR = 0; // disable timer
  33. GPT1_SR = 0x3F; // clear all prior status
  34. GPT1_PR = GPT1_TIMER_PRESCALE - 1;
  35. GPT1_CR |= GPT_CR_CLKSRC(1); //clock selection #1 (peripheral clock = 150 MHz)
  36. GPT1_CR |= GPT_CR_ENMOD; //reset count to zero before enabling
  37. GPT1_CR |= GPT_CR_OM1(1); // toggle mode
  38. GPT1_OCR1 = (GPT1_TIMER_RATE / frequency) -1; // Initial compare value
  39. GPT1_IR = GPT_IR_OF1IE; // Compare3 value
  40. GPT1_CR |= GPT_CR_EN; //enable GPT2 counting at 150 MHz
  41. OUT_WRITE(15, HIGH);
  42. attachInterruptVector(IRQ_GPT1, &stepTC_Handler);
  43. NVIC_SET_PRIORITY(IRQ_GPT1, 16);
  44. break;
  45. case MF_TIMER_TEMP:
  46. CCM_CSCMR1 &= ~CCM_CSCMR1_PERCLK_CLK_SEL; // turn off 24mhz mode
  47. CCM_CCGR0 |= CCM_CCGR0_GPT2_BUS(CCM_CCGR_ON);
  48. GPT2_CR = 0; // disable timer
  49. GPT2_SR = 0x3F; // clear all prior status
  50. GPT2_PR = GPT2_TIMER_PRESCALE - 1;
  51. GPT2_CR |= GPT_CR_CLKSRC(1); //clock selection #1 (peripheral clock = 150 MHz)
  52. GPT2_CR |= GPT_CR_ENMOD; //reset count to zero before enabling
  53. GPT2_CR |= GPT_CR_OM1(1); // toggle mode
  54. GPT2_OCR1 = (GPT2_TIMER_RATE / frequency) -1; // Initial compare value
  55. GPT2_IR = GPT_IR_OF1IE; // Compare3 value
  56. GPT2_CR |= GPT_CR_EN; //enable GPT2 counting at 150 MHz
  57. OUT_WRITE(14, HIGH);
  58. attachInterruptVector(IRQ_GPT2, &tempTC_Handler);
  59. NVIC_SET_PRIORITY(IRQ_GPT2, 32);
  60. break;
  61. }
  62. }
  63. void HAL_timer_enable_interrupt(const uint8_t timer_num) {
  64. switch (timer_num) {
  65. case MF_TIMER_STEP: NVIC_ENABLE_IRQ(IRQ_GPT1); break;
  66. case MF_TIMER_TEMP: NVIC_ENABLE_IRQ(IRQ_GPT2); break;
  67. }
  68. }
  69. void HAL_timer_disable_interrupt(const uint8_t timer_num) {
  70. switch (timer_num) {
  71. case MF_TIMER_STEP: NVIC_DISABLE_IRQ(IRQ_GPT1); break;
  72. case MF_TIMER_TEMP: NVIC_DISABLE_IRQ(IRQ_GPT2); break;
  73. }
  74. // We NEED memory barriers to ensure Interrupts are actually disabled!
  75. // ( https://dzone.com/articles/nvic-disabling-interrupts-on-arm-cortex-m-and-the )
  76. asm volatile("dsb");
  77. }
  78. bool HAL_timer_interrupt_enabled(const uint8_t timer_num) {
  79. switch (timer_num) {
  80. case MF_TIMER_STEP: return (NVIC_IS_ENABLED(IRQ_GPT1));
  81. case MF_TIMER_TEMP: return (NVIC_IS_ENABLED(IRQ_GPT2));
  82. }
  83. return false;
  84. }
  85. void HAL_timer_isr_prologue(const uint8_t timer_num) {
  86. switch (timer_num) {
  87. case MF_TIMER_STEP: GPT1_SR = GPT_IR_OF1IE; break; // clear OF3 bit
  88. case MF_TIMER_TEMP: GPT2_SR = GPT_IR_OF1IE; break; // clear OF3 bit
  89. }
  90. asm volatile("dsb");
  91. }
  92. #endif // __IMXRT1062__