My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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lpc17xx_gpdma.c 17KB

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  1. /**********************************************************************
  2. * $Id$ lpc17xx_gpdma.c 2010-03-21
  3. *//**
  4. * @file lpc17xx_gpdma.c
  5. * @brief Contains all functions support for GPDMA firmware
  6. * library on LPC17xx
  7. * @version 2.1
  8. * @date 25. July. 2011
  9. * @author NXP MCU SW Application Team
  10. *
  11. * Copyright(C) 2010, NXP Semiconductor
  12. * All rights reserved.
  13. *
  14. ***********************************************************************
  15. * Software that is described herein is for illustrative purposes only
  16. * which provides customers with programming information regarding the
  17. * products. This software is supplied "AS IS" without any warranties.
  18. * NXP Semiconductors assumes no responsibility or liability for the
  19. * use of the software, conveys no license or title under any patent,
  20. * copyright, or mask work right to the product. NXP Semiconductors
  21. * reserves the right to make changes in the software without
  22. * notification. NXP Semiconductors also make no representation or
  23. * warranty that such application will be suitable for the specified
  24. * use without further testing or modification.
  25. * Permission to use, copy, modify, and distribute this software and its
  26. * documentation is hereby granted, under NXP Semiconductors'
  27. * relevant copyright in the software, without fee, provided that it
  28. * is used in conjunction with NXP Semiconductors microcontrollers. This
  29. * copyright, permission, and disclaimer notice must appear in all copies of
  30. * this code.
  31. **********************************************************************/
  32. /* Peripheral group ----------------------------------------------------------- */
  33. /** @addtogroup GPDMA
  34. * @{
  35. */
  36. /* Includes ------------------------------------------------------------------- */
  37. #include "lpc17xx_gpdma.h"
  38. #include "lpc17xx_clkpwr.h"
  39. /* If this source file built with example, the LPC17xx FW library configuration
  40. * file in each example directory ("lpc17xx_libcfg.h") must be included,
  41. * otherwise the default FW library configuration file must be included instead
  42. */
  43. #ifdef __BUILD_WITH_EXAMPLE__
  44. #include "lpc17xx_libcfg.h"
  45. #else
  46. #include "lpc17xx_libcfg_default.h"
  47. #endif /* __BUILD_WITH_EXAMPLE__ */
  48. #ifdef _GPDMA
  49. /* Private Variables ---------------------------------------------------------- */
  50. /** @defgroup GPDMA_Private_Variables GPDMA Private Variables
  51. * @{
  52. */
  53. /**
  54. * @brief Lookup Table of Connection Type matched with
  55. * Peripheral Data (FIFO) register base address
  56. */
  57. //#ifdef __IAR_SYSTEMS_ICC__
  58. volatile const void *GPDMA_LUTPerAddr[] = {
  59. (&LPC_SSP0->DR), // SSP0 Tx
  60. (&LPC_SSP0->DR), // SSP0 Rx
  61. (&LPC_SSP1->DR), // SSP1 Tx
  62. (&LPC_SSP1->DR), // SSP1 Rx
  63. (&LPC_ADC->ADGDR), // ADC
  64. (&LPC_I2S->I2STXFIFO), // I2S Tx
  65. (&LPC_I2S->I2SRXFIFO), // I2S Rx
  66. (&LPC_DAC->DACR), // DAC
  67. (&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
  68. (&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
  69. (&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
  70. (&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
  71. (&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
  72. (&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
  73. (&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
  74. (&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
  75. (&LPC_TIM0->MR0), // MAT0.0
  76. (&LPC_TIM0->MR1), // MAT0.1
  77. (&LPC_TIM1->MR0), // MAT1.0
  78. (&LPC_TIM1->MR1), // MAT1.1
  79. (&LPC_TIM2->MR0), // MAT2.0
  80. (&LPC_TIM2->MR1), // MAT2.1
  81. (&LPC_TIM3->MR0), // MAT3.0
  82. (&LPC_TIM3->MR1) // MAT3.1
  83. };
  84. //#else
  85. //const uint32_t GPDMA_LUTPerAddr[] = {
  86. // ((uint32_t)&LPC_SSP0->DR), // SSP0 Tx
  87. // ((uint32_t)&LPC_SSP0->DR), // SSP0 Rx
  88. // ((uint32_t)&LPC_SSP1->DR), // SSP1 Tx
  89. // ((uint32_t)&LPC_SSP1->DR), // SSP1 Rx
  90. // ((uint32_t)&LPC_ADC->ADGDR), // ADC
  91. // ((uint32_t)&LPC_I2S->I2STXFIFO), // I2S Tx
  92. // ((uint32_t)&LPC_I2S->I2SRXFIFO), // I2S Rx
  93. // ((uint32_t)&LPC_DAC->DACR), // DAC
  94. // ((uint32_t)&LPC_UART0->/*RBTHDLR.*/THR), // UART0 Tx
  95. // ((uint32_t)&LPC_UART0->/*RBTHDLR.*/RBR), // UART0 Rx
  96. // ((uint32_t)&LPC_UART1->/*RBTHDLR.*/THR), // UART1 Tx
  97. // ((uint32_t)&LPC_UART1->/*RBTHDLR.*/RBR), // UART1 Rx
  98. // ((uint32_t)&LPC_UART2->/*RBTHDLR.*/THR), // UART2 Tx
  99. // ((uint32_t)&LPC_UART2->/*RBTHDLR.*/RBR), // UART2 Rx
  100. // ((uint32_t)&LPC_UART3->/*RBTHDLR.*/THR), // UART3 Tx
  101. // ((uint32_t)&LPC_UART3->/*RBTHDLR.*/RBR), // UART3 Rx
  102. // ((uint32_t)&LPC_TIM0->MR0), // MAT0.0
  103. // ((uint32_t)&LPC_TIM0->MR1), // MAT0.1
  104. // ((uint32_t)&LPC_TIM1->MR0), // MAT1.0
  105. // ((uint32_t)&LPC_TIM1->MR1), // MAT1.1
  106. // ((uint32_t)&LPC_TIM2->MR0), // MAT2.0
  107. // ((uint32_t)&LPC_TIM2->MR1), // MAT2.1
  108. // ((uint32_t)&LPC_TIM3->MR0), // MAT3.0
  109. // ((uint32_t)&LPC_TIM3->MR1) // MAT3.1
  110. //};
  111. //#endif
  112. /**
  113. * @brief Lookup Table of GPDMA Channel Number matched with
  114. * GPDMA channel pointer
  115. */
  116. const LPC_GPDMACH_TypeDef *pGPDMACh[8] = {
  117. LPC_GPDMACH0, // GPDMA Channel 0
  118. LPC_GPDMACH1, // GPDMA Channel 1
  119. LPC_GPDMACH2, // GPDMA Channel 2
  120. LPC_GPDMACH3, // GPDMA Channel 3
  121. LPC_GPDMACH4, // GPDMA Channel 4
  122. LPC_GPDMACH5, // GPDMA Channel 5
  123. LPC_GPDMACH6, // GPDMA Channel 6
  124. LPC_GPDMACH7 // GPDMA Channel 7
  125. };
  126. /**
  127. * @brief Optimized Peripheral Source and Destination burst size
  128. */
  129. const uint8_t GPDMA_LUTPerBurst[] = {
  130. GPDMA_BSIZE_4, // SSP0 Tx
  131. GPDMA_BSIZE_4, // SSP0 Rx
  132. GPDMA_BSIZE_4, // SSP1 Tx
  133. GPDMA_BSIZE_4, // SSP1 Rx
  134. GPDMA_BSIZE_1, // ADC
  135. GPDMA_BSIZE_32, // I2S channel 0
  136. GPDMA_BSIZE_32, // I2S channel 1
  137. GPDMA_BSIZE_1, // DAC
  138. GPDMA_BSIZE_1, // UART0 Tx
  139. GPDMA_BSIZE_1, // UART0 Rx
  140. GPDMA_BSIZE_1, // UART1 Tx
  141. GPDMA_BSIZE_1, // UART1 Rx
  142. GPDMA_BSIZE_1, // UART2 Tx
  143. GPDMA_BSIZE_1, // UART2 Rx
  144. GPDMA_BSIZE_1, // UART3 Tx
  145. GPDMA_BSIZE_1, // UART3 Rx
  146. GPDMA_BSIZE_1, // MAT0.0
  147. GPDMA_BSIZE_1, // MAT0.1
  148. GPDMA_BSIZE_1, // MAT1.0
  149. GPDMA_BSIZE_1, // MAT1.1
  150. GPDMA_BSIZE_1, // MAT2.0
  151. GPDMA_BSIZE_1, // MAT2.1
  152. GPDMA_BSIZE_1, // MAT3.0
  153. GPDMA_BSIZE_1 // MAT3.1
  154. };
  155. /**
  156. * @brief Optimized Peripheral Source and Destination transfer width
  157. */
  158. const uint8_t GPDMA_LUTPerWid[] = {
  159. GPDMA_WIDTH_BYTE, // SSP0 Tx
  160. GPDMA_WIDTH_BYTE, // SSP0 Rx
  161. GPDMA_WIDTH_BYTE, // SSP1 Tx
  162. GPDMA_WIDTH_BYTE, // SSP1 Rx
  163. GPDMA_WIDTH_WORD, // ADC
  164. GPDMA_WIDTH_WORD, // I2S channel 0
  165. GPDMA_WIDTH_WORD, // I2S channel 1
  166. GPDMA_WIDTH_BYTE, // DAC
  167. GPDMA_WIDTH_BYTE, // UART0 Tx
  168. GPDMA_WIDTH_BYTE, // UART0 Rx
  169. GPDMA_WIDTH_BYTE, // UART1 Tx
  170. GPDMA_WIDTH_BYTE, // UART1 Rx
  171. GPDMA_WIDTH_BYTE, // UART2 Tx
  172. GPDMA_WIDTH_BYTE, // UART2 Rx
  173. GPDMA_WIDTH_BYTE, // UART3 Tx
  174. GPDMA_WIDTH_BYTE, // UART3 Rx
  175. GPDMA_WIDTH_WORD, // MAT0.0
  176. GPDMA_WIDTH_WORD, // MAT0.1
  177. GPDMA_WIDTH_WORD, // MAT1.0
  178. GPDMA_WIDTH_WORD, // MAT1.1
  179. GPDMA_WIDTH_WORD, // MAT2.0
  180. GPDMA_WIDTH_WORD, // MAT2.1
  181. GPDMA_WIDTH_WORD, // MAT3.0
  182. GPDMA_WIDTH_WORD // MAT3.1
  183. };
  184. /**
  185. * @}
  186. */
  187. /* Public Functions ----------------------------------------------------------- */
  188. /** @addtogroup GPDMA_Public_Functions
  189. * @{
  190. */
  191. /********************************************************************//**
  192. * @brief Initialize GPDMA controller
  193. * @param None
  194. * @return None
  195. *********************************************************************/
  196. void GPDMA_Init(void)
  197. {
  198. /* Enable GPDMA clock */
  199. CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCGPDMA, ENABLE);
  200. // Reset all channel configuration register
  201. LPC_GPDMACH0->DMACCConfig = 0;
  202. LPC_GPDMACH1->DMACCConfig = 0;
  203. LPC_GPDMACH2->DMACCConfig = 0;
  204. LPC_GPDMACH3->DMACCConfig = 0;
  205. LPC_GPDMACH4->DMACCConfig = 0;
  206. LPC_GPDMACH5->DMACCConfig = 0;
  207. LPC_GPDMACH6->DMACCConfig = 0;
  208. LPC_GPDMACH7->DMACCConfig = 0;
  209. /* Clear all DMA interrupt and error flag */
  210. LPC_GPDMA->DMACIntTCClear = 0xFF;
  211. LPC_GPDMA->DMACIntErrClr = 0xFF;
  212. }
  213. /********************************************************************//**
  214. * @brief Setup GPDMA channel peripheral according to the specified
  215. * parameters in the GPDMAChannelConfig.
  216. * @param[in] GPDMAChannelConfig Pointer to a GPDMA_CH_CFG_Type
  217. * structure that contains the configuration
  218. * information for the specified GPDMA channel peripheral.
  219. * @return ERROR if selected channel is enabled before
  220. * or SUCCESS if channel is configured successfully
  221. *********************************************************************/
  222. Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig)
  223. {
  224. LPC_GPDMACH_TypeDef *pDMAch;
  225. uint32_t tmp1, tmp2;
  226. if (LPC_GPDMA->DMACEnbldChns & (GPDMA_DMACEnbldChns_Ch(GPDMAChannelConfig->ChannelNum))) {
  227. // This channel is enabled, return ERROR, need to release this channel first
  228. return ERROR;
  229. }
  230. // Get Channel pointer
  231. pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[GPDMAChannelConfig->ChannelNum];
  232. // Reset the Interrupt status
  233. LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(GPDMAChannelConfig->ChannelNum);
  234. LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(GPDMAChannelConfig->ChannelNum);
  235. // Clear DMA configure
  236. pDMAch->DMACCControl = 0x00;
  237. pDMAch->DMACCConfig = 0x00;
  238. /* Assign Linker List Item value */
  239. pDMAch->DMACCLLI = GPDMAChannelConfig->DMALLI;
  240. /* Set value to Channel Control Registers */
  241. switch (GPDMAChannelConfig->TransferType)
  242. {
  243. // Memory to memory
  244. case GPDMA_TRANSFERTYPE_M2M:
  245. // Assign physical source and destination address
  246. pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
  247. pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
  248. pDMAch->DMACCControl
  249. = GPDMA_DMACCxControl_TransferSize(GPDMAChannelConfig->TransferSize) \
  250. | GPDMA_DMACCxControl_SBSize(GPDMA_BSIZE_32) \
  251. | GPDMA_DMACCxControl_DBSize(GPDMA_BSIZE_32) \
  252. | GPDMA_DMACCxControl_SWidth(GPDMAChannelConfig->TransferWidth) \
  253. | GPDMA_DMACCxControl_DWidth(GPDMAChannelConfig->TransferWidth) \
  254. | GPDMA_DMACCxControl_SI \
  255. | GPDMA_DMACCxControl_DI \
  256. | GPDMA_DMACCxControl_I;
  257. break;
  258. // Memory to peripheral
  259. case GPDMA_TRANSFERTYPE_M2P:
  260. // Assign physical source
  261. pDMAch->DMACCSrcAddr = GPDMAChannelConfig->SrcMemAddr;
  262. // Assign peripheral destination address
  263. pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
  264. pDMAch->DMACCControl
  265. = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
  266. | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
  267. | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
  268. | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
  269. | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
  270. | GPDMA_DMACCxControl_SI \
  271. | GPDMA_DMACCxControl_I;
  272. break;
  273. // Peripheral to memory
  274. case GPDMA_TRANSFERTYPE_P2M:
  275. // Assign peripheral source address
  276. pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
  277. // Assign memory destination address
  278. pDMAch->DMACCDestAddr = GPDMAChannelConfig->DstMemAddr;
  279. pDMAch->DMACCControl
  280. = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
  281. | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
  282. | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
  283. | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
  284. | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
  285. | GPDMA_DMACCxControl_DI \
  286. | GPDMA_DMACCxControl_I;
  287. break;
  288. // Peripheral to peripheral
  289. case GPDMA_TRANSFERTYPE_P2P:
  290. // Assign peripheral source address
  291. pDMAch->DMACCSrcAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->SrcConn];
  292. // Assign peripheral destination address
  293. pDMAch->DMACCDestAddr = (uint32_t)GPDMA_LUTPerAddr[GPDMAChannelConfig->DstConn];
  294. pDMAch->DMACCControl
  295. = GPDMA_DMACCxControl_TransferSize((uint32_t)GPDMAChannelConfig->TransferSize) \
  296. | GPDMA_DMACCxControl_SBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->SrcConn]) \
  297. | GPDMA_DMACCxControl_DBSize((uint32_t)GPDMA_LUTPerBurst[GPDMAChannelConfig->DstConn]) \
  298. | GPDMA_DMACCxControl_SWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->SrcConn]) \
  299. | GPDMA_DMACCxControl_DWidth((uint32_t)GPDMA_LUTPerWid[GPDMAChannelConfig->DstConn]) \
  300. | GPDMA_DMACCxControl_I;
  301. break;
  302. // Do not support any more transfer type, return ERROR
  303. default:
  304. return ERROR;
  305. }
  306. /* Re-Configure DMA Request Select for source peripheral */
  307. if (GPDMAChannelConfig->SrcConn > 15)
  308. {
  309. LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->SrcConn - 16));
  310. } else {
  311. LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->SrcConn - 8));
  312. }
  313. /* Re-Configure DMA Request Select for Destination peripheral */
  314. if (GPDMAChannelConfig->DstConn > 15)
  315. {
  316. LPC_SC->DMAREQSEL |= (1<<(GPDMAChannelConfig->DstConn - 16));
  317. } else {
  318. LPC_SC->DMAREQSEL &= ~(1<<(GPDMAChannelConfig->DstConn - 8));
  319. }
  320. /* Enable DMA channels, little endian */
  321. LPC_GPDMA->DMACConfig = GPDMA_DMACConfig_E;
  322. while (!(LPC_GPDMA->DMACConfig & GPDMA_DMACConfig_E));
  323. // Calculate absolute value for Connection number
  324. tmp1 = GPDMAChannelConfig->SrcConn;
  325. tmp1 = ((tmp1 > 15) ? (tmp1 - 8) : tmp1);
  326. tmp2 = GPDMAChannelConfig->DstConn;
  327. tmp2 = ((tmp2 > 15) ? (tmp2 - 8) : tmp2);
  328. // Configure DMA Channel, enable Error Counter and Terminate counter
  329. pDMAch->DMACCConfig = GPDMA_DMACCxConfig_IE | GPDMA_DMACCxConfig_ITC /*| GPDMA_DMACCxConfig_E*/ \
  330. | GPDMA_DMACCxConfig_TransferType((uint32_t)GPDMAChannelConfig->TransferType) \
  331. | GPDMA_DMACCxConfig_SrcPeripheral(tmp1) \
  332. | GPDMA_DMACCxConfig_DestPeripheral(tmp2);
  333. return SUCCESS;
  334. }
  335. /*********************************************************************//**
  336. * @brief Enable/Disable DMA channel
  337. * @param[in] channelNum GPDMA channel, should be in range from 0 to 7
  338. * @param[in] NewState New State of this command, should be:
  339. * - ENABLE.
  340. * - DISABLE.
  341. * @return None
  342. **********************************************************************/
  343. void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState)
  344. {
  345. LPC_GPDMACH_TypeDef *pDMAch;
  346. // Get Channel pointer
  347. pDMAch = (LPC_GPDMACH_TypeDef *) pGPDMACh[channelNum];
  348. if (NewState == ENABLE) {
  349. pDMAch->DMACCConfig |= GPDMA_DMACCxConfig_E;
  350. } else {
  351. pDMAch->DMACCConfig &= ~GPDMA_DMACCxConfig_E;
  352. }
  353. }
  354. /*********************************************************************//**
  355. * @brief Check if corresponding channel does have an active interrupt
  356. * request or not
  357. * @param[in] type type of status, should be:
  358. * - GPDMA_STAT_INT: GPDMA Interrupt Status
  359. * - GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status
  360. * - GPDMA_STAT_INTERR: GPDMA Interrupt Error Status
  361. * - GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status
  362. * - GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status
  363. * - GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
  364. * @param[in] channel GPDMA channel, should be in range from 0 to 7
  365. * @return IntStatus status of DMA channel interrupt after masking
  366. * Should be:
  367. * - SET: the corresponding channel has no active interrupt request
  368. * - RESET: the corresponding channel does have an active interrupt request
  369. **********************************************************************/
  370. IntStatus GPDMA_IntGetStatus(GPDMA_Status_Type type, uint8_t channel)
  371. {
  372. CHECK_PARAM(PARAM_GPDMA_STAT(type));
  373. CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
  374. switch (type)
  375. {
  376. case GPDMA_STAT_INT: //check status of DMA channel interrupts
  377. if (LPC_GPDMA->DMACIntStat & (GPDMA_DMACIntStat_Ch(channel)))
  378. return SET;
  379. return RESET;
  380. case GPDMA_STAT_INTTC: // check terminal count interrupt request status for DMA
  381. if (LPC_GPDMA->DMACIntTCStat & GPDMA_DMACIntTCStat_Ch(channel))
  382. return SET;
  383. return RESET;
  384. case GPDMA_STAT_INTERR: //check interrupt status for DMA channels
  385. if (LPC_GPDMA->DMACIntErrStat & GPDMA_DMACIntTCClear_Ch(channel))
  386. return SET;
  387. return RESET;
  388. case GPDMA_STAT_RAWINTTC: //check status of the terminal count interrupt for DMA channels
  389. if (LPC_GPDMA->DMACRawIntErrStat & GPDMA_DMACRawIntTCStat_Ch(channel))
  390. return SET;
  391. return RESET;
  392. case GPDMA_STAT_RAWINTERR: //check status of the error interrupt for DMA channels
  393. if (LPC_GPDMA->DMACRawIntTCStat & GPDMA_DMACRawIntErrStat_Ch(channel))
  394. return SET;
  395. return RESET;
  396. default: //check enable status for DMA channels
  397. if (LPC_GPDMA->DMACEnbldChns & GPDMA_DMACEnbldChns_Ch(channel))
  398. return SET;
  399. return RESET;
  400. }
  401. }
  402. /*********************************************************************//**
  403. * @brief Clear one or more interrupt requests on DMA channels
  404. * @param[in] type type of interrupt request, should be:
  405. * - GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear
  406. * - GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
  407. * @param[in] channel GPDMA channel, should be in range from 0 to 7
  408. * @return None
  409. **********************************************************************/
  410. void GPDMA_ClearIntPending(GPDMA_StateClear_Type type, uint8_t channel)
  411. {
  412. CHECK_PARAM(PARAM_GPDMA_STATCLR(type));
  413. CHECK_PARAM(PARAM_GPDMA_CHANNEL(channel));
  414. if (type == GPDMA_STATCLR_INTTC) // clears the terminal count interrupt request on DMA channel
  415. LPC_GPDMA->DMACIntTCClear = GPDMA_DMACIntTCClear_Ch(channel);
  416. else // clear the error interrupt request
  417. LPC_GPDMA->DMACIntErrClr = GPDMA_DMACIntErrClr_Ch(channel);
  418. }
  419. /**
  420. * @}
  421. */
  422. #endif /* _GPDMA */
  423. /**
  424. * @}
  425. */
  426. /* --------------------------------- End Of File ------------------------------ */