My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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variant.cpp 8.5KB

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  1. /*
  2. Copyright (c) 2011 Arduino. All right reserved.
  3. This library is free software; you can redistribute it and/or
  4. modify it under the terms of the GNU Lesser General Public
  5. License as published by the Free Software Foundation; either
  6. version 2.1 of the License, or (at your option) any later version.
  7. This library is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  10. See the GNU Lesser General Public License for more details.
  11. You should have received a copy of the GNU Lesser General Public
  12. License along with this library; if not, write to the Free Software
  13. Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  14. */
  15. #include "pins_arduino.h"
  16. #ifdef __cplusplus
  17. extern "C" {
  18. #endif
  19. // Digital PinName array
  20. const PinName digitalPin[] = {
  21. PA_0, // Digital pin 0
  22. PA_1, // Digital pin 1
  23. PA_2, // Digital pin 2
  24. PA_3, // Digital pin 3
  25. PA_4, // Digital pin 4
  26. PA_5, // Digital pin 5
  27. PA_6, // Digital pin 6
  28. PA_7, // Digital pin 7
  29. PA_8, // Digital pin 8
  30. PA_9, // Digital pin 9
  31. PA_10, // Digital pin 10
  32. PA_11, // Digital pin 11
  33. PA_12, // Digital pin 12
  34. PA_13, // Digital pin 13
  35. PA_14, // Digital pin 14
  36. PA_15, // Digital pin 15
  37. PB_0, // Digital pin 16
  38. PB_1, // Digital pin 17
  39. PB_2, // Digital pin 18
  40. PB_3, // Digital pin 19
  41. PB_4, // Digital pin 20
  42. PB_5, // Digital pin 21
  43. PB_6, // Digital pin 22
  44. PB_7, // Digital pin 23
  45. PB_8, // Digital pin 24
  46. PB_9, // Digital pin 25
  47. PB_10, // Digital pin 26
  48. PB_12, // Digital pin 27
  49. PB_13, // Digital pin 28
  50. PB_14, // Digital pin 29
  51. PB_15, // Digital pin 30
  52. PC_0, // Digital pin 31
  53. PC_1, // Digital pin 32
  54. PC_2, // Digital pin 33
  55. PC_3, // Digital pin 34
  56. PC_4, // Digital pin 35
  57. PC_5, // Digital pin 36
  58. PC_6, // Digital pin 37
  59. PC_7, // Digital pin 38
  60. PC_8, // Digital pin 39
  61. PC_9, // Digital pin 40
  62. PC_10, // Digital pin 41
  63. PC_11, // Digital pin 42
  64. PC_12, // Digital pin 43
  65. PC_13, // Digital pin 44
  66. PC_14, // Digital pin 45
  67. PC_15, // Digital pin 46
  68. PD_2, // Digital pin 47
  69. PH_0, // Digital pin 48, used by the external oscillator
  70. PH_1 // Digital pin 49, used by the external oscillator
  71. };
  72. // Analog (Ax) pin number array
  73. const uint32_t analogInputPin[] = {
  74. 0, // A0, PA0
  75. 1, // A1, PA1
  76. 2, // A2, PA2
  77. 3, // A3, PA3
  78. 4, // A4, PA4
  79. 5, // A5, PA5
  80. 6, // A6, PA6
  81. 7, // A7, PA7
  82. 16, // A8, PB0
  83. 17, // A9, PB1
  84. 31, // A10, PC0
  85. 32, // A11, PC1
  86. 33, // A12, PC2
  87. 34, // A13, PC3
  88. 35, // A14, PC4
  89. 36 // A15, PC5
  90. };
  91. #ifdef __cplusplus
  92. }
  93. #endif
  94. // ----------------------------------------------------------------------------
  95. #ifdef __cplusplus
  96. extern "C" {
  97. #endif
  98. /*
  99. * @brief Configures the System clock source, PLL Multiplier and Divider factors,
  100. * AHB/APBx prescalers and Flash settings
  101. * @note This function should be called only once the RCC clock configuration
  102. * is reset to the default reset state (done in SystemInit() function).
  103. * @param None
  104. * @retval None
  105. */
  106. /******************************************************************************/
  107. /* PLL (clocked by HSE) used as System clock source */
  108. /******************************************************************************/
  109. static uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
  110. {
  111. RCC_OscInitTypeDef RCC_OscInitStruct;
  112. RCC_ClkInitTypeDef RCC_ClkInitStruct;
  113. /* The voltage scaling allows optimizing the power consumption when the device is
  114. clocked below the maximum system frequency, to update the voltage scaling value
  115. regarding system frequency refer to product datasheet. */
  116. __HAL_RCC_PWR_CLK_ENABLE();
  117. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
  118. // Enable HSE oscillator and activate PLL with HSE as source
  119. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
  120. if (bypass == 0) {
  121. RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
  122. } else {
  123. RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
  124. }
  125. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  126. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
  127. RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000L; // Expects an 8 MHz external clock by default. Redefine HSE_VALUE if not
  128. RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
  129. RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
  130. RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
  131. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
  132. return 0; // FAIL
  133. }
  134. // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
  135. RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
  136. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
  137. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
  138. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
  139. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
  140. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
  141. return 0; // FAIL
  142. }
  143. /* Output clock on MCO1 pin(PA8) for debugging purpose */
  144. /*
  145. if (bypass == 0)
  146. HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
  147. else
  148. HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
  149. */
  150. return 1; // OK
  151. }
  152. /******************************************************************************/
  153. /* PLL (clocked by HSI) used as System clock source */
  154. /******************************************************************************/
  155. uint8_t SetSysClock_PLL_HSI(void)
  156. {
  157. RCC_OscInitTypeDef RCC_OscInitStruct;
  158. RCC_ClkInitTypeDef RCC_ClkInitStruct;
  159. /* The voltage scaling allows optimizing the power consumption when the device is
  160. clocked below the maximum system frequency, to update the voltage scaling value
  161. regarding system frequency refer to product datasheet. */
  162. __HAL_RCC_PWR_CLK_ENABLE();
  163. __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
  164. // Enable HSI oscillator and activate PLL with HSI as source
  165. RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
  166. RCC_OscInitStruct.HSIState = RCC_HSI_ON;
  167. RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
  168. RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
  169. RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
  170. RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
  171. RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
  172. RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
  173. RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
  174. RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
  175. if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
  176. return 0; // FAIL
  177. }
  178. /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
  179. RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
  180. RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
  181. RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
  182. RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
  183. RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
  184. if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
  185. return 0; // FAIL
  186. }
  187. /* Output clock on MCO1 pin(PA8) for debugging purpose */
  188. //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
  189. return 1; // OK
  190. }
  191. WEAK void SystemClock_Config(void)
  192. {
  193. /* 1- If fail try to start with HSE and external xtal */
  194. if (SetSysClock_PLL_HSE(0) == 0) {
  195. /* 2- Try to start with HSE and external clock */
  196. if (SetSysClock_PLL_HSE(1) == 0) {
  197. /* 3- If fail start with HSI clock */
  198. if (SetSysClock_PLL_HSI() == 0) {
  199. Error_Handler();
  200. }
  201. }
  202. }
  203. /* Output clock on MCO2 pin(PC9) for debugging purpose */
  204. //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
  205. }
  206. #ifdef __cplusplus
  207. }
  208. #endif