My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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tft_fsmc.h 6.0KB

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  1. /**
  2. * Marlin 3D Printer Firmware
  3. * Copyright (c) 2020 MarlinFirmware [https://github.com/MarlinFirmware/Marlin]
  4. *
  5. * Based on Sprinter and grbl.
  6. * Copyright (c) 2011 Camiel Gubbels / Erik van der Zalm
  7. *
  8. * This program is free software: you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation, either version 3 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program. If not, see <https://www.gnu.org/licenses/>.
  20. *
  21. */
  22. #pragma once
  23. #ifdef STM32F1xx
  24. #include "stm32f1xx_hal.h"
  25. #elif defined(STM32F4xx)
  26. #include "stm32f4xx_hal.h"
  27. #else
  28. #error FSMC TFT is currently only supported on STM32F1 and STM32F4 hardware.
  29. #endif
  30. #ifndef LCD_READ_ID
  31. #define LCD_READ_ID 0x04 // Read display identification information (0xD3 on ILI9341)
  32. #endif
  33. #ifndef LCD_READ_ID4
  34. #define LCD_READ_ID4 0xD3 // Read display identification information (0xD3 on ILI9341)
  35. #endif
  36. #define DATASIZE_8BIT SPI_DATASIZE_8BIT
  37. #define DATASIZE_16BIT SPI_DATASIZE_16BIT
  38. #define TFT_IO_DRIVER TFT_FSMC
  39. #ifdef STM32F1xx
  40. #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CCR & DMA_CCR_EN)
  41. #elif defined(STM32F4xx)
  42. #define __IS_DMA_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR & DMA_SxCR_EN)
  43. #endif
  44. typedef struct {
  45. __IO uint16_t REG;
  46. __IO uint16_t RAM;
  47. } LCD_CONTROLLER_TypeDef;
  48. class TFT_FSMC {
  49. private:
  50. static SRAM_HandleTypeDef SRAMx;
  51. static DMA_HandleTypeDef DMAtx;
  52. static LCD_CONTROLLER_TypeDef *LCD;
  53. static uint32_t ReadID(uint16_t Reg);
  54. static void Transmit(uint16_t Data) { LCD->RAM = Data; __DSB(); }
  55. static void TransmitDMA(uint32_t MemoryIncrease, uint16_t *Data, uint16_t Count);
  56. public:
  57. static void Init();
  58. static uint32_t GetID();
  59. static bool isBusy();
  60. static void Abort() { __HAL_DMA_DISABLE(&DMAtx); }
  61. static void DataTransferBegin(uint16_t DataWidth = DATASIZE_16BIT) {}
  62. static void DataTransferEnd() {};
  63. static void WriteData(uint16_t Data) { Transmit(Data); }
  64. static void WriteReg(uint16_t Reg) { LCD->REG = Reg; __DSB(); }
  65. static void WriteSequence(uint16_t *Data, uint16_t Count) { TransmitDMA(DMA_PINC_ENABLE, Data, Count); }
  66. static void WriteMultiple(uint16_t Color, uint16_t Count) { static uint16_t Data; Data = Color; TransmitDMA(DMA_PINC_DISABLE, &Data, Count); }
  67. };
  68. #ifdef STM32F1xx
  69. #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)
  70. #elif defined(STM32F4xx)
  71. #define FSMC_PIN_DATA STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC)
  72. #define FSMC_BANK1_1 0x60000000U
  73. #define FSMC_BANK1_2 0x64000000U
  74. #define FSMC_BANK1_3 0x68000000U
  75. #define FSMC_BANK1_4 0x6C000000U
  76. #else
  77. #error No configuration for this MCU
  78. #endif
  79. const PinMap PinMap_FSMC[] = {
  80. {PD_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00
  81. {PD_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01
  82. {PD_0, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02
  83. {PD_1, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03
  84. {PE_7, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04
  85. {PE_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05
  86. {PE_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06
  87. {PE_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07
  88. {PE_11, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08
  89. {PE_12, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09
  90. {PE_13, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10
  91. {PE_14, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11
  92. {PE_15, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12
  93. {PD_8, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13
  94. {PD_9, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14
  95. {PD_10, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15
  96. {PD_4, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE
  97. {PD_5, FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE
  98. {NC, NP, 0}
  99. };
  100. const PinMap PinMap_FSMC_CS[] = {
  101. {PD_7, (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1
  102. #ifdef PF0
  103. {PG_9, (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2
  104. {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3
  105. {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4
  106. #endif
  107. {NC, NP, 0}
  108. };
  109. #define FSMC_RS(A) (void *)((2 << A) - 2)
  110. const PinMap PinMap_FSMC_RS[] = {
  111. #ifdef PF0
  112. {PF_0, FSMC_RS( 0), FSMC_PIN_DATA}, // FSMC_A0
  113. {PF_1, FSMC_RS( 1), FSMC_PIN_DATA}, // FSMC_A1
  114. {PF_2, FSMC_RS( 2), FSMC_PIN_DATA}, // FSMC_A2
  115. {PF_3, FSMC_RS( 3), FSMC_PIN_DATA}, // FSMC_A3
  116. {PF_4, FSMC_RS( 4), FSMC_PIN_DATA}, // FSMC_A4
  117. {PF_5, FSMC_RS( 5), FSMC_PIN_DATA}, // FSMC_A5
  118. {PF_12, FSMC_RS( 6), FSMC_PIN_DATA}, // FSMC_A6
  119. {PF_13, FSMC_RS( 7), FSMC_PIN_DATA}, // FSMC_A7
  120. {PF_14, FSMC_RS( 8), FSMC_PIN_DATA}, // FSMC_A8
  121. {PF_15, FSMC_RS( 9), FSMC_PIN_DATA}, // FSMC_A9
  122. {PG_0, FSMC_RS(10), FSMC_PIN_DATA}, // FSMC_A10
  123. {PG_1, FSMC_RS(11), FSMC_PIN_DATA}, // FSMC_A11
  124. {PG_2, FSMC_RS(12), FSMC_PIN_DATA}, // FSMC_A12
  125. {PG_3, FSMC_RS(13), FSMC_PIN_DATA}, // FSMC_A13
  126. {PG_4, FSMC_RS(14), FSMC_PIN_DATA}, // FSMC_A14
  127. {PG_5, FSMC_RS(15), FSMC_PIN_DATA}, // FSMC_A15
  128. #endif
  129. {PD_11, FSMC_RS(16), FSMC_PIN_DATA}, // FSMC_A16
  130. {PD_12, FSMC_RS(17), FSMC_PIN_DATA}, // FSMC_A17
  131. {PD_13, FSMC_RS(18), FSMC_PIN_DATA}, // FSMC_A18
  132. {PE_3, FSMC_RS(19), FSMC_PIN_DATA}, // FSMC_A19
  133. {PE_4, FSMC_RS(20), FSMC_PIN_DATA}, // FSMC_A20
  134. {PE_5, FSMC_RS(21), FSMC_PIN_DATA}, // FSMC_A21
  135. {PE_6, FSMC_RS(22), FSMC_PIN_DATA}, // FSMC_A22
  136. {PE_2, FSMC_RS(23), FSMC_PIN_DATA}, // FSMC_A23
  137. #ifdef PF0
  138. {PG_13, FSMC_RS(24), FSMC_PIN_DATA}, // FSMC_A24
  139. {PG_14, FSMC_RS(25), FSMC_PIN_DATA}, // FSMC_A25
  140. #endif
  141. {NC, NP, 0}
  142. };