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main.c 15KB

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  1. /**
  2. * Copyright (c) 2022 Brian Starkey <stark3y@gmail.com>
  3. *
  4. * Based on the Pico W tcp_server example:
  5. * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
  6. *
  7. * SPDX-License-Identifier: BSD-3-Clause
  8. */
  9. #include <string.h>
  10. #include <stdlib.h>
  11. #include "RP2040.h"
  12. #include "pico/critical_section.h"
  13. #include "pico/time.h"
  14. #include "pico/util/queue.h"
  15. #include "hardware/dma.h"
  16. #include "hardware/flash.h"
  17. #include "hardware/structs/dma.h"
  18. #include "hardware/structs/watchdog.h"
  19. #include "hardware/gpio.h"
  20. #include "hardware/resets.h"
  21. #include "hardware/uart.h"
  22. #include "hardware/watchdog.h"
  23. #include "pico/stdlib.h"
  24. #include "pico/cyw43_arch.h"
  25. #include "tcp_comm.h"
  26. #include "picowota/reboot.h"
  27. #ifdef DEBUG
  28. #include <stdio.h>
  29. #include "pico/stdio_usb.h"
  30. #define DBG_PRINTF_INIT() stdio_usb_init()
  31. #define DBG_PRINTF(...) printf(__VA_ARGS__)
  32. #else
  33. #define DBG_PRINTF_INIT() { }
  34. #define DBG_PRINTF(...) { }
  35. #endif
  36. #if PICOWOTA_WIFI_AP == 1
  37. #include "dhcpserver.h"
  38. static dhcp_server_t dhcp_server;
  39. #endif
  40. #define QUOTE(name) #name
  41. #define STR(macro) QUOTE(macro)
  42. #ifndef PICOWOTA_WIFI_SSID
  43. #warning "PICOWOTA_WIFI_SSID not defined"
  44. #else
  45. const char *wifi_ssid = STR(PICOWOTA_WIFI_SSID);
  46. #endif
  47. #ifndef PICOWOTA_WIFI_PASS
  48. #warning "PICOWOTA_WIFI_PASS not defined"
  49. #else
  50. const char *wifi_pass = STR(PICOWOTA_WIFI_PASS);
  51. #endif
  52. critical_section_t critical_section;
  53. #define EVENT_QUEUE_LENGTH 8
  54. queue_t event_queue;
  55. enum event_type {
  56. EVENT_TYPE_REBOOT = 1,
  57. EVENT_TYPE_GO,
  58. EVENT_TYPE_SERVER_DONE,
  59. };
  60. struct event {
  61. enum event_type type;
  62. union {
  63. struct {
  64. bool to_bootloader;
  65. } reboot;
  66. struct {
  67. uint32_t vtor;
  68. } go;
  69. };
  70. };
  71. #define BOOTLOADER_ENTRY_PIN 15
  72. #define TCP_PORT 4242
  73. #define IMAGE_HEADER_OFFSET (360 * 1024)
  74. #define WRITE_ADDR_MIN (XIP_BASE + IMAGE_HEADER_OFFSET + FLASH_SECTOR_SIZE)
  75. #define ERASE_ADDR_MIN (XIP_BASE + IMAGE_HEADER_OFFSET)
  76. #define FLASH_ADDR_MAX (XIP_BASE + PICO_FLASH_SIZE_BYTES)
  77. #define CMD_SYNC (('S' << 0) | ('Y' << 8) | ('N' << 16) | ('C' << 24))
  78. #define RSP_SYNC (('W' << 0) | ('O' << 8) | ('T' << 16) | ('A' << 24))
  79. #define CMD_INFO (('I' << 0) | ('N' << 8) | ('F' << 16) | ('O' << 24))
  80. #define CMD_READ (('R' << 0) | ('E' << 8) | ('A' << 16) | ('D' << 24))
  81. #define CMD_CSUM (('C' << 0) | ('S' << 8) | ('U' << 16) | ('M' << 24))
  82. #define CMD_CRC (('C' << 0) | ('R' << 8) | ('C' << 16) | ('C' << 24))
  83. #define CMD_ERASE (('E' << 0) | ('R' << 8) | ('A' << 16) | ('S' << 24))
  84. #define CMD_WRITE (('W' << 0) | ('R' << 8) | ('I' << 16) | ('T' << 24))
  85. #define CMD_SEAL (('S' << 0) | ('E' << 8) | ('A' << 16) | ('L' << 24))
  86. #define CMD_GO (('G' << 0) | ('O' << 8) | ('G' << 16) | ('O' << 24))
  87. #define CMD_REBOOT (('B' << 0) | ('O' << 8) | ('O' << 16) | ('T' << 24))
  88. static uint32_t handle_sync(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  89. {
  90. return RSP_SYNC;
  91. }
  92. const struct comm_command sync_cmd = {
  93. .opcode = CMD_SYNC,
  94. .nargs = 0,
  95. .resp_nargs = 0,
  96. .size = NULL,
  97. .handle = &handle_sync,
  98. };
  99. static uint32_t size_read(uint32_t *args_in, uint32_t *data_len_out, uint32_t *resp_data_len_out)
  100. {
  101. uint32_t size = args_in[1];
  102. if (size > TCP_COMM_MAX_DATA_LEN) {
  103. return TCP_COMM_RSP_ERR;
  104. }
  105. // TODO: Validate address
  106. *data_len_out = 0;
  107. *resp_data_len_out = size;
  108. return TCP_COMM_RSP_OK;
  109. }
  110. static uint32_t handle_read(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  111. {
  112. uint32_t addr = args_in[0];
  113. uint32_t size = args_in[1];
  114. memcpy(resp_data_out, (void *)addr, size);
  115. return TCP_COMM_RSP_OK;
  116. }
  117. const struct comm_command read_cmd = {
  118. // READ addr len
  119. // OKOK [data]
  120. .opcode = CMD_READ,
  121. .nargs = 2,
  122. .resp_nargs = 0,
  123. .size = &size_read,
  124. .handle = &handle_read,
  125. };
  126. static uint32_t size_csum(uint32_t *args_in, uint32_t *data_len_out, uint32_t *resp_data_len_out)
  127. {
  128. uint32_t addr = args_in[0];
  129. uint32_t size = args_in[1];
  130. if ((addr & 0x3) || (size & 0x3)) {
  131. // Must be aligned
  132. return TCP_COMM_RSP_ERR;
  133. }
  134. // TODO: Validate address
  135. *data_len_out = 0;
  136. *resp_data_len_out = 0;
  137. return TCP_COMM_RSP_OK;
  138. }
  139. static uint32_t handle_csum(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  140. {
  141. uint32_t dummy_dest;
  142. uint32_t addr = args_in[0];
  143. uint32_t size = args_in[1];
  144. int channel = dma_claim_unused_channel(true);
  145. dma_channel_config c = dma_channel_get_default_config(channel);
  146. channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
  147. channel_config_set_read_increment(&c, true);
  148. channel_config_set_write_increment(&c, false);
  149. channel_config_set_sniff_enable(&c, true);
  150. dma_hw->sniff_data = 0;
  151. dma_sniffer_enable(channel, 0xf, true);
  152. dma_channel_configure(channel, &c, &dummy_dest, (void *)addr, size / 4, true);
  153. dma_channel_wait_for_finish_blocking(channel);
  154. dma_sniffer_disable();
  155. dma_channel_unclaim(channel);
  156. *resp_args_out = dma_hw->sniff_data;
  157. return TCP_COMM_RSP_OK;
  158. }
  159. struct comm_command csum_cmd = {
  160. // CSUM addr len
  161. // OKOK csum
  162. .opcode = CMD_CSUM,
  163. .nargs = 2,
  164. .resp_nargs = 1,
  165. .size = &size_csum,
  166. .handle = &handle_csum,
  167. };
  168. static uint32_t size_crc(uint32_t *args_in, uint32_t *data_len_out, uint32_t *resp_data_len_out)
  169. {
  170. uint32_t addr = args_in[0];
  171. uint32_t size = args_in[1];
  172. if ((addr & 0x3) || (size & 0x3)) {
  173. // Must be aligned
  174. return TCP_COMM_RSP_ERR;
  175. }
  176. // TODO: Validate address
  177. *data_len_out = 0;
  178. *resp_data_len_out = 0;
  179. return TCP_COMM_RSP_OK;
  180. }
  181. // ptr must be 4-byte aligned and len must be a multiple of 4
  182. static uint32_t calc_crc32(void *ptr, uint32_t len)
  183. {
  184. uint32_t dummy_dest, crc;
  185. int channel = dma_claim_unused_channel(true);
  186. dma_channel_config c = dma_channel_get_default_config(channel);
  187. channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
  188. channel_config_set_read_increment(&c, true);
  189. channel_config_set_write_increment(&c, false);
  190. channel_config_set_sniff_enable(&c, true);
  191. // Seed the CRC calculation
  192. dma_hw->sniff_data = 0xffffffff;
  193. // Mode 1, then bit-reverse the result gives the same result as
  194. // golang's IEEE802.3 implementation
  195. dma_sniffer_enable(channel, 0x1, true);
  196. dma_hw->sniff_ctrl |= DMA_SNIFF_CTRL_OUT_REV_BITS;
  197. dma_channel_configure(channel, &c, &dummy_dest, ptr, len / 4, true);
  198. dma_channel_wait_for_finish_blocking(channel);
  199. // Read the result before resetting
  200. crc = dma_hw->sniff_data ^ 0xffffffff;
  201. dma_sniffer_disable();
  202. dma_channel_unclaim(channel);
  203. return crc;
  204. }
  205. static uint32_t handle_crc(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  206. {
  207. uint32_t addr = args_in[0];
  208. uint32_t size = args_in[1];
  209. resp_args_out[0] = calc_crc32((void *)addr, size);
  210. return TCP_COMM_RSP_OK;
  211. }
  212. struct comm_command crc_cmd = {
  213. // CRCC addr len
  214. // OKOK crc
  215. .opcode = CMD_CRC,
  216. .nargs = 2,
  217. .resp_nargs = 1,
  218. .size = &size_crc,
  219. .handle = &handle_crc,
  220. };
  221. static uint32_t handle_erase(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  222. {
  223. uint32_t addr = args_in[0];
  224. uint32_t size = args_in[1];
  225. if ((addr < ERASE_ADDR_MIN) || (addr + size >= FLASH_ADDR_MAX)) {
  226. // Outside flash
  227. return TCP_COMM_RSP_ERR;
  228. }
  229. if ((addr & (FLASH_SECTOR_SIZE - 1)) || (size & (FLASH_SECTOR_SIZE - 1))) {
  230. // Must be aligned
  231. return TCP_COMM_RSP_ERR;
  232. }
  233. critical_section_enter_blocking(&critical_section);
  234. flash_range_erase(addr - XIP_BASE, size);
  235. critical_section_exit(&critical_section);
  236. return TCP_COMM_RSP_OK;
  237. }
  238. struct comm_command erase_cmd = {
  239. // ERAS addr len
  240. // OKOK
  241. .opcode = CMD_ERASE,
  242. .nargs = 2,
  243. .resp_nargs = 0,
  244. .size = NULL,
  245. .handle = &handle_erase,
  246. };
  247. static uint32_t size_write(uint32_t *args_in, uint32_t *data_len_out, uint32_t *resp_data_len_out)
  248. {
  249. uint32_t addr = args_in[0];
  250. uint32_t size = args_in[1];
  251. if ((addr < WRITE_ADDR_MIN) || (addr + size >= FLASH_ADDR_MAX)) {
  252. // Outside flash
  253. return TCP_COMM_RSP_ERR;
  254. }
  255. if ((addr & (FLASH_PAGE_SIZE - 1)) || (size & (FLASH_PAGE_SIZE -1))) {
  256. // Must be aligned
  257. return TCP_COMM_RSP_ERR;
  258. }
  259. if (size > TCP_COMM_MAX_DATA_LEN) {
  260. return TCP_COMM_RSP_ERR;
  261. }
  262. // TODO: Validate address
  263. *data_len_out = size;
  264. *resp_data_len_out = 0;
  265. return TCP_COMM_RSP_OK;
  266. }
  267. static uint32_t handle_write(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  268. {
  269. uint32_t addr = args_in[0];
  270. uint32_t size = args_in[1];
  271. critical_section_enter_blocking(&critical_section);
  272. flash_range_program(addr - XIP_BASE, data_in, size);
  273. critical_section_exit(&critical_section);
  274. resp_args_out[0] = calc_crc32((void *)addr, size);
  275. return TCP_COMM_RSP_OK;
  276. }
  277. struct comm_command write_cmd = {
  278. // WRIT addr len [data]
  279. // OKOK crc
  280. .opcode = CMD_WRITE,
  281. .nargs = 2,
  282. .resp_nargs = 1,
  283. .size = &size_write,
  284. .handle = &handle_write,
  285. };
  286. struct image_header {
  287. uint32_t vtor;
  288. uint32_t size;
  289. uint32_t crc;
  290. uint8_t pad[FLASH_PAGE_SIZE - (3 * 4)];
  291. };
  292. static_assert(sizeof(struct image_header) == FLASH_PAGE_SIZE, "image_header must be FLASH_PAGE_SIZE bytes");
  293. static bool image_header_ok(struct image_header *hdr)
  294. {
  295. uint32_t *vtor = (uint32_t *)hdr->vtor;
  296. uint32_t calc = calc_crc32((void *)hdr->vtor, hdr->size);
  297. // CRC has to match
  298. if (calc != hdr->crc) {
  299. return false;
  300. }
  301. // Stack pointer needs to be in RAM
  302. if (vtor[0] < SRAM_BASE) {
  303. return false;
  304. }
  305. // Reset vector should be in the image, and thumb (bit 0 set)
  306. if ((vtor[1] < hdr->vtor) || (vtor[1] > hdr->vtor + hdr->size) || !(vtor[1] & 1)) {
  307. return false;
  308. }
  309. // Looks OK.
  310. return true;
  311. }
  312. static uint32_t handle_seal(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  313. {
  314. struct image_header hdr = {
  315. .vtor = args_in[0],
  316. .size = args_in[1],
  317. .crc = args_in[2],
  318. };
  319. if ((hdr.vtor & 0xff) || (hdr.size & 0x3)) {
  320. // Must be aligned
  321. return TCP_COMM_RSP_ERR;
  322. }
  323. if (!image_header_ok(&hdr)) {
  324. return TCP_COMM_RSP_ERR;
  325. }
  326. critical_section_enter_blocking(&critical_section);
  327. flash_range_erase(IMAGE_HEADER_OFFSET, FLASH_SECTOR_SIZE);
  328. flash_range_program(IMAGE_HEADER_OFFSET, (const uint8_t *)&hdr, sizeof(hdr));
  329. critical_section_exit(&critical_section);
  330. struct image_header *check = (struct image_header *)(XIP_BASE + IMAGE_HEADER_OFFSET);
  331. if (memcmp(&hdr, check, sizeof(hdr))) {
  332. return TCP_COMM_RSP_ERR;
  333. }
  334. return TCP_COMM_RSP_OK;
  335. }
  336. struct comm_command seal_cmd = {
  337. // SEAL vtor len crc
  338. // OKOK
  339. .opcode = CMD_SEAL,
  340. .nargs = 3,
  341. .resp_nargs = 0,
  342. .size = NULL,
  343. .handle = &handle_seal,
  344. };
  345. static void disable_interrupts(void)
  346. {
  347. SysTick->CTRL &= ~1;
  348. NVIC->ICER[0] = 0xFFFFFFFF;
  349. NVIC->ICPR[0] = 0xFFFFFFFF;
  350. }
  351. static void reset_peripherals(void)
  352. {
  353. reset_block(~(
  354. RESETS_RESET_IO_QSPI_BITS |
  355. RESETS_RESET_PADS_QSPI_BITS |
  356. RESETS_RESET_SYSCFG_BITS |
  357. RESETS_RESET_PLL_SYS_BITS
  358. ));
  359. }
  360. static void jump_to_vtor(uint32_t vtor)
  361. {
  362. // Derived from the Leaf Labs Cortex-M3 bootloader.
  363. // Copyright (c) 2010 LeafLabs LLC.
  364. // Modified 2021 Brian Starkey <stark3y@gmail.com>
  365. // Originally under The MIT License
  366. uint32_t reset_vector = *(volatile uint32_t *)(vtor + 0x04);
  367. SCB->VTOR = (volatile uint32_t)(vtor);
  368. asm volatile("msr msp, %0"::"g"
  369. (*(volatile uint32_t *)vtor));
  370. asm volatile("bx %0"::"r" (reset_vector));
  371. }
  372. static uint32_t handle_go(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  373. {
  374. struct event ev = {
  375. .type = EVENT_TYPE_GO,
  376. .go = {
  377. .vtor = args_in[0],
  378. },
  379. };
  380. if (!queue_try_add(&event_queue, &ev)) {
  381. return TCP_COMM_RSP_ERR;
  382. }
  383. return TCP_COMM_RSP_OK;
  384. }
  385. struct comm_command go_cmd = {
  386. // GOGO vtor
  387. // NO RESPONSE
  388. .opcode = CMD_GO,
  389. .nargs = 1,
  390. .resp_nargs = 0,
  391. .size = NULL,
  392. .handle = &handle_go,
  393. };
  394. static uint32_t handle_info(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  395. {
  396. resp_args_out[0] = WRITE_ADDR_MIN;
  397. resp_args_out[1] = (XIP_BASE + PICO_FLASH_SIZE_BYTES) - WRITE_ADDR_MIN;
  398. resp_args_out[2] = FLASH_SECTOR_SIZE;
  399. resp_args_out[3] = FLASH_PAGE_SIZE;
  400. resp_args_out[4] = TCP_COMM_MAX_DATA_LEN;
  401. return TCP_COMM_RSP_OK;
  402. }
  403. const struct comm_command info_cmd = {
  404. // INFO
  405. // OKOK flash_start flash_size erase_size write_size max_data_len
  406. .opcode = CMD_INFO,
  407. .nargs = 0,
  408. .resp_nargs = 5,
  409. .size = NULL,
  410. .handle = &handle_info,
  411. };
  412. static uint32_t size_reboot(uint32_t *args_in, uint32_t *data_len_out, uint32_t *resp_data_len_out)
  413. {
  414. *data_len_out = 0;
  415. *resp_data_len_out = 0;
  416. return TCP_COMM_RSP_OK;
  417. }
  418. static uint32_t handle_reboot(uint32_t *args_in, uint8_t *data_in, uint32_t *resp_args_out, uint8_t *resp_data_out)
  419. {
  420. struct event ev = {
  421. .type = EVENT_TYPE_REBOOT,
  422. .reboot = {
  423. .to_bootloader = !!args_in[0],
  424. },
  425. };
  426. if (!queue_try_add(&event_queue, &ev)) {
  427. return TCP_COMM_RSP_ERR;
  428. }
  429. return TCP_COMM_RSP_OK;
  430. }
  431. struct comm_command reboot_cmd = {
  432. // BOOT to_bootloader
  433. // NO RESPONSE
  434. .opcode = CMD_REBOOT,
  435. .nargs = 1,
  436. .resp_nargs = 0,
  437. .size = &size_reboot,
  438. .handle = &handle_reboot,
  439. };
  440. static bool should_stay_in_bootloader()
  441. {
  442. bool wd_says_so = (watchdog_hw->scratch[5] == PICOWOTA_BOOTLOADER_ENTRY_MAGIC) &&
  443. (watchdog_hw->scratch[6] == ~PICOWOTA_BOOTLOADER_ENTRY_MAGIC);
  444. return !gpio_get(BOOTLOADER_ENTRY_PIN) || wd_says_so;
  445. }
  446. static void network_deinit()
  447. {
  448. #if PICOWOTA_WIFI_AP == 1
  449. dhcp_server_deinit(&dhcp_server);
  450. #endif
  451. cyw43_arch_deinit();
  452. }
  453. int main()
  454. {
  455. err_t err;
  456. gpio_init(BOOTLOADER_ENTRY_PIN);
  457. gpio_pull_up(BOOTLOADER_ENTRY_PIN);
  458. gpio_set_dir(BOOTLOADER_ENTRY_PIN, 0);
  459. sleep_ms(10);
  460. struct image_header *hdr = (struct image_header *)(XIP_BASE + IMAGE_HEADER_OFFSET);
  461. if (!should_stay_in_bootloader() && image_header_ok(hdr)) {
  462. uint32_t vtor = *((uint32_t *)(XIP_BASE + IMAGE_HEADER_OFFSET));
  463. disable_interrupts();
  464. reset_peripherals();
  465. jump_to_vtor(vtor);
  466. }
  467. DBG_PRINTF_INIT();
  468. queue_init(&event_queue, sizeof(struct event), EVENT_QUEUE_LENGTH);
  469. if (cyw43_arch_init()) {
  470. DBG_PRINTF("failed to initialise\n");
  471. return 1;
  472. }
  473. #if PICOWOTA_WIFI_AP == 1
  474. cyw43_arch_enable_ap_mode(wifi_ssid, wifi_pass, CYW43_AUTH_WPA2_AES_PSK);
  475. DBG_PRINTF("Enabled the WiFi AP.\n");
  476. ip4_addr_t gw, mask;
  477. IP4_ADDR(&gw, 192, 168, 4, 1);
  478. IP4_ADDR(&mask, 255, 255, 255, 0);
  479. dhcp_server_t dhcp_server;
  480. dhcp_server_init(&dhcp_server, &gw, &mask);
  481. DBG_PRINTF("Started the DHCP server.\n");
  482. #else
  483. cyw43_arch_enable_sta_mode();
  484. DBG_PRINTF("Connecting to WiFi...\n");
  485. if (cyw43_arch_wifi_connect_timeout_ms(wifi_ssid, wifi_pass, CYW43_AUTH_WPA2_AES_PSK, 30000)) {
  486. DBG_PRINTF("failed to connect.\n");
  487. return 1;
  488. } else {
  489. DBG_PRINTF("Connected.\n");
  490. }
  491. #endif
  492. critical_section_init(&critical_section);
  493. const struct comm_command *cmds[] = {
  494. &sync_cmd,
  495. &read_cmd,
  496. &csum_cmd,
  497. &crc_cmd,
  498. &erase_cmd,
  499. &write_cmd,
  500. &seal_cmd,
  501. &go_cmd,
  502. &info_cmd,
  503. &reboot_cmd,
  504. };
  505. struct tcp_comm_ctx *tcp = tcp_comm_new(cmds, sizeof(cmds) / sizeof(cmds[0]), CMD_SYNC);
  506. struct event ev = {
  507. .type = EVENT_TYPE_SERVER_DONE,
  508. };
  509. queue_add_blocking(&event_queue, &ev);
  510. for ( ; ; ) {
  511. while (queue_try_remove(&event_queue, &ev)) {
  512. switch (ev.type) {
  513. case EVENT_TYPE_SERVER_DONE:
  514. err = tcp_comm_listen(tcp, TCP_PORT);
  515. if (err != ERR_OK) {
  516. DBG_PRINTF("Failed to start server: %d\n", err);
  517. }
  518. break;
  519. case EVENT_TYPE_REBOOT:
  520. tcp_comm_server_close(tcp);
  521. network_deinit();
  522. picowota_reboot(ev.reboot.to_bootloader);
  523. /* Should never get here */
  524. break;
  525. case EVENT_TYPE_GO:
  526. tcp_comm_server_close(tcp);
  527. network_deinit();
  528. disable_interrupts();
  529. reset_peripherals();
  530. jump_to_vtor(ev.go.vtor);
  531. /* Should never get here */
  532. break;
  533. };
  534. }
  535. cyw43_arch_poll();
  536. sleep_ms(5);
  537. }
  538. network_deinit();
  539. return 0;
  540. }