Naze32 clone with Frysky receiver
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LPC17xx.h 35KB

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  1. /**************************************************************************//**
  2. * @file LPC17xx.h
  3. * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
  4. * NXP LPC17xx Device Series
  5. * @version: V1.09
  6. * @date: 17. March 2010
  7. *
  8. * @note
  9. * Copyright (C) 2009 ARM Limited. All rights reserved.
  10. *
  11. * @par
  12. * ARM Limited (ARM) is supplying this software for use with Cortex-M
  13. * processor based microcontrollers. This file can be freely distributed
  14. * within development tools that are supporting such ARM based processors.
  15. *
  16. * @par
  17. * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  18. * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  19. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  20. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  21. * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  22. *
  23. ******************************************************************************/
  24. #ifndef __LPC17xx_H__
  25. #define __LPC17xx_H__
  26. /*
  27. * ==========================================================================
  28. * ---------- Interrupt Number Definition -----------------------------------
  29. * ==========================================================================
  30. */
  31. typedef enum IRQn
  32. {
  33. /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
  34. NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
  35. MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
  36. BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
  37. UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
  38. SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
  39. DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
  40. PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
  41. SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
  42. /****** LPC17xx Specific Interrupt Numbers *******************************************************/
  43. WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
  44. TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
  45. TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
  46. TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
  47. TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
  48. UART0_IRQn = 5, /*!< UART0 Interrupt */
  49. UART1_IRQn = 6, /*!< UART1 Interrupt */
  50. UART2_IRQn = 7, /*!< UART2 Interrupt */
  51. UART3_IRQn = 8, /*!< UART3 Interrupt */
  52. PWM1_IRQn = 9, /*!< PWM1 Interrupt */
  53. I2C0_IRQn = 10, /*!< I2C0 Interrupt */
  54. I2C1_IRQn = 11, /*!< I2C1 Interrupt */
  55. I2C2_IRQn = 12, /*!< I2C2 Interrupt */
  56. SPI_IRQn = 13, /*!< SPI Interrupt */
  57. SSP0_IRQn = 14, /*!< SSP0 Interrupt */
  58. SSP1_IRQn = 15, /*!< SSP1 Interrupt */
  59. PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
  60. RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
  61. EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
  62. EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
  63. EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
  64. EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
  65. ADC_IRQn = 22, /*!< A/D Converter Interrupt */
  66. BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
  67. USB_IRQn = 24, /*!< USB Interrupt */
  68. CAN_IRQn = 25, /*!< CAN Interrupt */
  69. DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
  70. I2S_IRQn = 27, /*!< I2S Interrupt */
  71. ENET_IRQn = 28, /*!< Ethernet Interrupt */
  72. RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
  73. MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
  74. QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
  75. PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
  76. USBActivity_IRQn = 33, /* USB Activity interrupt */
  77. CANActivity_IRQn = 34, /* CAN Activity interrupt */
  78. } IRQn_Type;
  79. /*
  80. * ==========================================================================
  81. * ----------- Processor and Core Peripheral Section ------------------------
  82. * ==========================================================================
  83. */
  84. /* Configuration of the Cortex-M3 Processor and Core Peripherals */
  85. #define __MPU_PRESENT 1 /*!< MPU present or not */
  86. #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
  87. #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
  88. #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
  89. #include "system_LPC17xx.h" /* System Header */
  90. /******************************************************************************/
  91. /* Device Specific Peripheral registers structures */
  92. /******************************************************************************/
  93. #if defined ( __CC_ARM )
  94. #pragma anon_unions
  95. #endif
  96. /*------------- System Control (SC) ------------------------------------------*/
  97. typedef struct
  98. {
  99. __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
  100. uint32_t RESERVED0[31];
  101. __IO uint32_t PLL0CON; /* Clocking and Power Control */
  102. __IO uint32_t PLL0CFG;
  103. __I uint32_t PLL0STAT;
  104. __O uint32_t PLL0FEED;
  105. uint32_t RESERVED1[4];
  106. __IO uint32_t PLL1CON;
  107. __IO uint32_t PLL1CFG;
  108. __I uint32_t PLL1STAT;
  109. __O uint32_t PLL1FEED;
  110. uint32_t RESERVED2[4];
  111. __IO uint32_t PCON;
  112. __IO uint32_t PCONP;
  113. uint32_t RESERVED3[15];
  114. __IO uint32_t CCLKCFG;
  115. __IO uint32_t USBCLKCFG;
  116. __IO uint32_t CLKSRCSEL;
  117. __IO uint32_t CANSLEEPCLR;
  118. __IO uint32_t CANWAKEFLAGS;
  119. uint32_t RESERVED4[10];
  120. __IO uint32_t EXTINT; /* External Interrupts */
  121. uint32_t RESERVED5;
  122. __IO uint32_t EXTMODE;
  123. __IO uint32_t EXTPOLAR;
  124. uint32_t RESERVED6[12];
  125. __IO uint32_t RSID; /* Reset */
  126. uint32_t RESERVED7[7];
  127. __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
  128. __IO uint32_t IRCTRIM; /* Clock Dividers */
  129. __IO uint32_t PCLKSEL0;
  130. __IO uint32_t PCLKSEL1;
  131. uint32_t RESERVED8[4];
  132. __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
  133. __IO uint32_t DMAREQSEL;
  134. __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
  135. } LPC_SC_TypeDef;
  136. /*------------- Pin Connect Block (PINCON) -----------------------------------*/
  137. typedef struct
  138. {
  139. __IO uint32_t PINSEL0;
  140. __IO uint32_t PINSEL1;
  141. __IO uint32_t PINSEL2;
  142. __IO uint32_t PINSEL3;
  143. __IO uint32_t PINSEL4;
  144. __IO uint32_t PINSEL5;
  145. __IO uint32_t PINSEL6;
  146. __IO uint32_t PINSEL7;
  147. __IO uint32_t PINSEL8;
  148. __IO uint32_t PINSEL9;
  149. __IO uint32_t PINSEL10;
  150. uint32_t RESERVED0[5];
  151. __IO uint32_t PINMODE0;
  152. __IO uint32_t PINMODE1;
  153. __IO uint32_t PINMODE2;
  154. __IO uint32_t PINMODE3;
  155. __IO uint32_t PINMODE4;
  156. __IO uint32_t PINMODE5;
  157. __IO uint32_t PINMODE6;
  158. __IO uint32_t PINMODE7;
  159. __IO uint32_t PINMODE8;
  160. __IO uint32_t PINMODE9;
  161. __IO uint32_t PINMODE_OD0;
  162. __IO uint32_t PINMODE_OD1;
  163. __IO uint32_t PINMODE_OD2;
  164. __IO uint32_t PINMODE_OD3;
  165. __IO uint32_t PINMODE_OD4;
  166. __IO uint32_t I2CPADCFG;
  167. } LPC_PINCON_TypeDef;
  168. /*------------- General Purpose Input/Output (GPIO) --------------------------*/
  169. typedef struct
  170. {
  171. union {
  172. __IO uint32_t FIODIR;
  173. struct {
  174. __IO uint16_t FIODIRL;
  175. __IO uint16_t FIODIRH;
  176. };
  177. struct {
  178. __IO uint8_t FIODIR0;
  179. __IO uint8_t FIODIR1;
  180. __IO uint8_t FIODIR2;
  181. __IO uint8_t FIODIR3;
  182. };
  183. };
  184. uint32_t RESERVED0[3];
  185. union {
  186. __IO uint32_t FIOMASK;
  187. struct {
  188. __IO uint16_t FIOMASKL;
  189. __IO uint16_t FIOMASKH;
  190. };
  191. struct {
  192. __IO uint8_t FIOMASK0;
  193. __IO uint8_t FIOMASK1;
  194. __IO uint8_t FIOMASK2;
  195. __IO uint8_t FIOMASK3;
  196. };
  197. };
  198. union {
  199. __IO uint32_t FIOPIN;
  200. struct {
  201. __IO uint16_t FIOPINL;
  202. __IO uint16_t FIOPINH;
  203. };
  204. struct {
  205. __IO uint8_t FIOPIN0;
  206. __IO uint8_t FIOPIN1;
  207. __IO uint8_t FIOPIN2;
  208. __IO uint8_t FIOPIN3;
  209. };
  210. };
  211. union {
  212. __IO uint32_t FIOSET;
  213. struct {
  214. __IO uint16_t FIOSETL;
  215. __IO uint16_t FIOSETH;
  216. };
  217. struct {
  218. __IO uint8_t FIOSET0;
  219. __IO uint8_t FIOSET1;
  220. __IO uint8_t FIOSET2;
  221. __IO uint8_t FIOSET3;
  222. };
  223. };
  224. union {
  225. __O uint32_t FIOCLR;
  226. struct {
  227. __O uint16_t FIOCLRL;
  228. __O uint16_t FIOCLRH;
  229. };
  230. struct {
  231. __O uint8_t FIOCLR0;
  232. __O uint8_t FIOCLR1;
  233. __O uint8_t FIOCLR2;
  234. __O uint8_t FIOCLR3;
  235. };
  236. };
  237. } LPC_GPIO_TypeDef;
  238. typedef struct
  239. {
  240. __I uint32_t IntStatus;
  241. __I uint32_t IO0IntStatR;
  242. __I uint32_t IO0IntStatF;
  243. __O uint32_t IO0IntClr;
  244. __IO uint32_t IO0IntEnR;
  245. __IO uint32_t IO0IntEnF;
  246. uint32_t RESERVED0[3];
  247. __I uint32_t IO2IntStatR;
  248. __I uint32_t IO2IntStatF;
  249. __O uint32_t IO2IntClr;
  250. __IO uint32_t IO2IntEnR;
  251. __IO uint32_t IO2IntEnF;
  252. } LPC_GPIOINT_TypeDef;
  253. /*------------- Timer (TIM) --------------------------------------------------*/
  254. typedef struct
  255. {
  256. __IO uint32_t IR;
  257. __IO uint32_t TCR;
  258. __IO uint32_t TC;
  259. __IO uint32_t PR;
  260. __IO uint32_t PC;
  261. __IO uint32_t MCR;
  262. __IO uint32_t MR0;
  263. __IO uint32_t MR1;
  264. __IO uint32_t MR2;
  265. __IO uint32_t MR3;
  266. __IO uint32_t CCR;
  267. __I uint32_t CR0;
  268. __I uint32_t CR1;
  269. uint32_t RESERVED0[2];
  270. __IO uint32_t EMR;
  271. uint32_t RESERVED1[12];
  272. __IO uint32_t CTCR;
  273. } LPC_TIM_TypeDef;
  274. /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
  275. typedef struct
  276. {
  277. __IO uint32_t IR;
  278. __IO uint32_t TCR;
  279. __IO uint32_t TC;
  280. __IO uint32_t PR;
  281. __IO uint32_t PC;
  282. __IO uint32_t MCR;
  283. __IO uint32_t MR0;
  284. __IO uint32_t MR1;
  285. __IO uint32_t MR2;
  286. __IO uint32_t MR3;
  287. __IO uint32_t CCR;
  288. __I uint32_t CR0;
  289. __I uint32_t CR1;
  290. __I uint32_t CR2;
  291. __I uint32_t CR3;
  292. uint32_t RESERVED0;
  293. __IO uint32_t MR4;
  294. __IO uint32_t MR5;
  295. __IO uint32_t MR6;
  296. __IO uint32_t PCR;
  297. __IO uint32_t LER;
  298. uint32_t RESERVED1[7];
  299. __IO uint32_t CTCR;
  300. } LPC_PWM_TypeDef;
  301. /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
  302. typedef struct
  303. {
  304. union {
  305. __I uint8_t RBR;
  306. __O uint8_t THR;
  307. __IO uint8_t DLL;
  308. uint32_t RESERVED0;
  309. };
  310. union {
  311. __IO uint8_t DLM;
  312. __IO uint32_t IER;
  313. };
  314. union {
  315. __I uint32_t IIR;
  316. __O uint8_t FCR;
  317. };
  318. __IO uint8_t LCR;
  319. uint8_t RESERVED1[7];
  320. __I uint8_t LSR;
  321. uint8_t RESERVED2[7];
  322. __IO uint8_t SCR;
  323. uint8_t RESERVED3[3];
  324. __IO uint32_t ACR;
  325. __IO uint8_t ICR;
  326. uint8_t RESERVED4[3];
  327. __IO uint8_t FDR;
  328. uint8_t RESERVED5[7];
  329. __IO uint8_t TER;
  330. uint8_t RESERVED6[39];
  331. __IO uint32_t FIFOLVL;
  332. } LPC_UART_TypeDef;
  333. typedef struct
  334. {
  335. union {
  336. __I uint8_t RBR;
  337. __O uint8_t THR;
  338. __IO uint8_t DLL;
  339. uint32_t RESERVED0;
  340. };
  341. union {
  342. __IO uint8_t DLM;
  343. __IO uint32_t IER;
  344. };
  345. union {
  346. __I uint32_t IIR;
  347. __O uint8_t FCR;
  348. };
  349. __IO uint8_t LCR;
  350. uint8_t RESERVED1[7];
  351. __I uint8_t LSR;
  352. uint8_t RESERVED2[7];
  353. __IO uint8_t SCR;
  354. uint8_t RESERVED3[3];
  355. __IO uint32_t ACR;
  356. __IO uint8_t ICR;
  357. uint8_t RESERVED4[3];
  358. __IO uint8_t FDR;
  359. uint8_t RESERVED5[7];
  360. __IO uint8_t TER;
  361. uint8_t RESERVED6[39];
  362. __IO uint32_t FIFOLVL;
  363. } LPC_UART0_TypeDef;
  364. typedef struct
  365. {
  366. union {
  367. __I uint8_t RBR;
  368. __O uint8_t THR;
  369. __IO uint8_t DLL;
  370. uint32_t RESERVED0;
  371. };
  372. union {
  373. __IO uint8_t DLM;
  374. __IO uint32_t IER;
  375. };
  376. union {
  377. __I uint32_t IIR;
  378. __O uint8_t FCR;
  379. };
  380. __IO uint8_t LCR;
  381. uint8_t RESERVED1[3];
  382. __IO uint8_t MCR;
  383. uint8_t RESERVED2[3];
  384. __I uint8_t LSR;
  385. uint8_t RESERVED3[3];
  386. __I uint8_t MSR;
  387. uint8_t RESERVED4[3];
  388. __IO uint8_t SCR;
  389. uint8_t RESERVED5[3];
  390. __IO uint32_t ACR;
  391. uint32_t RESERVED6;
  392. __IO uint32_t FDR;
  393. uint32_t RESERVED7;
  394. __IO uint8_t TER;
  395. uint8_t RESERVED8[27];
  396. __IO uint8_t RS485CTRL;
  397. uint8_t RESERVED9[3];
  398. __IO uint8_t ADRMATCH;
  399. uint8_t RESERVED10[3];
  400. __IO uint8_t RS485DLY;
  401. uint8_t RESERVED11[3];
  402. __IO uint32_t FIFOLVL;
  403. } LPC_UART1_TypeDef;
  404. /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
  405. typedef struct
  406. {
  407. __IO uint32_t SPCR;
  408. __I uint32_t SPSR;
  409. __IO uint32_t SPDR;
  410. __IO uint32_t SPCCR;
  411. uint32_t RESERVED0[3];
  412. __IO uint32_t SPINT;
  413. } LPC_SPI_TypeDef;
  414. /*------------- Synchronous Serial Communication (SSP) -----------------------*/
  415. typedef struct
  416. {
  417. __IO uint32_t CR0;
  418. __IO uint32_t CR1;
  419. __IO uint32_t DR;
  420. __I uint32_t SR;
  421. __IO uint32_t CPSR;
  422. __IO uint32_t IMSC;
  423. __IO uint32_t RIS;
  424. __IO uint32_t MIS;
  425. __IO uint32_t ICR;
  426. __IO uint32_t DMACR;
  427. } LPC_SSP_TypeDef;
  428. /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
  429. typedef struct
  430. {
  431. __IO uint32_t I2CONSET;
  432. __I uint32_t I2STAT;
  433. __IO uint32_t I2DAT;
  434. __IO uint32_t I2ADR0;
  435. __IO uint32_t I2SCLH;
  436. __IO uint32_t I2SCLL;
  437. __O uint32_t I2CONCLR;
  438. __IO uint32_t MMCTRL;
  439. __IO uint32_t I2ADR1;
  440. __IO uint32_t I2ADR2;
  441. __IO uint32_t I2ADR3;
  442. __I uint32_t I2DATA_BUFFER;
  443. __IO uint32_t I2MASK0;
  444. __IO uint32_t I2MASK1;
  445. __IO uint32_t I2MASK2;
  446. __IO uint32_t I2MASK3;
  447. } LPC_I2C_TypeDef;
  448. /*------------- Inter IC Sound (I2S) -----------------------------------------*/
  449. typedef struct
  450. {
  451. __IO uint32_t I2SDAO;
  452. __IO uint32_t I2SDAI;
  453. __O uint32_t I2STXFIFO;
  454. __I uint32_t I2SRXFIFO;
  455. __I uint32_t I2SSTATE;
  456. __IO uint32_t I2SDMA1;
  457. __IO uint32_t I2SDMA2;
  458. __IO uint32_t I2SIRQ;
  459. __IO uint32_t I2STXRATE;
  460. __IO uint32_t I2SRXRATE;
  461. __IO uint32_t I2STXBITRATE;
  462. __IO uint32_t I2SRXBITRATE;
  463. __IO uint32_t I2STXMODE;
  464. __IO uint32_t I2SRXMODE;
  465. } LPC_I2S_TypeDef;
  466. /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
  467. typedef struct
  468. {
  469. __IO uint32_t RICOMPVAL;
  470. __IO uint32_t RIMASK;
  471. __IO uint8_t RICTRL;
  472. uint8_t RESERVED0[3];
  473. __IO uint32_t RICOUNTER;
  474. } LPC_RIT_TypeDef;
  475. /*------------- Real-Time Clock (RTC) ----------------------------------------*/
  476. typedef struct
  477. {
  478. __IO uint8_t ILR;
  479. uint8_t RESERVED0[7];
  480. __IO uint8_t CCR;
  481. uint8_t RESERVED1[3];
  482. __IO uint8_t CIIR;
  483. uint8_t RESERVED2[3];
  484. __IO uint8_t AMR;
  485. uint8_t RESERVED3[3];
  486. __I uint32_t CTIME0;
  487. __I uint32_t CTIME1;
  488. __I uint32_t CTIME2;
  489. __IO uint8_t SEC;
  490. uint8_t RESERVED4[3];
  491. __IO uint8_t MIN;
  492. uint8_t RESERVED5[3];
  493. __IO uint8_t HOUR;
  494. uint8_t RESERVED6[3];
  495. __IO uint8_t DOM;
  496. uint8_t RESERVED7[3];
  497. __IO uint8_t DOW;
  498. uint8_t RESERVED8[3];
  499. __IO uint16_t DOY;
  500. uint16_t RESERVED9;
  501. __IO uint8_t MONTH;
  502. uint8_t RESERVED10[3];
  503. __IO uint16_t YEAR;
  504. uint16_t RESERVED11;
  505. __IO uint32_t CALIBRATION;
  506. __IO uint32_t GPREG0;
  507. __IO uint32_t GPREG1;
  508. __IO uint32_t GPREG2;
  509. __IO uint32_t GPREG3;
  510. __IO uint32_t GPREG4;
  511. __IO uint8_t RTC_AUXEN;
  512. uint8_t RESERVED12[3];
  513. __IO uint8_t RTC_AUX;
  514. uint8_t RESERVED13[3];
  515. __IO uint8_t ALSEC;
  516. uint8_t RESERVED14[3];
  517. __IO uint8_t ALMIN;
  518. uint8_t RESERVED15[3];
  519. __IO uint8_t ALHOUR;
  520. uint8_t RESERVED16[3];
  521. __IO uint8_t ALDOM;
  522. uint8_t RESERVED17[3];
  523. __IO uint8_t ALDOW;
  524. uint8_t RESERVED18[3];
  525. __IO uint16_t ALDOY;
  526. uint16_t RESERVED19;
  527. __IO uint8_t ALMON;
  528. uint8_t RESERVED20[3];
  529. __IO uint16_t ALYEAR;
  530. uint16_t RESERVED21;
  531. } LPC_RTC_TypeDef;
  532. /*------------- Watchdog Timer (WDT) -----------------------------------------*/
  533. typedef struct
  534. {
  535. __IO uint8_t WDMOD;
  536. uint8_t RESERVED0[3];
  537. __IO uint32_t WDTC;
  538. __O uint8_t WDFEED;
  539. uint8_t RESERVED1[3];
  540. __I uint32_t WDTV;
  541. __IO uint32_t WDCLKSEL;
  542. } LPC_WDT_TypeDef;
  543. /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
  544. typedef struct
  545. {
  546. __IO uint32_t ADCR;
  547. __IO uint32_t ADGDR;
  548. uint32_t RESERVED0;
  549. __IO uint32_t ADINTEN;
  550. __I uint32_t ADDR0;
  551. __I uint32_t ADDR1;
  552. __I uint32_t ADDR2;
  553. __I uint32_t ADDR3;
  554. __I uint32_t ADDR4;
  555. __I uint32_t ADDR5;
  556. __I uint32_t ADDR6;
  557. __I uint32_t ADDR7;
  558. __I uint32_t ADSTAT;
  559. __IO uint32_t ADTRM;
  560. } LPC_ADC_TypeDef;
  561. /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
  562. typedef struct
  563. {
  564. __IO uint32_t DACR;
  565. __IO uint32_t DACCTRL;
  566. __IO uint16_t DACCNTVAL;
  567. } LPC_DAC_TypeDef;
  568. /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
  569. typedef struct
  570. {
  571. __I uint32_t MCCON;
  572. __O uint32_t MCCON_SET;
  573. __O uint32_t MCCON_CLR;
  574. __I uint32_t MCCAPCON;
  575. __O uint32_t MCCAPCON_SET;
  576. __O uint32_t MCCAPCON_CLR;
  577. __IO uint32_t MCTIM0;
  578. __IO uint32_t MCTIM1;
  579. __IO uint32_t MCTIM2;
  580. __IO uint32_t MCPER0;
  581. __IO uint32_t MCPER1;
  582. __IO uint32_t MCPER2;
  583. __IO uint32_t MCPW0;
  584. __IO uint32_t MCPW1;
  585. __IO uint32_t MCPW2;
  586. __IO uint32_t MCDEADTIME;
  587. __IO uint32_t MCCCP;
  588. __IO uint32_t MCCR0;
  589. __IO uint32_t MCCR1;
  590. __IO uint32_t MCCR2;
  591. __I uint32_t MCINTEN;
  592. __O uint32_t MCINTEN_SET;
  593. __O uint32_t MCINTEN_CLR;
  594. __I uint32_t MCCNTCON;
  595. __O uint32_t MCCNTCON_SET;
  596. __O uint32_t MCCNTCON_CLR;
  597. __I uint32_t MCINTFLAG;
  598. __O uint32_t MCINTFLAG_SET;
  599. __O uint32_t MCINTFLAG_CLR;
  600. __O uint32_t MCCAP_CLR;
  601. } LPC_MCPWM_TypeDef;
  602. /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
  603. typedef struct
  604. {
  605. __O uint32_t QEICON;
  606. __I uint32_t QEISTAT;
  607. __IO uint32_t QEICONF;
  608. __I uint32_t QEIPOS;
  609. __IO uint32_t QEIMAXPOS;
  610. __IO uint32_t CMPOS0;
  611. __IO uint32_t CMPOS1;
  612. __IO uint32_t CMPOS2;
  613. __I uint32_t INXCNT;
  614. __IO uint32_t INXCMP;
  615. __IO uint32_t QEILOAD;
  616. __I uint32_t QEITIME;
  617. __I uint32_t QEIVEL;
  618. __I uint32_t QEICAP;
  619. __IO uint32_t VELCOMP;
  620. __IO uint32_t FILTER;
  621. uint32_t RESERVED0[998];
  622. __O uint32_t QEIIEC;
  623. __O uint32_t QEIIES;
  624. __I uint32_t QEIINTSTAT;
  625. __I uint32_t QEIIE;
  626. __O uint32_t QEICLR;
  627. __O uint32_t QEISET;
  628. } LPC_QEI_TypeDef;
  629. /*------------- Controller Area Network (CAN) --------------------------------*/
  630. typedef struct
  631. {
  632. __IO uint32_t mask[512]; /* ID Masks */
  633. } LPC_CANAF_RAM_TypeDef;
  634. typedef struct /* Acceptance Filter Registers */
  635. {
  636. __IO uint32_t AFMR;
  637. __IO uint32_t SFF_sa;
  638. __IO uint32_t SFF_GRP_sa;
  639. __IO uint32_t EFF_sa;
  640. __IO uint32_t EFF_GRP_sa;
  641. __IO uint32_t ENDofTable;
  642. __I uint32_t LUTerrAd;
  643. __I uint32_t LUTerr;
  644. __IO uint32_t FCANIE;
  645. __IO uint32_t FCANIC0;
  646. __IO uint32_t FCANIC1;
  647. } LPC_CANAF_TypeDef;
  648. typedef struct /* Central Registers */
  649. {
  650. __I uint32_t CANTxSR;
  651. __I uint32_t CANRxSR;
  652. __I uint32_t CANMSR;
  653. } LPC_CANCR_TypeDef;
  654. typedef struct /* Controller Registers */
  655. {
  656. __IO uint32_t MOD;
  657. __O uint32_t CMR;
  658. __IO uint32_t GSR;
  659. __I uint32_t ICR;
  660. __IO uint32_t IER;
  661. __IO uint32_t BTR;
  662. __IO uint32_t EWL;
  663. __I uint32_t SR;
  664. __IO uint32_t RFS;
  665. __IO uint32_t RID;
  666. __IO uint32_t RDA;
  667. __IO uint32_t RDB;
  668. __IO uint32_t TFI1;
  669. __IO uint32_t TID1;
  670. __IO uint32_t TDA1;
  671. __IO uint32_t TDB1;
  672. __IO uint32_t TFI2;
  673. __IO uint32_t TID2;
  674. __IO uint32_t TDA2;
  675. __IO uint32_t TDB2;
  676. __IO uint32_t TFI3;
  677. __IO uint32_t TID3;
  678. __IO uint32_t TDA3;
  679. __IO uint32_t TDB3;
  680. } LPC_CAN_TypeDef;
  681. /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
  682. typedef struct /* Common Registers */
  683. {
  684. __I uint32_t DMACIntStat;
  685. __I uint32_t DMACIntTCStat;
  686. __O uint32_t DMACIntTCClear;
  687. __I uint32_t DMACIntErrStat;
  688. __O uint32_t DMACIntErrClr;
  689. __I uint32_t DMACRawIntTCStat;
  690. __I uint32_t DMACRawIntErrStat;
  691. __I uint32_t DMACEnbldChns;
  692. __IO uint32_t DMACSoftBReq;
  693. __IO uint32_t DMACSoftSReq;
  694. __IO uint32_t DMACSoftLBReq;
  695. __IO uint32_t DMACSoftLSReq;
  696. __IO uint32_t DMACConfig;
  697. __IO uint32_t DMACSync;
  698. } LPC_GPDMA_TypeDef;
  699. typedef struct /* Channel Registers */
  700. {
  701. __IO uint32_t DMACCSrcAddr;
  702. __IO uint32_t DMACCDestAddr;
  703. __IO uint32_t DMACCLLI;
  704. __IO uint32_t DMACCControl;
  705. __IO uint32_t DMACCConfig;
  706. } LPC_GPDMACH_TypeDef;
  707. /*------------- Universal Serial Bus (USB) -----------------------------------*/
  708. typedef struct
  709. {
  710. __I uint32_t HcRevision; /* USB Host Registers */
  711. __IO uint32_t HcControl;
  712. __IO uint32_t HcCommandStatus;
  713. __IO uint32_t HcInterruptStatus;
  714. __IO uint32_t HcInterruptEnable;
  715. __IO uint32_t HcInterruptDisable;
  716. __IO uint32_t HcHCCA;
  717. __I uint32_t HcPeriodCurrentED;
  718. __IO uint32_t HcControlHeadED;
  719. __IO uint32_t HcControlCurrentED;
  720. __IO uint32_t HcBulkHeadED;
  721. __IO uint32_t HcBulkCurrentED;
  722. __I uint32_t HcDoneHead;
  723. __IO uint32_t HcFmInterval;
  724. __I uint32_t HcFmRemaining;
  725. __I uint32_t HcFmNumber;
  726. __IO uint32_t HcPeriodicStart;
  727. __IO uint32_t HcLSTreshold;
  728. __IO uint32_t HcRhDescriptorA;
  729. __IO uint32_t HcRhDescriptorB;
  730. __IO uint32_t HcRhStatus;
  731. __IO uint32_t HcRhPortStatus1;
  732. __IO uint32_t HcRhPortStatus2;
  733. uint32_t RESERVED0[40];
  734. __I uint32_t Module_ID;
  735. __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
  736. __IO uint32_t OTGIntEn;
  737. __O uint32_t OTGIntSet;
  738. __O uint32_t OTGIntClr;
  739. __IO uint32_t OTGStCtrl;
  740. __IO uint32_t OTGTmr;
  741. uint32_t RESERVED1[58];
  742. __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
  743. __IO uint32_t USBDevIntEn;
  744. __O uint32_t USBDevIntClr;
  745. __O uint32_t USBDevIntSet;
  746. __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
  747. __I uint32_t USBCmdData;
  748. __I uint32_t USBRxData; /* USB Device Transfer Registers */
  749. __O uint32_t USBTxData;
  750. __I uint32_t USBRxPLen;
  751. __O uint32_t USBTxPLen;
  752. __IO uint32_t USBCtrl;
  753. __O uint32_t USBDevIntPri;
  754. __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
  755. __IO uint32_t USBEpIntEn;
  756. __O uint32_t USBEpIntClr;
  757. __O uint32_t USBEpIntSet;
  758. __O uint32_t USBEpIntPri;
  759. __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
  760. __O uint32_t USBEpInd;
  761. __IO uint32_t USBMaxPSize;
  762. __I uint32_t USBDMARSt; /* USB Device DMA Registers */
  763. __O uint32_t USBDMARClr;
  764. __O uint32_t USBDMARSet;
  765. uint32_t RESERVED2[9];
  766. __IO uint32_t USBUDCAH;
  767. __I uint32_t USBEpDMASt;
  768. __O uint32_t USBEpDMAEn;
  769. __O uint32_t USBEpDMADis;
  770. __I uint32_t USBDMAIntSt;
  771. __IO uint32_t USBDMAIntEn;
  772. uint32_t RESERVED3[2];
  773. __I uint32_t USBEoTIntSt;
  774. __O uint32_t USBEoTIntClr;
  775. __O uint32_t USBEoTIntSet;
  776. __I uint32_t USBNDDRIntSt;
  777. __O uint32_t USBNDDRIntClr;
  778. __O uint32_t USBNDDRIntSet;
  779. __I uint32_t USBSysErrIntSt;
  780. __O uint32_t USBSysErrIntClr;
  781. __O uint32_t USBSysErrIntSet;
  782. uint32_t RESERVED4[15];
  783. union {
  784. __I uint32_t I2C_RX; /* USB OTG I2C Registers */
  785. __O uint32_t I2C_TX;
  786. };
  787. __I uint32_t I2C_STS;
  788. __IO uint32_t I2C_CTL;
  789. __IO uint32_t I2C_CLKHI;
  790. __O uint32_t I2C_CLKLO;
  791. uint32_t RESERVED5[824];
  792. union {
  793. __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
  794. __IO uint32_t OTGClkCtrl;
  795. };
  796. union {
  797. __I uint32_t USBClkSt;
  798. __I uint32_t OTGClkSt;
  799. };
  800. } LPC_USB_TypeDef;
  801. /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
  802. typedef struct
  803. {
  804. __IO uint32_t MAC1; /* MAC Registers */
  805. __IO uint32_t MAC2;
  806. __IO uint32_t IPGT;
  807. __IO uint32_t IPGR;
  808. __IO uint32_t CLRT;
  809. __IO uint32_t MAXF;
  810. __IO uint32_t SUPP;
  811. __IO uint32_t TEST;
  812. __IO uint32_t MCFG;
  813. __IO uint32_t MCMD;
  814. __IO uint32_t MADR;
  815. __O uint32_t MWTD;
  816. __I uint32_t MRDD;
  817. __I uint32_t MIND;
  818. uint32_t RESERVED0[2];
  819. __IO uint32_t SA0;
  820. __IO uint32_t SA1;
  821. __IO uint32_t SA2;
  822. uint32_t RESERVED1[45];
  823. __IO uint32_t Command; /* Control Registers */
  824. __I uint32_t Status;
  825. __IO uint32_t RxDescriptor;
  826. __IO uint32_t RxStatus;
  827. __IO uint32_t RxDescriptorNumber;
  828. __I uint32_t RxProduceIndex;
  829. __IO uint32_t RxConsumeIndex;
  830. __IO uint32_t TxDescriptor;
  831. __IO uint32_t TxStatus;
  832. __IO uint32_t TxDescriptorNumber;
  833. __IO uint32_t TxProduceIndex;
  834. __I uint32_t TxConsumeIndex;
  835. uint32_t RESERVED2[10];
  836. __I uint32_t TSV0;
  837. __I uint32_t TSV1;
  838. __I uint32_t RSV;
  839. uint32_t RESERVED3[3];
  840. __IO uint32_t FlowControlCounter;
  841. __I uint32_t FlowControlStatus;
  842. uint32_t RESERVED4[34];
  843. __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
  844. __IO uint32_t RxFilterWoLStatus;
  845. __IO uint32_t RxFilterWoLClear;
  846. uint32_t RESERVED5;
  847. __IO uint32_t HashFilterL;
  848. __IO uint32_t HashFilterH;
  849. uint32_t RESERVED6[882];
  850. __I uint32_t IntStatus; /* Module Control Registers */
  851. __IO uint32_t IntEnable;
  852. __O uint32_t IntClear;
  853. __O uint32_t IntSet;
  854. uint32_t RESERVED7;
  855. __IO uint32_t PowerDown;
  856. uint32_t RESERVED8;
  857. __IO uint32_t Module_ID;
  858. } LPC_EMAC_TypeDef;
  859. #if defined ( __CC_ARM )
  860. #pragma no_anon_unions
  861. #endif
  862. /******************************************************************************/
  863. /* Peripheral memory map */
  864. /******************************************************************************/
  865. /* Base addresses */
  866. #define LPC_FLASH_BASE (0x00000000UL)
  867. #define LPC_RAM_BASE (0x10000000UL)
  868. #define LPC_GPIO_BASE (0x2009C000UL)
  869. #define LPC_APB0_BASE (0x40000000UL)
  870. #define LPC_APB1_BASE (0x40080000UL)
  871. #define LPC_AHB_BASE (0x50000000UL)
  872. #define LPC_CM3_BASE (0xE0000000UL)
  873. /* APB0 peripherals */
  874. #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
  875. #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
  876. #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
  877. #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
  878. #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
  879. #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
  880. #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
  881. #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
  882. #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
  883. #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
  884. #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
  885. #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
  886. #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
  887. #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
  888. #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
  889. #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
  890. #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
  891. #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
  892. #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
  893. /* APB1 peripherals */
  894. #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
  895. #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
  896. #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
  897. #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
  898. #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
  899. #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
  900. #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
  901. #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
  902. #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
  903. #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
  904. #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
  905. #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
  906. /* AHB peripherals */
  907. #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
  908. #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
  909. #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
  910. #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
  911. #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
  912. #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
  913. #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
  914. #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
  915. #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
  916. #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
  917. #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
  918. /* GPIOs */
  919. #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
  920. #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
  921. #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
  922. #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
  923. #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
  924. /******************************************************************************/
  925. /* Peripheral declaration */
  926. /******************************************************************************/
  927. #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
  928. #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
  929. #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
  930. #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
  931. #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
  932. #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
  933. #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
  934. #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
  935. #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
  936. #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
  937. #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
  938. #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
  939. #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
  940. #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
  941. #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
  942. #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
  943. #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
  944. #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
  945. #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
  946. #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
  947. #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
  948. #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
  949. #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
  950. #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
  951. #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
  952. #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
  953. #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
  954. #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
  955. #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
  956. #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
  957. #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
  958. #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
  959. #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
  960. #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
  961. #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
  962. #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
  963. #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
  964. #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
  965. #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
  966. #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
  967. #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
  968. #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
  969. #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
  970. #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
  971. #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
  972. #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
  973. #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
  974. #endif // __LPC17xx_H__