Naze32 clone with Frysky receiver
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iface_cc2500.h 8.0KB

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  1. #ifndef _IFACE_CC2500_H_
  2. #define _IFACE_CC2500_H_
  3. enum {
  4. CC2500_00_IOCFG2 = 0x00, // GDO2 output pin configuration
  5. CC2500_01_IOCFG1 = 0x01, // GDO1 output pin configuration
  6. CC2500_02_IOCFG0 = 0x02, // GDO0 output pin configuration
  7. CC2500_03_FIFOTHR = 0x03, // RX FIFO and TX FIFO thresholds
  8. CC2500_04_SYNC1 = 0x04, // Sync word, high byte
  9. CC2500_05_SYNC0 = 0x05, // Sync word, low byte
  10. CC2500_06_PKTLEN = 0x06, // Packet length
  11. CC2500_07_PKTCTRL1 = 0x07, // Packet automation control
  12. CC2500_08_PKTCTRL0 = 0x08, // Packet automation control
  13. CC2500_09_ADDR = 0x09, // Device address
  14. CC2500_0A_CHANNR = 0x0A, // Channel number
  15. CC2500_0B_FSCTRL1 = 0x0B, // Frequency synthesizer control
  16. CC2500_0C_FSCTRL0 = 0x0C, // Frequency synthesizer control
  17. CC2500_0D_FREQ2 = 0x0D, // Frequency control word, high byte
  18. CC2500_0E_FREQ1 = 0x0E, // Frequency control word, middle byte
  19. CC2500_0F_FREQ0 = 0x0F, // Frequency control word, low byte
  20. CC2500_10_MDMCFG4 = 0x10, // Modem configuration
  21. CC2500_11_MDMCFG3 = 0x11, // Modem configuration
  22. CC2500_12_MDMCFG2 = 0x12, // Modem configuration
  23. CC2500_13_MDMCFG1 = 0x13, // Modem configuration
  24. CC2500_14_MDMCFG0 = 0x14, // Modem configuration
  25. CC2500_15_DEVIATN = 0x15, // Modem deviation setting
  26. CC2500_16_MCSM2 = 0x16, // Main Radio Cntrl State Machine config
  27. CC2500_17_MCSM1 = 0x17, // Main Radio Cntrl State Machine config
  28. CC2500_18_MCSM0 = 0x18, // Main Radio Cntrl State Machine config
  29. CC2500_19_FOCCFG = 0x19, // Frequency Offset Compensation config
  30. CC2500_1A_BSCFG = 0x1A, // Bit Synchronization configuration
  31. CC2500_1B_AGCCTRL2 = 0x1B, // AGC control
  32. CC2500_1C_AGCCTRL1 = 0x1C, // AGC control
  33. CC2500_1D_AGCCTRL0 = 0x1D, // AGC control
  34. CC2500_1E_WOREVT1 = 0x1E, // High byte Event 0 timeout
  35. CC2500_1F_WOREVT0 = 0x1F, // Low byte Event 0 timeout
  36. CC2500_20_WORCTRL = 0x20, // Wake On Radio control
  37. CC2500_21_FREND1 = 0x21, // Front end RX configuration
  38. CC2500_22_FREND0 = 0x22, // Front end TX configuration
  39. CC2500_23_FSCAL3 = 0x23, // Frequency synthesizer calibration
  40. CC2500_24_FSCAL2 = 0x24, // Frequency synthesizer calibration
  41. CC2500_25_FSCAL1 = 0x25, // Frequency synthesizer calibration
  42. CC2500_26_FSCAL0 = 0x26, // Frequency synthesizer calibration
  43. CC2500_27_RCCTRL1 = 0x27, // RC oscillator configuration
  44. CC2500_28_RCCTRL0 = 0x28, // RC oscillator configuration
  45. CC2500_29_FSTEST = 0x29, // Frequency synthesizer cal control
  46. CC2500_2A_PTEST = 0x2A, // Production test
  47. CC2500_2B_AGCTEST = 0x2B, // AGC test
  48. CC2500_2C_TEST2 = 0x2C, // Various test settings
  49. CC2500_2D_TEST1 = 0x2D, // Various test settings
  50. CC2500_2E_TEST0 = 0x2E, // Various test settings
  51. // Status registers
  52. CC2500_30_PARTNUM = 0x30, // Part number
  53. CC2500_31_VERSION = 0x31, // Current version number
  54. CC2500_32_FREQEST = 0x32, // Frequency offset estimate
  55. CC2500_33_LQI = 0x33, // Demodulator estimate for link quality
  56. CC2500_34_RSSI = 0x34, // Received signal strength indication
  57. CC2500_35_MARCSTATE = 0x35, // Control state machine state
  58. CC2500_36_WORTIME1 = 0x36, // High byte of WOR timer
  59. CC2500_37_WORTIME0 = 0x37, // Low byte of WOR timer
  60. CC2500_38_PKTSTATUS = 0x38, // Current GDOx status and packet status
  61. CC2500_39_VCO_VC_DAC = 0x39, // Current setting from PLL cal module
  62. CC2500_3A_TXBYTES = 0x3A, // Underflow and # of bytes in TXFIFO
  63. CC2500_3B_RXBYTES = 0x3B, // Overflow and # of bytes in RXFIFO
  64. // Multi byte memory locations
  65. CC2500_3E_PATABLE = 0x3E,
  66. CC2500_3F_TXFIFO = 0x3F,
  67. CC2500_3F_RXFIFO = 0x3F,
  68. };
  69. // Definitions for burst/single access to registers
  70. #define CC2500_WRITE_SINGLE 0x00
  71. #define CC2500_WRITE_BURST 0x40
  72. #define CC2500_READ_SINGLE 0x80
  73. #define CC2500_READ_BURST 0xC0
  74. // Strobe commands
  75. #define CC2500_SRES 0x30 // Reset chip.
  76. #define CC2500_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1).
  77. // If in RX/TX: Go to a wait state where only the synthesizer is
  78. // running (for quick RX / TX turnaround).
  79. #define CC2500_SXOFF 0x32 // Turn off crystal oscillator.
  80. #define CC2500_SCAL 0x33 // Calibrate frequency synthesizer and turn it off
  81. // (enables quick start).
  82. #define CC2500_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and
  83. // MCSM0.FS_AUTOCAL=1.
  84. #define CC2500_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if
  85. // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled:
  86. // Only go to TX if channel is clear.
  87. #define CC2500_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit
  88. // Wake-On-Radio mode if applicable.
  89. #define CC2500_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer
  90. #define CC2500_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio)
  91. #define CC2500_SPWD 0x39 // Enter power down mode when CSn goes high.
  92. #define CC2500_SFRX 0x3A // Flush the RX FIFO buffer.
  93. #define CC2500_SFTX 0x3B // Flush the TX FIFO buffer.
  94. #define CC2500_SWORRST 0x3C // Reset real time clock.
  95. #define CC2500_SNOP 0x3D // No operation. May be used to pad strobe commands to two
  96. // bytes for simpler software.
  97. //----------------------------------------------------------------------------------
  98. // Chip Status Byte
  99. //----------------------------------------------------------------------------------
  100. // Bit fields in the chip status byte
  101. #define CC2500_STATUS_CHIP_RDYn_BM 0x80
  102. #define CC2500_STATUS_STATE_BM 0x70
  103. #define CC2500_STATUS_FIFO_BYTES_AVAILABLE_BM 0x0F
  104. // Chip states
  105. #define CC2500_STATE_IDLE 0x00
  106. #define CC2500_STATE_RX 0x10
  107. #define CC2500_STATE_TX 0x20
  108. #define CC2500_STATE_FSTXON 0x30
  109. #define CC2500_STATE_CALIBRATE 0x40
  110. #define CC2500_STATE_SETTLING 0x50
  111. #define CC2500_STATE_RX_OVERFLOW 0x60
  112. #define CC2500_STATE_TX_UNDERFLOW 0x70
  113. //----------------------------------------------------------------------------------
  114. // Other register bit fields
  115. //----------------------------------------------------------------------------------
  116. #define CC2500_LQI_CRC_OK_BM 0x80
  117. #define CC2500_LQI_EST_BM 0x7F
  118. //void CC2500_WriteReg(u8 addr, u8 data);
  119. //u8 CC2500_ReadReg(u8 addr);
  120. //void CC2500_Reset();
  121. //void CC2500_Strobe(u8 cmd);
  122. //void CC2500_WriteData(u8 *packet, u8 length);
  123. //void CC2500_ReadData(u8 *dpbuffer, int len);
  124. #endif