|
@@ -101,8 +101,24 @@ bool SDIO_ReadBlock_DMA(uint32_t blockAddress, uint8_t *data) {
|
101
|
101
|
return false;
|
102
|
102
|
}
|
103
|
103
|
|
104
|
|
- while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) {}
|
|
104
|
+ while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) { /* wait */ }
|
|
105
|
+
|
|
106
|
+ //If there were SDIO errors, do not wait DMA.
|
|
107
|
+ if (SDIO->STA & SDIO_STA_TRX_ERROR_FLAGS) {
|
|
108
|
+ SDIO_CLEAR_FLAG(SDIO_ICR_CMD_FLAGS | SDIO_ICR_DATA_FLAGS);
|
|
109
|
+ dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
|
|
110
|
+ return false;
|
|
111
|
+ }
|
|
112
|
+
|
|
113
|
+ //Wait for DMA transaction to complete
|
|
114
|
+ while ((DMA2_BASE->ISR & (DMA_ISR_TEIF4|DMA_ISR_TCIF4)) == 0 ) { /* wait */ }
|
105
|
115
|
|
|
116
|
+ if (DMA2_BASE->ISR & DMA_ISR_TEIF4) {
|
|
117
|
+ dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
|
|
118
|
+ SDIO_CLEAR_FLAG(SDIO_ICR_CMD_FLAGS | SDIO_ICR_DATA_FLAGS);
|
|
119
|
+ return false;
|
|
120
|
+ }
|
|
121
|
+
|
106
|
122
|
dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
|
107
|
123
|
|
108
|
124
|
if (SDIO->STA & SDIO_STA_RXDAVL) {
|
|
@@ -146,7 +162,7 @@ bool SDIO_WriteBlock(uint32_t blockAddress, const uint8_t *data) {
|
146
|
162
|
|
147
|
163
|
sdio_setup_transfer(SDIO_DATA_TIMEOUT * (F_CPU / 1000U), 512U, SDIO_BLOCKSIZE_512 | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN);
|
148
|
164
|
|
149
|
|
- while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) {}
|
|
165
|
+ while (!SDIO_GET_FLAG(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) { /* wait */ }
|
150
|
166
|
|
151
|
167
|
dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
|
152
|
168
|
|