Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)

- And implement the `backtrace()` function call

- Watchdog reset during SD Card initialization.
- Move `DebugMonitor` to `DebugMonitor_Due.cpp`.
- Since the watchdog is enabled on boot do extra resets during init.
- Have `thermalManager` do watchdog reset before its ISR starts to prevent reset.
- Ensure that timers are stopped before reprogramming them to address tone issues.
- Improve SAM3XE reset when reflashed through the native port.