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My Marlin configs for Fabrikator Mini and CTC i3 Pro B
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marlin/frameworks/CMSIS/LPC1768/include/LPC17xx.h

LPC17xx.h 37KB
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  1. /**************************************************************************//**

  2.  * @file     LPC17xx.h

  3.  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for

  4.  *           NXP LPC17xx Device Series

  5.  * @version: V1.09

  6.  * @date:    25. July. 2011

  7.  *

  8.  * @note

  9.  * Copyright (C) 2009 ARM Limited. All rights reserved.

  10.  *

  11.  * @par

  12.  * ARM Limited (ARM) is supplying this software for use with Cortex-M

  13.  * processor based microcontrollers.  This file can be freely distributed

  14.  * within development tools that are supporting such ARM based processors.

  15.  *

  16.  * @par

  17.  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED

  18.  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF

  19.  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.

  20.  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR

  21.  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

  22.  *

  23.  ******************************************************************************/

  24. 

  25. 

  26. #ifndef __LPC17xx_H__

  27. #define __LPC17xx_H__

  28. 

  29. /*

  30.  * ==========================================================================

  31.  * ---------- Interrupt Number Definition -----------------------------------

  32.  * ==========================================================================

  33.  */

  34. 

  35. /** @addtogroup LPC17xx_System

  36.  * @{

  37.  */

  38. 

  39. /** @brief IRQ interrupt source definition */

  40. typedef enum IRQn

  41. {

  42. /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/

  43.   NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */

  44.   MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */

  45.   BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */

  46.   UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */

  47.   SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */

  48.   DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */

  49.   PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */

  50.   SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */

  51. 

  52. /******  LPC17xx Specific Interrupt Numbers *******************************************************/

  53.   WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */

  54.   TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */

  55.   TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */

  56.   TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */

  57.   TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */

  58.   UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */

  59.   UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */

  60.   UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */

  61.   UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */

  62.   PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */

  63.   I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */

  64.   I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */

  65.   I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */

  66.   SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */

  67.   SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */

  68.   SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */

  69.   PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */

  70.   RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */

  71.   EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */

  72.   EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */

  73.   EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */

  74.   EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */

  75.   ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */

  76.   BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */

  77.   USB_IRQn                      = 24,       /*!< USB Interrupt                                    */

  78.   CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */

  79.   DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */

  80.   I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */

  81.   ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */

  82.   RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */

  83.   MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */

  84.   QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */

  85.   PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */

  86.   USBActivity_IRQn				= 33,		/*!< USB Activity Interrupt 						  */

  87.   CANActivity_IRQn				= 34		/*!< CAN Activity Interrupt 						  */

  88. } IRQn_Type;

  89. 

  90. 

  91. /*

  92.  * ==========================================================================

  93.  * ----------- Processor and Core Peripheral Section ------------------------

  94.  * ==========================================================================

  95.  */

  96. 

  97. /* Configuration of the Cortex-M3 Processor and Core Peripherals */

  98. #define __MPU_PRESENT             1         /*!< MPU present or not                               */

  99. #define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */

  100. #define __Vendor_SysTickConfig    1         /*!< Set to 1 if different SysTick Config is used     */

  101. 

  102. 

  103. #include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */

  104. #include "system_LPC17xx.h"                 /* System Header                                      */

  105. 

  106. 

  107. /******************************************************************************/

  108. /*                Device Specific Peripheral registers structures             */

  109. /******************************************************************************/

  110. 

  111. #if defined ( __CC_ARM   )

  112. #pragma anon_unions

  113. #endif

  114. 

  115. /*------------- System Control (SC) ------------------------------------------*/

  116. /** @brief System Control (SC) register structure definition */

  117. typedef struct

  118. {

  119.   __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */

  120.        uint32_t RESERVED0[31];

  121.   __IO uint32_t PLL0CON;                /* Clocking and Power Control         */

  122.   __IO uint32_t PLL0CFG;

  123.   __I  uint32_t PLL0STAT;

  124.   __O  uint32_t PLL0FEED;

  125.        uint32_t RESERVED1[4];

  126.   __IO uint32_t PLL1CON;

  127.   __IO uint32_t PLL1CFG;

  128.   __I  uint32_t PLL1STAT;

  129.   __O  uint32_t PLL1FEED;

  130.        uint32_t RESERVED2[4];

  131.   __IO uint32_t PCON;

  132.   __IO uint32_t PCONP;

  133.        uint32_t RESERVED3[15];

  134.   __IO uint32_t CCLKCFG;

  135.   __IO uint32_t USBCLKCFG;

  136.   __IO uint32_t CLKSRCSEL;

  137.   __IO uint32_t	CANSLEEPCLR;

  138.   __IO uint32_t	CANWAKEFLAGS;

  139.        uint32_t RESERVED4[10];

  140.   __IO uint32_t EXTINT;                 /* External Interrupts                */

  141.        uint32_t RESERVED5;

  142.   __IO uint32_t EXTMODE;

  143.   __IO uint32_t EXTPOLAR;

  144.        uint32_t RESERVED6[12];

  145.   __IO uint32_t RSID;                   /* Reset                              */

  146.        uint32_t RESERVED7[7];

  147.   __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */

  148.   __IO uint32_t IRCTRIM;                /* Clock Dividers                     */

  149.   __IO uint32_t PCLKSEL0;

  150.   __IO uint32_t PCLKSEL1;

  151.        uint32_t RESERVED8[4];

  152.   __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */

  153.   __IO uint32_t DMAREQSEL;

  154.   __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */

  155.  } LPC_SC_TypeDef;

  156. 

  157. /*------------- Pin Connect Block (PINCON) -----------------------------------*/

  158. /** @brief Pin Connect Block (PINCON) register structure definition */

  159. typedef struct

  160. {

  161.   __IO uint32_t PINSEL0;

  162.   __IO uint32_t PINSEL1;

  163.   __IO uint32_t PINSEL2;

  164.   __IO uint32_t PINSEL3;

  165.   __IO uint32_t PINSEL4;

  166.   __IO uint32_t PINSEL5;

  167.   __IO uint32_t PINSEL6;

  168.   __IO uint32_t PINSEL7;

  169.   __IO uint32_t PINSEL8;

  170.   __IO uint32_t PINSEL9;

  171.   __IO uint32_t PINSEL10;

  172.        uint32_t RESERVED0[5];

  173.   __IO uint32_t PINMODE0;

  174.   __IO uint32_t PINMODE1;

  175.   __IO uint32_t PINMODE2;

  176.   __IO uint32_t PINMODE3;

  177.   __IO uint32_t PINMODE4;

  178.   __IO uint32_t PINMODE5;

  179.   __IO uint32_t PINMODE6;

  180.   __IO uint32_t PINMODE7;

  181.   __IO uint32_t PINMODE8;

  182.   __IO uint32_t PINMODE9;

  183.   __IO uint32_t PINMODE_OD0;

  184.   __IO uint32_t PINMODE_OD1;

  185.   __IO uint32_t PINMODE_OD2;

  186.   __IO uint32_t PINMODE_OD3;

  187.   __IO uint32_t PINMODE_OD4;

  188.   __IO uint32_t I2CPADCFG;

  189. } LPC_PINCON_TypeDef;

  190. 

  191. /*------------- General Purpose Input/Output (GPIO) --------------------------*/

  192. /** @brief General Purpose Input/Output (GPIO) register structure definition */

  193. typedef struct

  194. {

  195.   union {

  196.     __IO uint32_t FIODIR;

  197.     struct {

  198.       __IO uint16_t FIODIRL;

  199.       __IO uint16_t FIODIRH;

  200.     };

  201.     struct {

  202.       __IO uint8_t  FIODIR0;

  203.       __IO uint8_t  FIODIR1;

  204.       __IO uint8_t  FIODIR2;

  205.       __IO uint8_t  FIODIR3;

  206.     };

  207.   };

  208.   uint32_t RESERVED0[3];

  209.   union {

  210.     __IO uint32_t FIOMASK;

  211.     struct {

  212.       __IO uint16_t FIOMASKL;

  213.       __IO uint16_t FIOMASKH;

  214.     };

  215.     struct {

  216.       __IO uint8_t  FIOMASK0;

  217.       __IO uint8_t  FIOMASK1;

  218.       __IO uint8_t  FIOMASK2;

  219.       __IO uint8_t  FIOMASK3;

  220.     };

  221.   };

  222.   union {

  223.     __IO uint32_t FIOPIN;

  224.     struct {

  225.       __IO uint16_t FIOPINL;

  226.       __IO uint16_t FIOPINH;

  227.     };

  228.     struct {

  229.       __IO uint8_t  FIOPIN0;

  230.       __IO uint8_t  FIOPIN1;

  231.       __IO uint8_t  FIOPIN2;

  232.       __IO uint8_t  FIOPIN3;

  233.     };

  234.   };

  235.   union {

  236.     __IO uint32_t FIOSET;

  237.     struct {

  238.       __IO uint16_t FIOSETL;

  239.       __IO uint16_t FIOSETH;

  240.     };

  241.     struct {

  242.       __IO uint8_t  FIOSET0;

  243.       __IO uint8_t  FIOSET1;

  244.       __IO uint8_t  FIOSET2;

  245.       __IO uint8_t  FIOSET3;

  246.     };

  247.   };

  248.   union {

  249.     __O  uint32_t FIOCLR;

  250.     struct {

  251.       __O  uint16_t FIOCLRL;

  252.       __O  uint16_t FIOCLRH;

  253.     };

  254.     struct {

  255.       __O  uint8_t  FIOCLR0;

  256.       __O  uint8_t  FIOCLR1;

  257.       __O  uint8_t  FIOCLR2;

  258.       __O  uint8_t  FIOCLR3;

  259.     };

  260.   };

  261. } LPC_GPIO_TypeDef;

  262. 

  263. /** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */

  264. typedef struct

  265. {

  266.   __I  uint32_t IntStatus;

  267.   __I  uint32_t IO0IntStatR;

  268.   __I  uint32_t IO0IntStatF;

  269.   __O  uint32_t IO0IntClr;

  270.   __IO uint32_t IO0IntEnR;

  271.   __IO uint32_t IO0IntEnF;

  272.        uint32_t RESERVED0[3];

  273.   __I  uint32_t IO2IntStatR;

  274.   __I  uint32_t IO2IntStatF;

  275.   __O  uint32_t IO2IntClr;

  276.   __IO uint32_t IO2IntEnR;

  277.   __IO uint32_t IO2IntEnF;

  278. } LPC_GPIOINT_TypeDef;

  279. 

  280. /*------------- Timer (TIM) --------------------------------------------------*/

  281. /** @brief Timer (TIM) register structure definition */

  282. typedef struct

  283. {

  284.   __IO uint32_t IR;

  285.   __IO uint32_t TCR;

  286.   __IO uint32_t TC;

  287.   __IO uint32_t PR;

  288.   __IO uint32_t PC;

  289.   __IO uint32_t MCR;

  290.   __IO uint32_t MR0;

  291.   __IO uint32_t MR1;

  292.   __IO uint32_t MR2;

  293.   __IO uint32_t MR3;

  294.   __IO uint32_t CCR;

  295.   __I  uint32_t CR0;

  296.   __I  uint32_t CR1;

  297.        uint32_t RESERVED0[2];

  298.   __IO uint32_t EMR;

  299.        uint32_t RESERVED1[12];

  300.   __IO uint32_t CTCR;

  301. } LPC_TIM_TypeDef;

  302. 

  303. /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/

  304. /** @brief Pulse-Width Modulation (PWM) register structure definition */

  305. typedef struct

  306. {

  307.   __IO uint32_t IR;

  308.   __IO uint32_t TCR;

  309.   __IO uint32_t TC;

  310.   __IO uint32_t PR;

  311.   __IO uint32_t PC;

  312.   __IO uint32_t MCR;

  313.   __IO uint32_t MR0;

  314.   __IO uint32_t MR1;

  315.   __IO uint32_t MR2;

  316.   __IO uint32_t MR3;

  317.   __IO uint32_t CCR;

  318.   __I  uint32_t CR0;

  319.   __I  uint32_t CR1;

  320.   __I  uint32_t CR2;

  321.   __I  uint32_t CR3;

  322.        uint32_t RESERVED0;

  323.   __IO uint32_t MR4;

  324.   __IO uint32_t MR5;

  325.   __IO uint32_t MR6;

  326.   __IO uint32_t PCR;

  327.   __IO uint32_t LER;

  328.        uint32_t RESERVED1[7];

  329.   __IO uint32_t CTCR;

  330. } LPC_PWM_TypeDef;

  331. 

  332. /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/

  333. /** @brief  Universal Asynchronous Receiver Transmitter (UART) register structure definition */

  334. typedef struct

  335. {

  336.   union {

  337.   __I  uint8_t  RBR;

  338.   __O  uint8_t  THR;

  339.   __IO uint8_t  DLL;

  340.        uint32_t RESERVED0;

  341.   };

  342.   union {

  343.   __IO uint8_t  DLM;

  344.   __IO uint32_t IER;

  345.   };

  346.   union {

  347.   __I  uint32_t IIR;

  348.   __O  uint8_t  FCR;

  349.   };

  350.   __IO uint8_t  LCR;

  351.        uint8_t  RESERVED1[7];

  352.   __I  uint8_t  LSR;

  353.        uint8_t  RESERVED2[7];

  354.   __IO uint8_t  SCR;

  355.        uint8_t  RESERVED3[3];

  356.   __IO uint32_t ACR;

  357.   __IO uint8_t  ICR;

  358.        uint8_t  RESERVED4[3];

  359.   __IO uint8_t  FDR;

  360.        uint8_t  RESERVED5[7];

  361.   __IO uint8_t  TER;

  362.        uint8_t  RESERVED6[39];

  363.   __I  uint8_t  FIFOLVL;

  364. } LPC_UART_TypeDef;

  365. 

  366. /** @brief  Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */

  367. typedef struct

  368. {

  369.   union {

  370.   __I  uint8_t  RBR;

  371.   __O  uint8_t  THR;

  372.   __IO uint8_t  DLL;

  373.        uint32_t RESERVED0;

  374.   };

  375.   union {

  376.   __IO uint8_t  DLM;

  377.   __IO uint32_t IER;

  378.   };

  379.   union {

  380.   __I  uint32_t IIR;

  381.   __O  uint8_t  FCR;

  382.   };

  383.   __IO uint8_t  LCR;

  384.        uint8_t  RESERVED1[7];

  385.   __I  uint8_t  LSR;

  386.        uint8_t  RESERVED2[7];

  387.   __IO uint8_t  SCR;

  388.        uint8_t  RESERVED3[3];

  389.   __IO uint32_t ACR;

  390.   __IO uint8_t  ICR;

  391.        uint8_t  RESERVED4[3];

  392.   __IO uint8_t  FDR;

  393.        uint8_t  RESERVED5[7];

  394.   __IO uint8_t  TER;

  395.        uint8_t  RESERVED6[39];

  396.   __I  uint8_t  FIFOLVL;

  397. } LPC_UART0_TypeDef;

  398. 

  399. /** @brief  Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */

  400. typedef struct

  401. {

  402.   union {

  403.   __I  uint8_t  RBR;

  404.   __O  uint8_t  THR;

  405.   __IO uint8_t  DLL;

  406.        uint32_t RESERVED0;

  407.   };

  408.   union {

  409.   __IO uint8_t  DLM;

  410.   __IO uint32_t IER;

  411.   };

  412.   union {

  413.   __I  uint32_t IIR;

  414.   __O  uint8_t  FCR;

  415.   };

  416.   __IO uint8_t  LCR;

  417.        uint8_t  RESERVED1[3];

  418.   __IO uint8_t  MCR;

  419.        uint8_t  RESERVED2[3];

  420.   __I  uint8_t  LSR;

  421.        uint8_t  RESERVED3[3];

  422.   __I  uint8_t  MSR;

  423.        uint8_t  RESERVED4[3];

  424.   __IO uint8_t  SCR;

  425.        uint8_t  RESERVED5[3];

  426.   __IO uint32_t ACR;

  427.        uint32_t RESERVED6;

  428.   __IO uint32_t FDR;

  429.        uint32_t RESERVED7;

  430.   __IO uint8_t  TER;

  431.        uint8_t  RESERVED8[27];

  432.   __IO uint8_t  RS485CTRL;

  433.        uint8_t  RESERVED9[3];

  434.   __IO uint8_t  ADRMATCH;

  435.        uint8_t  RESERVED10[3];

  436.   __IO uint8_t  RS485DLY;

  437.        uint8_t  RESERVED11[3];

  438.   __I  uint8_t  FIFOLVL;

  439. } LPC_UART1_TypeDef;

  440. 

  441. /*------------- Serial Peripheral Interface (SPI) ----------------------------*/

  442. /** @brief  Serial Peripheral Interface (SPI) register structure definition */

  443. typedef struct

  444. {

  445.   __IO uint32_t SPCR;

  446.   __I  uint32_t SPSR;

  447.   __IO uint32_t SPDR;

  448.   __IO uint32_t SPCCR;

  449.        uint32_t RESERVED0[3];

  450.   __IO uint32_t SPINT;

  451. } LPC_SPI_TypeDef;

  452. 

  453. /*------------- Synchronous Serial Communication (SSP) -----------------------*/

  454. /** @brief  Synchronous Serial Communication (SSP) register structure definition */

  455. typedef struct

  456. {

  457.   __IO uint32_t CR0;

  458.   __IO uint32_t CR1;

  459.   __IO uint32_t DR;

  460.   __I  uint32_t SR;

  461.   __IO uint32_t CPSR;

  462.   __IO uint32_t IMSC;

  463.   __IO uint32_t RIS;

  464.   __IO uint32_t MIS;

  465.   __IO uint32_t ICR;

  466.   __IO uint32_t DMACR;

  467. } LPC_SSP_TypeDef;

  468. 

  469. /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/

  470. /** @brief  Inter-Integrated Circuit (I2C) register structure definition */

  471. typedef struct

  472. {

  473.   __IO uint32_t I2CONSET;

  474.   __I  uint32_t I2STAT;

  475.   __IO uint32_t I2DAT;

  476.   __IO uint32_t I2ADR0;

  477.   __IO uint32_t I2SCLH;

  478.   __IO uint32_t I2SCLL;

  479.   __O  uint32_t I2CONCLR;

  480.   __IO uint32_t MMCTRL;

  481.   __IO uint32_t I2ADR1;

  482.   __IO uint32_t I2ADR2;

  483.   __IO uint32_t I2ADR3;

  484.   __I  uint32_t I2DATA_BUFFER;

  485.   __IO uint32_t I2MASK0;

  486.   __IO uint32_t I2MASK1;

  487.   __IO uint32_t I2MASK2;

  488.   __IO uint32_t I2MASK3;

  489. } LPC_I2C_TypeDef;

  490. 

  491. /*------------- Inter IC Sound (I2S) -----------------------------------------*/

  492. /** @brief  Inter IC Sound (I2S) register structure definition */

  493. typedef struct

  494. {

  495.   __IO uint32_t I2SDAO;

  496.   __IO uint32_t I2SDAI;

  497.   __O  uint32_t I2STXFIFO;

  498.   __I  uint32_t I2SRXFIFO;

  499.   __I  uint32_t I2SSTATE;

  500.   __IO uint32_t I2SDMA1;

  501.   __IO uint32_t I2SDMA2;

  502.   __IO uint32_t I2SIRQ;

  503.   __IO uint32_t I2STXRATE;

  504.   __IO uint32_t I2SRXRATE;

  505.   __IO uint32_t I2STXBITRATE;

  506.   __IO uint32_t I2SRXBITRATE;

  507.   __IO uint32_t I2STXMODE;

  508.   __IO uint32_t I2SRXMODE;

  509. } LPC_I2S_TypeDef;

  510. 

  511. /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/

  512. /** @brief  Repetitive Interrupt Timer (RIT) register structure definition */

  513. typedef struct

  514. {

  515.   __IO uint32_t RICOMPVAL;

  516.   __IO uint32_t RIMASK;

  517.   __IO uint8_t  RICTRL;

  518.        uint8_t  RESERVED0[3];

  519.   __IO uint32_t RICOUNTER;

  520. } LPC_RIT_TypeDef;

  521. 

  522. /*------------- Real-Time Clock (RTC) ----------------------------------------*/

  523. /** @brief  Real-Time Clock (RTC) register structure definition */

  524. typedef struct

  525. {

  526.   __IO uint8_t  ILR;

  527.        uint8_t  RESERVED0[7];

  528.   __IO uint8_t  CCR;

  529.        uint8_t  RESERVED1[3];

  530.   __IO uint8_t  CIIR;

  531.        uint8_t  RESERVED2[3];

  532.   __IO uint8_t  AMR;

  533.        uint8_t  RESERVED3[3];

  534.   __I  uint32_t CTIME0;

  535.   __I  uint32_t CTIME1;

  536.   __I  uint32_t CTIME2;

  537.   __IO uint8_t  SEC;

  538.        uint8_t  RESERVED4[3];

  539.   __IO uint8_t  MIN;

  540.        uint8_t  RESERVED5[3];

  541.   __IO uint8_t  HOUR;

  542.        uint8_t  RESERVED6[3];

  543.   __IO uint8_t  DOM;

  544.        uint8_t  RESERVED7[3];

  545.   __IO uint8_t  DOW;

  546.        uint8_t  RESERVED8[3];

  547.   __IO uint16_t DOY;

  548.        uint16_t RESERVED9;

  549.   __IO uint8_t  MONTH;

  550.        uint8_t  RESERVED10[3];

  551.   __IO uint16_t YEAR;

  552.        uint16_t RESERVED11;

  553.   __IO uint32_t CALIBRATION;

  554.   __IO uint32_t GPREG0;

  555.   __IO uint32_t GPREG1;

  556.   __IO uint32_t GPREG2;

  557.   __IO uint32_t GPREG3;

  558.   __IO uint32_t GPREG4;

  559.   __IO uint8_t  RTC_AUXEN;

  560.        uint8_t  RESERVED12[3];

  561.   __IO uint8_t  RTC_AUX;

  562.        uint8_t  RESERVED13[3];

  563.   __IO uint8_t  ALSEC;

  564.        uint8_t  RESERVED14[3];

  565.   __IO uint8_t  ALMIN;

  566.        uint8_t  RESERVED15[3];

  567.   __IO uint8_t  ALHOUR;

  568.        uint8_t  RESERVED16[3];

  569.   __IO uint8_t  ALDOM;

  570.        uint8_t  RESERVED17[3];

  571.   __IO uint8_t  ALDOW;

  572.        uint8_t  RESERVED18[3];

  573.   __IO uint16_t ALDOY;

  574.        uint16_t RESERVED19;

  575.   __IO uint8_t  ALMON;

  576.        uint8_t  RESERVED20[3];

  577.   __IO uint16_t ALYEAR;

  578.        uint16_t RESERVED21;

  579. } LPC_RTC_TypeDef;

  580. 

  581. /*------------- Watchdog Timer (WDT) -----------------------------------------*/

  582. /** @brief  Watchdog Timer (WDT) register structure definition */

  583. typedef struct

  584. {

  585.   __IO uint8_t  WDMOD;

  586.        uint8_t  RESERVED0[3];

  587.   __IO uint32_t WDTC;

  588.   __O  uint8_t  WDFEED;

  589.        uint8_t  RESERVED1[3];

  590.   __I  uint32_t WDTV;

  591.   __IO uint32_t WDCLKSEL;

  592. } LPC_WDT_TypeDef;

  593. 

  594. /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/

  595. /** @brief  Analog-to-Digital Converter (ADC) register structure definition */

  596. typedef struct

  597. {

  598.   __IO uint32_t ADCR;

  599.   __IO uint32_t ADGDR;

  600.        uint32_t RESERVED0;

  601.   __IO uint32_t ADINTEN;

  602.   __I  uint32_t ADDR0;

  603.   __I  uint32_t ADDR1;

  604.   __I  uint32_t ADDR2;

  605.   __I  uint32_t ADDR3;

  606.   __I  uint32_t ADDR4;

  607.   __I  uint32_t ADDR5;

  608.   __I  uint32_t ADDR6;

  609.   __I  uint32_t ADDR7;

  610.   __I  uint32_t ADSTAT;

  611.   __IO uint32_t ADTRM;

  612. } LPC_ADC_TypeDef;

  613. 

  614. /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/

  615. /** @brief  Digital-to-Analog Converter (DAC) register structure definition */

  616. typedef struct

  617. {

  618.   __IO uint32_t DACR;

  619.   __IO uint32_t DACCTRL;

  620.   __IO uint16_t DACCNTVAL;

  621. } LPC_DAC_TypeDef;

  622. 

  623. /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/

  624. /** @brief  Motor Control Pulse-Width Modulation (MCPWM) register structure definition */

  625. typedef struct

  626. {

  627.   __I  uint32_t MCCON;

  628.   __O  uint32_t MCCON_SET;

  629.   __O  uint32_t MCCON_CLR;

  630.   __I  uint32_t MCCAPCON;

  631.   __O  uint32_t MCCAPCON_SET;

  632.   __O  uint32_t MCCAPCON_CLR;

  633.   __IO uint32_t MCTIM0;

  634.   __IO uint32_t MCTIM1;

  635.   __IO uint32_t MCTIM2;

  636.   __IO uint32_t MCPER0;

  637.   __IO uint32_t MCPER1;

  638.   __IO uint32_t MCPER2;

  639.   __IO uint32_t MCPW0;

  640.   __IO uint32_t MCPW1;

  641.   __IO uint32_t MCPW2;

  642.   __IO uint32_t MCDEADTIME;

  643.   __IO uint32_t MCCCP;

  644.   __IO uint32_t MCCR0;

  645.   __IO uint32_t MCCR1;

  646.   __IO uint32_t MCCR2;

  647.   __I  uint32_t MCINTEN;

  648.   __O  uint32_t MCINTEN_SET;

  649.   __O  uint32_t MCINTEN_CLR;

  650.   __I  uint32_t MCCNTCON;

  651.   __O  uint32_t MCCNTCON_SET;

  652.   __O  uint32_t MCCNTCON_CLR;

  653.   __I  uint32_t MCINTFLAG;

  654.   __O  uint32_t MCINTFLAG_SET;

  655.   __O  uint32_t MCINTFLAG_CLR;

  656.   __O  uint32_t MCCAP_CLR;

  657. } LPC_MCPWM_TypeDef;

  658. 

  659. /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/

  660. /** @brief  Quadrature Encoder Interface (QEI) register structure definition */

  661. typedef struct

  662. {

  663.   __O  uint32_t QEICON;

  664.   __I  uint32_t QEISTAT;

  665.   __IO uint32_t QEICONF;

  666.   __I  uint32_t QEIPOS;

  667.   __IO uint32_t QEIMAXPOS;

  668.   __IO uint32_t CMPOS0;

  669.   __IO uint32_t CMPOS1;

  670.   __IO uint32_t CMPOS2;

  671.   __I  uint32_t INXCNT;

  672.   __IO uint32_t INXCMP;

  673.   __IO uint32_t QEILOAD;

  674.   __I  uint32_t QEITIME;

  675.   __I  uint32_t QEIVEL;

  676.   __I  uint32_t QEICAP;

  677.   __IO uint32_t VELCOMP;

  678.   __IO uint32_t FILTER;

  679.        uint32_t RESERVED0[998];

  680.   __O  uint32_t QEIIEC;

  681.   __O  uint32_t QEIIES;

  682.   __I  uint32_t QEIINTSTAT;

  683.   __I  uint32_t QEIIE;

  684.   __O  uint32_t QEICLR;

  685.   __O  uint32_t QEISET;

  686. } LPC_QEI_TypeDef;

  687. 

  688. /*------------- Controller Area Network (CAN) --------------------------------*/

  689. /** @brief  Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */

  690. typedef struct

  691. {

  692.   __IO uint32_t mask[512];              /* ID Masks                           */

  693. } LPC_CANAF_RAM_TypeDef;

  694. 

  695. /** @brief  Controller Area Network Acceptance Filter(CANAF) register structure definition */

  696. typedef struct                          /* Acceptance Filter Registers        */

  697. {

  698.   __IO uint32_t AFMR;

  699.   __IO uint32_t SFF_sa;

  700.   __IO uint32_t SFF_GRP_sa;

  701.   __IO uint32_t EFF_sa;

  702.   __IO uint32_t EFF_GRP_sa;

  703.   __IO uint32_t ENDofTable;

  704.   __I  uint32_t LUTerrAd;

  705.   __I  uint32_t LUTerr;

  706.   __IO uint32_t FCANIE;

  707.   __IO uint32_t FCANIC0;

  708.   __IO uint32_t FCANIC1;

  709. } LPC_CANAF_TypeDef;

  710. 

  711. /** @brief  Controller Area Network Central (CANCR) register structure definition */

  712. typedef struct                          /* Central Registers                  */

  713. {

  714.   __I  uint32_t CANTxSR;

  715.   __I  uint32_t CANRxSR;

  716.   __I  uint32_t CANMSR;

  717. } LPC_CANCR_TypeDef;

  718. 

  719. /** @brief  Controller Area Network Controller (CAN) register structure definition */

  720. typedef struct                          /* Controller Registers               */

  721. {

  722.   __IO uint32_t MOD;

  723.   __O  uint32_t CMR;

  724.   __IO uint32_t GSR;

  725.   __I  uint32_t ICR;

  726.   __IO uint32_t IER;

  727.   __IO uint32_t BTR;

  728.   __IO uint32_t EWL;

  729.   __I  uint32_t SR;

  730.   __IO uint32_t RFS;

  731.   __IO uint32_t RID;

  732.   __IO uint32_t RDA;

  733.   __IO uint32_t RDB;

  734.   __IO uint32_t TFI1;

  735.   __IO uint32_t TID1;

  736.   __IO uint32_t TDA1;

  737.   __IO uint32_t TDB1;

  738.   __IO uint32_t TFI2;

  739.   __IO uint32_t TID2;

  740.   __IO uint32_t TDA2;

  741.   __IO uint32_t TDB2;

  742.   __IO uint32_t TFI3;

  743.   __IO uint32_t TID3;

  744.   __IO uint32_t TDA3;

  745.   __IO uint32_t TDB3;

  746. } LPC_CAN_TypeDef;

  747. 

  748. /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/

  749. /** @brief  General Purpose Direct Memory Access (GPDMA) register structure definition */

  750. typedef struct                          /* Common Registers                   */

  751. {

  752.   __I  uint32_t DMACIntStat;

  753.   __I  uint32_t DMACIntTCStat;

  754.   __O  uint32_t DMACIntTCClear;

  755.   __I  uint32_t DMACIntErrStat;

  756.   __O  uint32_t DMACIntErrClr;

  757.   __I  uint32_t DMACRawIntTCStat;

  758.   __I  uint32_t DMACRawIntErrStat;

  759.   __I  uint32_t DMACEnbldChns;

  760.   __IO uint32_t DMACSoftBReq;

  761.   __IO uint32_t DMACSoftSReq;

  762.   __IO uint32_t DMACSoftLBReq;

  763.   __IO uint32_t DMACSoftLSReq;

  764.   __IO uint32_t DMACConfig;

  765.   __IO uint32_t DMACSync;

  766. } LPC_GPDMA_TypeDef;

  767. 

  768. /** @brief  General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */

  769. typedef struct                          /* Channel Registers                  */

  770. {

  771.   __IO uint32_t DMACCSrcAddr;

  772.   __IO uint32_t DMACCDestAddr;

  773.   __IO uint32_t DMACCLLI;

  774.   __IO uint32_t DMACCControl;

  775.   __IO uint32_t DMACCConfig;

  776. } LPC_GPDMACH_TypeDef;

  777. 

  778. /*------------- Universal Serial Bus (USB) -----------------------------------*/

  779. /** @brief  Universal Serial Bus (USB) register structure definition */

  780. typedef struct

  781. {

  782.   __I  uint32_t HcRevision;             /* USB Host Registers                 */

  783.   __IO uint32_t HcControl;

  784.   __IO uint32_t HcCommandStatus;

  785.   __IO uint32_t HcInterruptStatus;

  786.   __IO uint32_t HcInterruptEnable;

  787.   __IO uint32_t HcInterruptDisable;

  788.   __IO uint32_t HcHCCA;

  789.   __I  uint32_t HcPeriodCurrentED;

  790.   __IO uint32_t HcControlHeadED;

  791.   __IO uint32_t HcControlCurrentED;

  792.   __IO uint32_t HcBulkHeadED;

  793.   __IO uint32_t HcBulkCurrentED;

  794.   __I  uint32_t HcDoneHead;

  795.   __IO uint32_t HcFmInterval;

  796.   __I  uint32_t HcFmRemaining;

  797.   __I  uint32_t HcFmNumber;

  798.   __IO uint32_t HcPeriodicStart;

  799.   __IO uint32_t HcLSTreshold;

  800.   __IO uint32_t HcRhDescriptorA;

  801.   __IO uint32_t HcRhDescriptorB;

  802.   __IO uint32_t HcRhStatus;

  803.   __IO uint32_t HcRhPortStatus1;

  804.   __IO uint32_t HcRhPortStatus2;

  805.        uint32_t RESERVED0[40];

  806.   __I  uint32_t Module_ID;

  807. 

  808.   __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */

  809.   __IO uint32_t OTGIntEn;

  810.   __O  uint32_t OTGIntSet;

  811.   __O  uint32_t OTGIntClr;

  812.   __IO uint32_t OTGStCtrl;

  813.   __IO uint32_t OTGTmr;

  814.        uint32_t RESERVED1[58];

  815. 

  816.   __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */

  817.   __IO uint32_t USBDevIntEn;

  818.   __O  uint32_t USBDevIntClr;

  819.   __O  uint32_t USBDevIntSet;

  820. 

  821.   __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */

  822.   __I  uint32_t USBCmdData;

  823. 

  824.   __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */

  825.   __O  uint32_t USBTxData;

  826.   __I  uint32_t USBRxPLen;

  827.   __O  uint32_t USBTxPLen;

  828.   __IO uint32_t USBCtrl;

  829.   __O  uint32_t USBDevIntPri;

  830. 

  831.   __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */

  832.   __IO uint32_t USBEpIntEn;

  833.   __O  uint32_t USBEpIntClr;

  834.   __O  uint32_t USBEpIntSet;

  835.   __O  uint32_t USBEpIntPri;

  836. 

  837.   __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/

  838.   __O  uint32_t USBEpInd;

  839.   __IO uint32_t USBMaxPSize;

  840. 

  841.   __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */

  842.   __O  uint32_t USBDMARClr;

  843.   __O  uint32_t USBDMARSet;

  844.        uint32_t RESERVED2[9];

  845.   __IO uint32_t USBUDCAH;

  846.   __I  uint32_t USBEpDMASt;

  847.   __O  uint32_t USBEpDMAEn;

  848.   __O  uint32_t USBEpDMADis;

  849.   __I  uint32_t USBDMAIntSt;

  850.   __IO uint32_t USBDMAIntEn;

  851.        uint32_t RESERVED3[2];

  852.   __I  uint32_t USBEoTIntSt;

  853.   __O  uint32_t USBEoTIntClr;

  854.   __O  uint32_t USBEoTIntSet;

  855.   __I  uint32_t USBNDDRIntSt;

  856.   __O  uint32_t USBNDDRIntClr;

  857.   __O  uint32_t USBNDDRIntSet;

  858.   __I  uint32_t USBSysErrIntSt;

  859.   __O  uint32_t USBSysErrIntClr;

  860.   __O  uint32_t USBSysErrIntSet;

  861.        uint32_t RESERVED4[15];

  862. 

  863.   union {

  864.   __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */

  865.   __O  uint32_t I2C_TX;

  866.   };

  867.   __I  uint32_t I2C_STS;

  868.   __IO uint32_t I2C_CTL;

  869.   __IO uint32_t I2C_CLKHI;

  870.   __O  uint32_t I2C_CLKLO;

  871.        uint32_t RESERVED5[824];

  872. 

  873.   union {

  874.   __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */

  875.   __IO uint32_t OTGClkCtrl;

  876.   };

  877.   union {

  878.   __I  uint32_t USBClkSt;

  879.   __I  uint32_t OTGClkSt;

  880.   };

  881. } LPC_USB_TypeDef;

  882. 

  883. /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/

  884. /** @brief  Ethernet Media Access Controller (EMAC) register structure definition */

  885. typedef struct

  886. {

  887.   __IO uint32_t MAC1;                   /* MAC Registers                      */

  888.   __IO uint32_t MAC2;

  889.   __IO uint32_t IPGT;

  890.   __IO uint32_t IPGR;

  891.   __IO uint32_t CLRT;

  892.   __IO uint32_t MAXF;

  893.   __IO uint32_t SUPP;

  894.   __IO uint32_t TEST;

  895.   __IO uint32_t MCFG;

  896.   __IO uint32_t MCMD;

  897.   __IO uint32_t MADR;

  898.   __O  uint32_t MWTD;

  899.   __I  uint32_t MRDD;

  900.   __I  uint32_t MIND;

  901.        uint32_t RESERVED0[2];

  902.   __IO uint32_t SA0;

  903.   __IO uint32_t SA1;

  904.   __IO uint32_t SA2;

  905.        uint32_t RESERVED1[45];

  906.   __IO uint32_t Command;                /* Control Registers                  */

  907.   __I  uint32_t Status;

  908.   __IO uint32_t RxDescriptor;

  909.   __IO uint32_t RxStatus;

  910.   __IO uint32_t RxDescriptorNumber;

  911.   __I  uint32_t RxProduceIndex;

  912.   __IO uint32_t RxConsumeIndex;

  913.   __IO uint32_t TxDescriptor;

  914.   __IO uint32_t TxStatus;

  915.   __IO uint32_t TxDescriptorNumber;

  916.   __IO uint32_t TxProduceIndex;

  917.   __I  uint32_t TxConsumeIndex;

  918.        uint32_t RESERVED2[10];

  919.   __I  uint32_t TSV0;

  920.   __I  uint32_t TSV1;

  921.   __I  uint32_t RSV;

  922.        uint32_t RESERVED3[3];

  923.   __IO uint32_t FlowControlCounter;

  924.   __I  uint32_t FlowControlStatus;

  925.        uint32_t RESERVED4[34];

  926.   __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */

  927.   __IO uint32_t RxFilterWoLStatus;

  928.   __IO uint32_t RxFilterWoLClear;

  929.        uint32_t RESERVED5;

  930.   __IO uint32_t HashFilterL;

  931.   __IO uint32_t HashFilterH;

  932.        uint32_t RESERVED6[882];

  933.   __I  uint32_t IntStatus;              /* Module Control Registers           */

  934.   __IO uint32_t IntEnable;

  935.   __O  uint32_t IntClear;

  936.   __O  uint32_t IntSet;

  937.        uint32_t RESERVED7;

  938.   __IO uint32_t PowerDown;

  939.        uint32_t RESERVED8;

  940.   __IO uint32_t Module_ID;

  941. } LPC_EMAC_TypeDef;

  942. 

  943. 

  944. #if defined ( __CC_ARM   )

  945. #pragma no_anon_unions

  946. #endif

  947. 

  948. 

  949. /******************************************************************************/

  950. /*                         Peripheral memory map                              */

  951. /******************************************************************************/

  952. /* Base addresses                                                             */

  953. #define LPC_FLASH_BASE        (0x00000000UL)

  954. #define LPC_RAM_BASE          (0x10000000UL)

  955. #ifdef __LPC17XX_REV00

  956. #define LPC_AHBRAM0_BASE      (0x20000000UL)

  957. #define LPC_AHBRAM1_BASE      (0x20004000UL)

  958. #else

  959. #define LPC_AHBRAM0_BASE      (0x2007C000UL)

  960. #define LPC_AHBRAM1_BASE      (0x20080000UL)

  961. #endif

  962. #define LPC_GPIO_BASE         (0x2009C000UL)

  963. #define LPC_APB0_BASE         (0x40000000UL)

  964. #define LPC_APB1_BASE         (0x40080000UL)

  965. #define LPC_AHB_BASE          (0x50000000UL)

  966. #define LPC_CM3_BASE          (0xE0000000UL)

  967. 

  968. /* APB0 peripherals                                                           */

  969. #define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)

  970. #define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)

  971. #define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)

  972. #define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)

  973. #define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)

  974. #define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)

  975. #define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)

  976. #define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)

  977. #define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)

  978. #define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)

  979. #define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)

  980. #define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)

  981. #define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)

  982. #define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)

  983. #define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)

  984. #define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)

  985. #define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)

  986. #define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)

  987. #define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)

  988. 

  989. /* APB1 peripherals                                                           */

  990. #define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)

  991. #define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)

  992. #define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)

  993. #define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)

  994. #define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)

  995. #define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)

  996. #define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)

  997. #define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)

  998. #define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)

  999. #define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)

  1000. #define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)

  1001. #define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)

  1002. 

  1003. /* AHB peripherals                                                            */

  1004. #define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)

  1005. #define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)

  1006. #define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)

  1007. #define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)

  1008. #define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)

  1009. #define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)

  1010. #define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)

  1011. #define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)

  1012. #define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)

  1013. #define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)

  1014. #define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)

  1015. 

  1016. /* GPIOs                                                                      */

  1017. #define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)

  1018. #define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)

  1019. #define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)

  1020. #define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)

  1021. #define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)

  1022. 

  1023. /******************************************************************************/

  1024. /*                         Peripheral declaration                             */

  1025. /******************************************************************************/

  1026. #define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )

  1027. #define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )

  1028. #define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )

  1029. #define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )

  1030. #define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )

  1031. #define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )

  1032. #define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )

  1033. #define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )

  1034. #define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )

  1035. #define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )

  1036. #define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )

  1037. #define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )

  1038. #define LPC_UART0             ((LPC_UART_TypeDef      *) LPC_UART0_BASE    )

  1039. #define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )

  1040. #define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )

  1041. #define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )

  1042. #define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )

  1043. #define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )

  1044. #define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )

  1045. #define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )

  1046. #define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )

  1047. #define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )

  1048. #define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )

  1049. #define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )

  1050. #define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )

  1051. #define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )

  1052. #define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )

  1053. #define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )

  1054. #define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )

  1055. #define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)

  1056. #define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )

  1057. #define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )

  1058. #define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )

  1059. #define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )

  1060. #define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )

  1061. #define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )

  1062. #define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )

  1063. #define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )

  1064. #define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )

  1065. #define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )

  1066. #define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )

  1067. #define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )

  1068. #define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )

  1069. #define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )

  1070. #define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )

  1071. #define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )

  1072. #define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )

  1073. 

  1074. /**

  1075.  * @}

  1076.  */

  1077. 

  1078. #endif  // __LPC17xx_H__