Browse Source

Can now compile for AVR or ARM mbed

Thomas Buck 8 years ago
parent
commit
1e061e9725
100 changed files with 31525 additions and 53 deletions
  1. 34
    0
      include/arm/spi.h
  2. 0
    0
      include/avr/serial_device.h
  3. 64
    0
      include/avr/spi.h
  4. 12
    2
      include/main.h
  5. 10
    0
      include/serial.h
  6. 3
    51
      include/spi.h
  7. 17
    0
      include/timer.h
  8. 0
    0
      lib/mbed/.hg/keep.me
  9. 103
    0
      lib/mbed/AnalogIn.h
  10. 121
    0
      lib/mbed/AnalogOut.h
  11. 98
    0
      lib/mbed/BusIn.h
  12. 117
    0
      lib/mbed/BusInOut.h
  13. 101
    0
      lib/mbed/BusOut.h
  14. 243
    0
      lib/mbed/CAN.h
  15. 202
    0
      lib/mbed/CThunk.h
  16. 181
    0
      lib/mbed/CallChain.h
  17. 98
    0
      lib/mbed/CircularBuffer.h
  18. 107
    0
      lib/mbed/DigitalIn.h
  19. 124
    0
      lib/mbed/DigitalInOut.h
  20. 116
    0
      lib/mbed/DigitalOut.h
  21. 104
    0
      lib/mbed/DirHandle.h
  22. 170
    0
      lib/mbed/Ethernet.h
  23. 80
    0
      lib/mbed/FileBase.h
  24. 119
    0
      lib/mbed/FileHandle.h
  25. 44
    0
      lib/mbed/FileLike.h
  26. 46
    0
      lib/mbed/FilePath.h
  27. 104
    0
      lib/mbed/FileSystemLike.h
  28. 202
    0
      lib/mbed/FunctionPointer.h
  29. 176
    0
      lib/mbed/I2C.h
  30. 154
    0
      lib/mbed/I2CSlave.h
  31. 135
    0
      lib/mbed/InterruptIn.h
  32. 143
    0
      lib/mbed/InterruptManager.h
  33. 103
    0
      lib/mbed/LocalFileSystem.h
  34. 44
    0
      lib/mbed/LowPowerTicker.h
  35. 42
    0
      lib/mbed/LowPowerTimeout.h
  36. 42
    0
      lib/mbed/LowPowerTimer.h
  37. 93
    0
      lib/mbed/PortIn.h
  38. 104
    0
      lib/mbed/PortInOut.h
  39. 104
    0
      lib/mbed/PortOut.h
  40. 158
    0
      lib/mbed/PwmOut.h
  41. 90
    0
      lib/mbed/RawSerial.h
  42. 245
    0
      lib/mbed/SPI.h
  43. 122
    0
      lib/mbed/SPISlave.h
  44. 74
    0
      lib/mbed/Serial.h
  45. 223
    0
      lib/mbed/SerialBase.h
  46. 68
    0
      lib/mbed/Stream.h
  47. 1035
    0
      lib/mbed/TARGET_LPC1768/LPC17xx.h
  48. 111
    0
      lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PeripheralNames.h
  49. 34
    0
      lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PortNames.h
  50. 139
    0
      lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h
  51. 60
    0
      lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/device.h
  52. 8
    0
      lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/reserved_pins.h
  53. 56
    0
      lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/gpio_object.h
  54. 78
    0
      lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/objects.h
  55. 172
    0
      lib/mbed/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/LPC1768.ld
  56. BIN
      lib/mbed/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/libmbed.a
  57. 136
    0
      lib/mbed/TARGET_LPC1768/arm_common_tables.h
  58. 79
    0
      lib/mbed/TARGET_LPC1768/arm_const_structs.h
  59. 7556
    0
      lib/mbed/TARGET_LPC1768/arm_math.h
  60. 13
    0
      lib/mbed/TARGET_LPC1768/cmsis.h
  61. 51
    0
      lib/mbed/TARGET_LPC1768/cmsis_nvic.h
  62. 276
    0
      lib/mbed/TARGET_LPC1768/core_ca9.h
  63. 1418
    0
      lib/mbed/TARGET_LPC1768/core_caFunc.h
  64. 45
    0
      lib/mbed/TARGET_LPC1768/core_caInstr.h
  65. 847
    0
      lib/mbed/TARGET_LPC1768/core_ca_mmu.h
  66. 740
    0
      lib/mbed/TARGET_LPC1768/core_cm0.h
  67. 854
    0
      lib/mbed/TARGET_LPC1768/core_cm0plus.h
  68. 1693
    0
      lib/mbed/TARGET_LPC1768/core_cm3.h
  69. 1858
    0
      lib/mbed/TARGET_LPC1768/core_cm4.h
  70. 673
    0
      lib/mbed/TARGET_LPC1768/core_cm4_simd.h
  71. 2397
    0
      lib/mbed/TARGET_LPC1768/core_cm7.h
  72. 664
    0
      lib/mbed/TARGET_LPC1768/core_cmFunc.h
  73. 916
    0
      lib/mbed/TARGET_LPC1768/core_cmInstr.h
  74. 697
    0
      lib/mbed/TARGET_LPC1768/core_cmSimd.h
  75. 864
    0
      lib/mbed/TARGET_LPC1768/core_sc000.h
  76. 1675
    0
      lib/mbed/TARGET_LPC1768/core_sc300.h
  77. 60
    0
      lib/mbed/TARGET_LPC1768/system_LPC17xx.h
  78. 127
    0
      lib/mbed/Ticker.h
  79. 59
    0
      lib/mbed/Timeout.h
  80. 91
    0
      lib/mbed/Timer.h
  81. 56
    0
      lib/mbed/TimerEvent.h
  82. 73
    0
      lib/mbed/Transaction.h
  83. 39
    0
      lib/mbed/analogin_api.h
  84. 42
    0
      lib/mbed/analogout_api.h
  85. 30
    0
      lib/mbed/buffer.h
  86. 80
    0
      lib/mbed/can_api.h
  87. 53
    0
      lib/mbed/can_helper.h
  88. 45
    0
      lib/mbed/dma_api.h
  89. 63
    0
      lib/mbed/ethernet_api.h
  90. 57
    0
      lib/mbed/gpio_api.h
  91. 49
    0
      lib/mbed/gpio_irq_api.h
  92. 224
    0
      lib/mbed/i2c_api.h
  93. 82
    0
      lib/mbed/lp_ticker_api.h
  94. 70
    0
      lib/mbed/mbed.h
  95. 49
    0
      lib/mbed/mbed_assert.h
  96. 66
    0
      lib/mbed/mbed_debug.h
  97. 66
    0
      lib/mbed/mbed_error.h
  98. 114
    0
      lib/mbed/mbed_interface.h
  99. 45
    0
      lib/mbed/pinmap.h
  100. 0
    0
      lib/mbed/platform.h

+ 34
- 0
include/arm/spi.h View File

@@ -0,0 +1,34 @@
1
+/*
2
+ * Bit-Banged SPI routines
3
+ */
4
+
5
+#ifndef _ARM_SPI_H
6
+#define _ARM_SPI_H
7
+
8
+// TODO obviously
9
+
10
+#define SCK_on
11
+#define SCK_off
12
+#define SCK_dir
13
+
14
+#define MO_on
15
+#define MO_off
16
+#define MO_dir
17
+
18
+#define CS_on
19
+#define CS_off
20
+#define CS_dir
21
+
22
+#define MI_1 1
23
+#define MI_0 0
24
+#define MI_dir
25
+
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+#define GDO_1 1
27
+#define GDO_0 0
28
+#define GDO_dir
29
+
30
+// TODO delay 62.5ns!!
31
+#define NOP()
32
+
33
+#endif
34
+

include/serial_device.h → include/avr/serial_device.h View File


+ 64
- 0
include/avr/spi.h View File

@@ -0,0 +1,64 @@
1
+/*
2
+ * Bit-Banged SPI routines
3
+ */
4
+
5
+#ifndef _AVR_SPI_H
6
+#define _AVR_SPI_H
7
+
8
+#include <avr/io.h>
9
+
10
+#ifdef DEBUG
11
+
12
+// Arduino D3 = PD3
13
+#define SCK_on PORTD |= (1 << PD3)
14
+#define SCK_off PORTD &= ~(1 << PD3)
15
+#define SCK_dir DDRD |= (1 << PD3)
16
+
17
+// Arduino D7 = PD7
18
+#define MO_on PORTD |= (1 << PD7)
19
+#define MO_off PORTD &= ~(1 << PD7)
20
+#define MO_dir DDRD |= (1 << PD7)
21
+
22
+// Arduino D8 = PB0
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+#define CS_on PORTB |= (1 << PB0)
24
+#define CS_off PORTB &= ~(1 << PB0)
25
+#define CS_dir DDRB |= (1 << PB0)
26
+
27
+// Arduino D2 = PD2
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+#define MI_1 (PIND & (1 << PD2)) != 0
29
+#define MI_0 (PIND & (1 << PD2)) == 0
30
+#define MI_dir DDRD &= ~(1 << PD2); PORTD |= (1 << PD2)
31
+
32
+// Arduino D9 = PB1
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+#define GDO_1 (PINB & (1 << PB1)) != 0
34
+#define GDO_0 (PINB & (1 << PB1)) == 0
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+#define GDO_dir DDRB &= ~(1 << PB1); PORTB |= (1 << PB1)
36
+
37
+#else
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+
39
+#define SCK_on PORTB |= (1 << PB4)
40
+#define SCK_off PORTB &= ~(1 << PB4)
41
+#define SCK_dir DDRB |= (1 << PB4)
42
+
43
+#define MO_on PORTB |= (1 << PB2)
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+#define MO_off PORTB &= ~(1 << PB2)
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+#define MO_dir DDRB |= (1 << PB2)
46
+
47
+#define CS_on PORTB |= (1 << PB1)
48
+#define CS_off PORTB &= ~(1 << PB1)
49
+#define CS_dir DDRB |= (1 << PB1)
50
+
51
+#define MI_1 (PINB & (1 << PB3)) != 0
52
+#define MI_0 (PINB & (1 << PB3)) == 0
53
+#define MI_dir DDRB &= ~(1 << PB3); PORTB |= (1 << PB3)
54
+
55
+#define GDO_1 (PINB & (1 << PB0)) != 0
56
+#define GDO_0 (PINB & (1 << PB0)) == 0
57
+#define GDO_dir DDRB &= ~(1 << PB0); PORTB |= (1 << PB0)
58
+
59
+#endif
60
+
61
+#define NOP() __asm__ __volatile__("nop")
62
+
63
+#endif
64
+

+ 12
- 2
include/main.h View File

@@ -11,8 +11,13 @@
11 11
 
12 12
 //#define DEBUG_UART_MENU
13 13
 
14
-#define debugWrite(x) serialWriteString(0, x);
15
-#define debugHex(x) serialWriteHex(0, x);
14
+#define debugChar(x) serialWrite(0, x)
15
+#define debugWrite(x) serialWriteString(0, x)
16
+#define debugHex(x) serialWriteHex(0, x)
17
+#define debugUnsigned8(x) serialWriteUnsigned8(0, x)
18
+#define debugUnsigned16(x) serialWriteUnsigned16(0, x)
19
+#define debugUnsigned32(x) serialWriteUnsigned32(0, x)
20
+#define debugUnsigned64(x) serialWriteUnsigned64(0, x)
16 21
 
17 22
 #ifdef DEBUG_UART_MENU
18 23
 void uartMenu(void);
@@ -20,8 +25,13 @@ void uartMenu(void);
20 25
 
21 26
 #else // DEBUG
22 27
 
28
+#define debugChar(x)
23 29
 #define debugWrite(x)
24 30
 #define debugHex(x)
31
+#define debugUnsigned8(x)
32
+#define debugUnsigned16(x)
33
+#define debugUnsigned32(x)
34
+#define debugUnsigned64(x)
25 35
 
26 36
 #endif // DEBUG
27 37
 

+ 10
- 0
include/serial.h View File

@@ -30,6 +30,8 @@
30 30
 #ifndef _serial_h
31 31
 #define _serial_h
32 32
 
33
+#include <stdint.h>
34
+
33 35
 /** \addtogroup uart UART Library
34 36
  *  UART Library enabling you to control all available
35 37
  *  UART Modules. With XON/XOFF Flow Control and buffered
@@ -41,9 +43,17 @@
41 43
  *  UART Library Header File
42 44
  */
43 45
 
46
+#if defined(__AVR__)
47
+
44 48
 /** Calculate Baudrate Register Value */
45 49
 #define BAUD(baudRate,xtalCpu) ((xtalCpu)/((baudRate)*16l)-1)
46 50
 
51
+#else
52
+
53
+#define BAUD(baudRate,xtalCpu) (baudRate)
54
+
55
+#endif
56
+
47 57
 /** Get number of available UART modules.
48 58
  *  \returns number of modules
49 59
  */

+ 3
- 51
include/spi.h View File

@@ -6,61 +6,13 @@
6 6
 #define _SPI_H
7 7
 
8 8
 #include <stdint.h>
9
-#include <avr/io.h>
10
-
11
-#ifdef DEBUG
12
-
13
-// Arduino D3 = PD3
14
-#define SCK_on PORTD |= (1 << PD3)
15
-#define SCK_off PORTD &= ~(1 << PD3)
16
-#define SCK_dir DDRD |= (1 << PD3)
17
-
18
-// Arduino D7 = PD7
19
-#define MO_on PORTD |= (1 << PD7)
20
-#define MO_off PORTD &= ~(1 << PD7)
21
-#define MO_dir DDRD |= (1 << PD7)
22
-
23
-// Arduino D8 = PB0
24
-#define CS_on PORTB |= (1 << PB0)
25
-#define CS_off PORTB &= ~(1 << PB0)
26
-#define CS_dir DDRB |= (1 << PB0)
27
-
28
-// Arduino D2 = PD2
29
-#define MI_1 (PIND & (1 << PD2)) != 0
30
-#define MI_0 (PIND & (1 << PD2)) == 0
31
-#define MI_dir DDRD &= ~(1 << PD2); PORTD |= (1 << PD2)
32
-
33
-// Arduino D9 = PB1
34
-#define GDO_1 (PINB & (1 << PB1)) != 0
35
-#define GDO_0 (PINB & (1 << PB1)) == 0
36
-#define GDO_dir DDRB &= ~(1 << PB1); PORTB |= (1 << PB1)
37 9
 
10
+#if defined(__AVR__)
11
+#include "avr/spi.h"
38 12
 #else
39
-
40
-#define SCK_on PORTB |= (1 << PB4)
41
-#define SCK_off PORTB &= ~(1 << PB4)
42
-#define SCK_dir DDRB |= (1 << PB4)
43
-
44
-#define MO_on PORTB |= (1 << PB2)
45
-#define MO_off PORTB &= ~(1 << PB2)
46
-#define MO_dir DDRB |= (1 << PB2)
47
-
48
-#define CS_on PORTB |= (1 << PB1)
49
-#define CS_off PORTB &= ~(1 << PB1)
50
-#define CS_dir DDRB |= (1 << PB1)
51
-
52
-#define MI_1 (PINB & (1 << PB3)) != 0
53
-#define MI_0 (PINB & (1 << PB3)) == 0
54
-#define MI_dir DDRB &= ~(1 << PB3); PORTB |= (1 << PB3)
55
-
56
-#define GDO_1 (PINB & (1 << PB0)) != 0
57
-#define GDO_0 (PINB & (1 << PB0)) == 0
58
-#define GDO_dir DDRB &= ~(1 << PB0); PORTB |= (1 << PB0)
59
-
13
+#include "arm/spi.h"
60 14
 #endif
61 15
 
62
-#define NOP() __asm__ __volatile__("nop")
63
-
64 16
 void spiInit(void);
65 17
 uint8_t spiReadWrite(uint8_t command);
66 18
 

+ 17
- 0
include/timer.h View File

@@ -5,6 +5,23 @@
5 5
 #ifndef _TIMER_H
6 6
 #define _TIMER_H
7 7
 
8
+#include <stdint.h>
9
+
10
+#ifdef __AVR__
11
+
12
+#include <util/delay.h>
13
+
14
+#define delay_us(x) _delay_us(x)
15
+#define delay_ms(x) _delay_ms(x)
16
+
17
+#else
18
+
19
+// TODO!!!
20
+#define delay_us(x)
21
+#define delay_ms(x)
22
+
23
+#endif
24
+
8 25
 typedef uint64_t time_t;
9 26
 
10 27
 void timerInit(void);

+ 0
- 0
lib/mbed/.hg/keep.me View File


+ 103
- 0
lib/mbed/AnalogIn.h View File

@@ -0,0 +1,103 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ANALOGIN_H
17
+#define MBED_ANALOGIN_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_ANALOGIN
22
+
23
+#include "analogin_api.h"
24
+
25
+namespace mbed {
26
+
27
+/** An analog input, used for reading the voltage on a pin
28
+ *
29
+ * Example:
30
+ * @code
31
+ * // Print messages when the AnalogIn is greater than 50%
32
+ *
33
+ * #include "mbed.h"
34
+ *
35
+ * AnalogIn temperature(p20);
36
+ *
37
+ * int main() {
38
+ *     while(1) {
39
+ *         if(temperature > 0.5) {
40
+ *             printf("Too hot! (%f)", temperature.read());
41
+ *         }
42
+ *     }
43
+ * }
44
+ * @endcode
45
+ */
46
+class AnalogIn {
47
+
48
+public:
49
+
50
+    /** Create an AnalogIn, connected to the specified pin
51
+     *
52
+     * @param pin AnalogIn pin to connect to
53
+     * @param name (optional) A string to identify the object
54
+     */
55
+    AnalogIn(PinName pin) {
56
+        analogin_init(&_adc, pin);
57
+    }
58
+
59
+    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
60
+     *
61
+     * @returns A floating-point value representing the current input voltage, measured as a percentage
62
+     */
63
+    float read() {
64
+        return analogin_read(&_adc);
65
+    }
66
+
67
+    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
68
+     *
69
+     * @returns
70
+     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
71
+     */
72
+    unsigned short read_u16() {
73
+        return analogin_read_u16(&_adc);
74
+    }
75
+
76
+#ifdef MBED_OPERATORS
77
+    /** An operator shorthand for read()
78
+     *
79
+     * The float() operator can be used as a shorthand for read() to simplify common code sequences
80
+     *
81
+     * Example:
82
+     * @code
83
+     * float x = volume.read();
84
+     * float x = volume;
85
+     *
86
+     * if(volume.read() > 0.25) { ... }
87
+     * if(volume > 0.25) { ... }
88
+     * @endcode
89
+     */
90
+    operator float() {
91
+        return read();
92
+    }
93
+#endif
94
+
95
+protected:
96
+    analogin_t _adc;
97
+};
98
+
99
+} // namespace mbed
100
+
101
+#endif
102
+
103
+#endif

+ 121
- 0
lib/mbed/AnalogOut.h View File

@@ -0,0 +1,121 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ANALOGOUT_H
17
+#define MBED_ANALOGOUT_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_ANALOGOUT
22
+
23
+#include "analogout_api.h"
24
+
25
+namespace mbed {
26
+
27
+/** An analog output, used for setting the voltage on a pin
28
+ *
29
+ * Example:
30
+ * @code
31
+ * // Make a sawtooth output
32
+ *
33
+ * #include "mbed.h"
34
+ *
35
+ * AnalogOut tri(p18);
36
+ * int main() {
37
+ *     while(1) {
38
+ *         tri = tri + 0.01;
39
+ *         wait_us(1);
40
+ *         if(tri == 1) {
41
+ *             tri = 0;
42
+ *         }
43
+ *     }
44
+ * }
45
+ * @endcode
46
+ */
47
+class AnalogOut {
48
+
49
+public:
50
+
51
+    /** Create an AnalogOut connected to the specified pin
52
+     *
53
+     *  @param AnalogOut pin to connect to (18)
54
+     */
55
+    AnalogOut(PinName pin) {
56
+        analogout_init(&_dac, pin);
57
+    }
58
+
59
+    /** Set the output voltage, specified as a percentage (float)
60
+     *
61
+     *  @param value A floating-point value representing the output voltage,
62
+     *    specified as a percentage. The value should lie between
63
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
64
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
65
+     */
66
+    void write(float value) {
67
+        analogout_write(&_dac, value);
68
+    }
69
+
70
+    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
71
+     *
72
+     *  @param value 16-bit unsigned short representing the output voltage,
73
+     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
74
+     */
75
+    void write_u16(unsigned short value) {
76
+        analogout_write_u16(&_dac, value);
77
+    }
78
+
79
+    /** Return the current output voltage setting, measured as a percentage (float)
80
+     *
81
+     *  @returns
82
+     *    A floating-point value representing the current voltage being output on the pin,
83
+     *    measured as a percentage. The returned value will lie between
84
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
85
+     *
86
+     *  @note
87
+     *    This value may not match exactly the value set by a previous write().
88
+     */
89
+    float read() {
90
+        return analogout_read(&_dac);
91
+    }
92
+
93
+#ifdef MBED_OPERATORS
94
+    /** An operator shorthand for write()
95
+     */
96
+    AnalogOut& operator= (float percent) {
97
+        write(percent);
98
+        return *this;
99
+    }
100
+
101
+    AnalogOut& operator= (AnalogOut& rhs) {
102
+        write(rhs.read());
103
+        return *this;
104
+    }
105
+
106
+    /** An operator shorthand for read()
107
+     */
108
+    operator float() {
109
+        return read();
110
+    }
111
+#endif
112
+
113
+protected:
114
+    dac_t _dac;
115
+};
116
+
117
+} // namespace mbed
118
+
119
+#endif
120
+
121
+#endif

+ 98
- 0
lib/mbed/BusIn.h View File

@@ -0,0 +1,98 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_BUSIN_H
17
+#define MBED_BUSIN_H
18
+
19
+#include "platform.h"
20
+#include "DigitalIn.h"
21
+
22
+namespace mbed {
23
+
24
+/** A digital input bus, used for reading the state of a collection of pins
25
+ */
26
+class BusIn {
27
+
28
+public:
29
+    /* Group: Configuration Methods */
30
+
31
+    /** Create an BusIn, connected to the specified pins
32
+     *
33
+     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
34
+     *
35
+     * @note
36
+     *  It is only required to specify as many pin variables as is required
37
+     *  for the bus; the rest will default to NC (not connected)
38
+     */
39
+    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
40
+          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
41
+          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
42
+          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
43
+
44
+    BusIn(PinName pins[16]);
45
+
46
+    virtual ~BusIn();
47
+
48
+    /** Read the value of the input bus
49
+     *
50
+     *  @returns
51
+     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
52
+     */
53
+    int read();
54
+
55
+    /** Set the input pin mode
56
+     *
57
+     *  @param mode PullUp, PullDown, PullNone
58
+     */
59
+    void mode(PinMode pull);
60
+
61
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
62
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
63
+     *
64
+     *  @returns
65
+     *    Binary mask of connected pins
66
+     */
67
+    int mask() {
68
+        return _nc_mask;
69
+    }
70
+
71
+#ifdef MBED_OPERATORS
72
+    /** A shorthand for read()
73
+     */
74
+    operator int();
75
+
76
+    /** Access to particular bit in random-iterator fashion
77
+     */
78
+    DigitalIn & operator[] (int index);
79
+#endif
80
+
81
+protected:
82
+    DigitalIn* _pin[16];
83
+
84
+    /** Mask of bus's NC pins
85
+     * If bit[n] is set to 1 - pin is connected
86
+     * if bit[n] is cleared - pin is not connected (NC)
87
+     */
88
+    int _nc_mask;
89
+
90
+    /* disallow copy constructor and assignment operators */
91
+private:
92
+    BusIn(const BusIn&);
93
+    BusIn & operator = (const BusIn&);
94
+};
95
+
96
+} // namespace mbed
97
+
98
+#endif

+ 117
- 0
lib/mbed/BusInOut.h View File

@@ -0,0 +1,117 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_BUSINOUT_H
17
+#define MBED_BUSINOUT_H
18
+
19
+#include "DigitalInOut.h"
20
+
21
+namespace mbed {
22
+
23
+/** A digital input output bus, used for setting the state of a collection of pins
24
+ */
25
+class BusInOut {
26
+
27
+public:
28
+
29
+    /** Create an BusInOut, connected to the specified pins
30
+     *
31
+     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
32
+     *
33
+     *  @note
34
+     *  It is only required to specify as many pin variables as is required
35
+     *  for the bus; the rest will default to NC (not connected)
36
+     */
37
+    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
38
+             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
39
+             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
40
+             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
41
+
42
+    BusInOut(PinName pins[16]);
43
+
44
+    virtual ~BusInOut();
45
+
46
+    /* Group: Access Methods */
47
+
48
+    /** Write the value to the output bus
49
+     *
50
+     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
51
+     */
52
+    void write(int value);
53
+
54
+    /** Read the value currently output on the bus
55
+     *
56
+     *  @returns
57
+     *    An integer with each bit corresponding to associated DigitalInOut pin setting
58
+     */
59
+    int read();
60
+
61
+    /** Set as an output
62
+     */
63
+    void output();
64
+
65
+    /** Set as an input
66
+     */
67
+    void input();
68
+
69
+    /** Set the input pin mode
70
+     *
71
+     *  @param mode PullUp, PullDown, PullNone
72
+     */
73
+    void mode(PinMode pull);
74
+
75
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
76
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
77
+     *
78
+     *  @returns
79
+     *    Binary mask of connected pins
80
+     */
81
+    int mask() {
82
+        return _nc_mask;
83
+    }
84
+
85
+#ifdef MBED_OPERATORS
86
+     /** A shorthand for write()
87
+     */
88
+    BusInOut& operator= (int v);
89
+    BusInOut& operator= (BusInOut& rhs);
90
+
91
+    /** Access to particular bit in random-iterator fashion
92
+    */
93
+    DigitalInOut& operator[] (int index);
94
+
95
+    /** A shorthand for read()
96
+     */
97
+    operator int();
98
+#endif
99
+
100
+protected:
101
+    DigitalInOut* _pin[16];
102
+
103
+    /** Mask of bus's NC pins
104
+     * If bit[n] is set to 1 - pin is connected
105
+     * if bit[n] is cleared - pin is not connected (NC)
106
+     */
107
+    int _nc_mask;
108
+
109
+    /* disallow copy constructor and assignment operators */
110
+private:
111
+    BusInOut(const BusInOut&);
112
+    BusInOut & operator = (const BusInOut&);
113
+};
114
+
115
+} // namespace mbed
116
+
117
+#endif

+ 101
- 0
lib/mbed/BusOut.h View File

@@ -0,0 +1,101 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_BUSOUT_H
17
+#define MBED_BUSOUT_H
18
+
19
+#include "DigitalOut.h"
20
+
21
+namespace mbed {
22
+
23
+/** A digital output bus, used for setting the state of a collection of pins
24
+ */
25
+class BusOut {
26
+
27
+public:
28
+
29
+    /** Create an BusOut, connected to the specified pins
30
+     *
31
+     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
32
+     *
33
+     *  @note
34
+     *  It is only required to specify as many pin variables as is required
35
+     *  for the bus; the rest will default to NC (not connected)
36
+     */
37
+    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
38
+           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
39
+           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
40
+           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
41
+
42
+    BusOut(PinName pins[16]);
43
+
44
+    virtual ~BusOut();
45
+
46
+    /** Write the value to the output bus
47
+     *
48
+     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
49
+     */
50
+    void write(int value);
51
+
52
+    /** Read the value currently output on the bus
53
+     *
54
+     *  @returns
55
+     *    An integer with each bit corresponding to associated DigitalOut pin setting
56
+     */
57
+    int read();
58
+
59
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
60
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
61
+     *
62
+     *  @returns
63
+     *    Binary mask of connected pins
64
+     */
65
+    int mask() {
66
+        return _nc_mask;
67
+    }
68
+
69
+#ifdef MBED_OPERATORS
70
+    /** A shorthand for write()
71
+     */
72
+    BusOut& operator= (int v);
73
+    BusOut& operator= (BusOut& rhs);
74
+
75
+    /** Access to particular bit in random-iterator fashion
76
+     */
77
+    DigitalOut& operator[] (int index);
78
+
79
+    /** A shorthand for read()
80
+     */
81
+    operator int();
82
+#endif
83
+
84
+protected:
85
+    DigitalOut* _pin[16];
86
+
87
+    /** Mask of bus's NC pins
88
+     * If bit[n] is set to 1 - pin is connected
89
+     * if bit[n] is cleared - pin is not connected (NC)
90
+     */
91
+    int _nc_mask;
92
+
93
+   /* disallow copy constructor and assignment operators */
94
+private:
95
+    BusOut(const BusOut&);
96
+    BusOut & operator = (const BusOut&);
97
+};
98
+
99
+} // namespace mbed
100
+
101
+#endif

+ 243
- 0
lib/mbed/CAN.h View File

@@ -0,0 +1,243 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_CAN_H
17
+#define MBED_CAN_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_CAN
22
+
23
+#include "can_api.h"
24
+#include "can_helper.h"
25
+#include "FunctionPointer.h"
26
+
27
+namespace mbed {
28
+
29
+/** CANMessage class
30
+ */
31
+class CANMessage : public CAN_Message {
32
+
33
+public:
34
+    /** Creates empty CAN message.
35
+     */
36
+    CANMessage() : CAN_Message() {
37
+        len    = 8;
38
+        type   = CANData;
39
+        format = CANStandard;
40
+        id     = 0;
41
+        memset(data, 0, 8);
42
+    }
43
+
44
+    /** Creates CAN message with specific content.
45
+     */
46
+    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
47
+      len    = _len & 0xF;
48
+      type   = _type;
49
+      format = _format;
50
+      id     = _id;
51
+      memcpy(data, _data, _len);
52
+    }
53
+
54
+    /** Creates CAN remote message.
55
+     */
56
+    CANMessage(int _id, CANFormat _format = CANStandard) {
57
+      len    = 0;
58
+      type   = CANRemote;
59
+      format = _format;
60
+      id     = _id;
61
+      memset(data, 0, 8);
62
+    }
63
+};
64
+
65
+/** A can bus client, used for communicating with can devices
66
+ */
67
+class CAN {
68
+
69
+public:
70
+    /** Creates an CAN interface connected to specific pins.
71
+     *
72
+     *  @param rd read from transmitter
73
+     *  @param td transmit to transmitter
74
+     *
75
+     * Example:
76
+     * @code
77
+     * #include "mbed.h"
78
+     *
79
+     * Ticker ticker;
80
+     * DigitalOut led1(LED1);
81
+     * DigitalOut led2(LED2);
82
+     * CAN can1(p9, p10);
83
+     * CAN can2(p30, p29);
84
+     *
85
+     * char counter = 0;
86
+     *
87
+     * void send() {
88
+     *     if(can1.write(CANMessage(1337, &counter, 1))) {
89
+     *         printf("Message sent: %d\n", counter);
90
+     *         counter++;
91
+     *     }
92
+     *     led1 = !led1;
93
+     * }
94
+     *
95
+     * int main() {
96
+     *     ticker.attach(&send, 1);
97
+     *    CANMessage msg;
98
+     *     while(1) {
99
+     *         if(can2.read(msg)) {
100
+     *             printf("Message received: %d\n\n", msg.data[0]);
101
+     *             led2 = !led2;
102
+     *         }
103
+     *         wait(0.2);
104
+     *     }
105
+     * }
106
+     * @endcode
107
+     */
108
+    CAN(PinName rd, PinName td);
109
+    virtual ~CAN();
110
+
111
+    /** Set the frequency of the CAN interface
112
+     *
113
+     *  @param hz The bus frequency in hertz
114
+     *
115
+     *  @returns
116
+     *    1 if successful,
117
+     *    0 otherwise
118
+     */
119
+    int frequency(int hz);
120
+
121
+    /** Write a CANMessage to the bus.
122
+     *
123
+     *  @param msg The CANMessage to write.
124
+     *
125
+     *  @returns
126
+     *    0 if write failed,
127
+     *    1 if write was successful
128
+     */
129
+    int write(CANMessage msg);
130
+
131
+    /** Read a CANMessage from the bus.
132
+     *
133
+     *  @param msg A CANMessage to read to.
134
+     *  @param handle message filter handle (0 for any message)
135
+     *
136
+     *  @returns
137
+     *    0 if no message arrived,
138
+     *    1 if message arrived
139
+     */
140
+    int read(CANMessage &msg, int handle = 0);
141
+
142
+    /** Reset CAN interface.
143
+     *
144
+     * To use after error overflow.
145
+     */
146
+    void reset();
147
+
148
+    /** Puts or removes the CAN interface into silent monitoring mode
149
+     *
150
+     *  @param silent boolean indicating whether to go into silent mode or not
151
+     */
152
+    void monitor(bool silent);
153
+
154
+    enum Mode {
155
+        Reset = 0,
156
+        Normal,
157
+        Silent,
158
+        LocalTest,
159
+        GlobalTest,
160
+        SilentTest
161
+    };
162
+
163
+    /** Change CAN operation to the specified mode
164
+     *
165
+     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
166
+     *
167
+     *  @returns
168
+     *    0 if mode change failed or unsupported,
169
+     *    1 if mode change was successful
170
+     */
171
+    int mode(Mode mode);
172
+
173
+    /** Filter out incomming messages
174
+     *
175
+     *  @param id the id to filter on
176
+     *  @param mask the mask applied to the id
177
+     *  @param format format to filter on (Default CANAny)
178
+     *  @param handle message filter handle (Optional)
179
+     *
180
+     *  @returns
181
+     *    0 if filter change failed or unsupported,
182
+     *    new filter handle if successful
183
+     */
184
+    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
185
+
186
+    /** Returns number of read errors to detect read overflow errors.
187
+     */
188
+    unsigned char rderror();
189
+
190
+    /** Returns number of write errors to detect write overflow errors.
191
+     */
192
+    unsigned char tderror();
193
+
194
+    enum IrqType {
195
+        RxIrq = 0,
196
+        TxIrq,
197
+        EwIrq,
198
+        DoIrq,
199
+        WuIrq,
200
+        EpIrq,
201
+        AlIrq,
202
+        BeIrq,
203
+        IdIrq
204
+    };
205
+
206
+    /** Attach a function to call whenever a CAN frame received interrupt is
207
+     *  generated.
208
+     *
209
+     *  @param fptr A pointer to a void function, or 0 to set as none
210
+     *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
211
+     */
212
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
213
+
214
+   /** Attach a member function to call whenever a CAN frame received interrupt
215
+    *  is generated.
216
+    *
217
+    *  @param tptr pointer to the object to call the member function on
218
+    *  @param mptr pointer to the member function to be called
219
+    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
220
+    */
221
+   template<typename T>
222
+   void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
223
+        if((mptr != NULL) && (tptr != NULL)) {
224
+            _irq[type].attach(tptr, mptr);
225
+            can_irq_set(&_can, (CanIrqType)type, 1);
226
+        }
227
+        else {
228
+            can_irq_set(&_can, (CanIrqType)type, 0);
229
+        }
230
+    }
231
+
232
+    static void _irq_handler(uint32_t id, CanIrqType type);
233
+
234
+protected:
235
+    can_t           _can;
236
+    FunctionPointer _irq[9];
237
+};
238
+
239
+} // namespace mbed
240
+
241
+#endif
242
+
243
+#endif    // MBED_CAN_H

+ 202
- 0
lib/mbed/CThunk.h View File

@@ -0,0 +1,202 @@
1
+/* General C++ Object Thunking class
2
+ *
3
+ * - allows direct callbacks to non-static C++ class functions
4
+ * - keeps track for the corresponding class instance
5
+ * - supports an optional context parameter for the called function
6
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
7
+ *
8
+ * Copyright (c) 2014-2015 ARM Limited
9
+ *
10
+ * Licensed under the Apache License, Version 2.0 (the "License");
11
+ * you may not use this file except in compliance with the License.
12
+ * You may obtain a copy of the License at
13
+ *
14
+ *     http://www.apache.org/licenses/LICENSE-2.0
15
+ *
16
+ * Unless required by applicable law or agreed to in writing, software
17
+ * distributed under the License is distributed on an "AS IS" BASIS,
18
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
19
+ * See the License for the specific language governing permissions and
20
+ * limitations under the License.
21
+ */
22
+#ifndef __CTHUNK_H__
23
+#define __CTHUNK_H__
24
+
25
+#define CTHUNK_ADDRESS 1
26
+
27
+#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)
28
+#define CTHUNK_VARIABLES volatile uint32_t code[1]
29
+/**
30
+* CTHUNK disassembly for Cortex-M3/M4 (thumb2):
31
+* * ldm.w pc,{r0,r1,r2,pc}
32
+*
33
+* This instruction loads the arguments for the static thunking function to r0-r2, and
34
+* branches to that function by loading its address into PC.
35
+*
36
+* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
37
+* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
38
+*/
39
+#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
40
+
41
+#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0)
42
+/*
43
+* CTHUNK disassembly for Cortex M0 (thumb):
44
+* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
45
+* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
46
+* * add r4,pc set up address to load arguments from (immediately following this code block) (2)
47
+* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
48
+* * blx r3 call static thunk function
49
+* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
50
+*/
51
+#define CTHUNK_VARIABLES volatile uint32_t code[3]
52
+#define CTHUNK_ASSIGMENT do {                              \
53
+                             m_thunk.code[0] = 0x2404B51F; \
54
+                             m_thunk.code[1] = 0xCC0F447C; \
55
+                             m_thunk.code[2] = 0xBD1F4798; \
56
+                         } while (0)
57
+
58
+#else
59
+#error "Target is not currently suported."
60
+#endif
61
+
62
+/* IRQ/Exception compatible thunk entry function */
63
+typedef void (*CThunkEntry)(void);
64
+
65
+template<class T>
66
+class CThunk
67
+{
68
+    public:
69
+        typedef void (T::*CCallbackSimple)(void);
70
+        typedef void (T::*CCallback)(void* context);
71
+
72
+        inline CThunk(T *instance)
73
+        {
74
+            init(instance, NULL, NULL);
75
+        }
76
+
77
+        inline CThunk(T *instance, CCallback callback)
78
+        {
79
+            init(instance, callback, NULL);
80
+        }
81
+
82
+        ~CThunk() {
83
+
84
+        }
85
+
86
+        inline CThunk(T *instance, CCallbackSimple callback)
87
+        {
88
+            init(instance, (CCallback)callback, NULL);
89
+        }
90
+
91
+        inline CThunk(T &instance, CCallback callback)
92
+        {
93
+            init(instance, callback, NULL);
94
+        }
95
+
96
+        inline CThunk(T &instance, CCallbackSimple callback)
97
+        {
98
+            init(instance, (CCallback)callback, NULL);
99
+        }
100
+
101
+        inline CThunk(T &instance, CCallback callback, void* context)
102
+        {
103
+            init(instance, callback, context);
104
+        }
105
+
106
+        inline void callback(CCallback callback)
107
+        {
108
+            m_callback = callback;
109
+        }
110
+
111
+        inline void callback(CCallbackSimple callback)
112
+        {
113
+            m_callback = (CCallback)callback;
114
+        }
115
+
116
+        inline void context(void* context)
117
+        {
118
+            m_thunk.context = (uint32_t)context;
119
+        }
120
+
121
+        inline void context(uint32_t context)
122
+        {
123
+            m_thunk.context = context;
124
+        }
125
+        
126
+        inline uint32_t entry(void)
127
+        {
128
+            return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
129
+        }
130
+
131
+        /* get thunk entry point for connecting rhunk to an IRQ table */
132
+        inline operator CThunkEntry(void)
133
+        {
134
+            return (CThunkEntry)entry();
135
+        }
136
+
137
+        /* get thunk entry point for connecting rhunk to an IRQ table */
138
+        inline operator uint32_t(void)
139
+        {
140
+            return entry();
141
+        }
142
+
143
+        /* simple test function */
144
+        inline void call(void)
145
+        {
146
+            (((CThunkEntry)(entry()))());
147
+        }
148
+
149
+    private:
150
+        T* m_instance;
151
+        volatile CCallback m_callback;
152
+
153
+// TODO: this needs proper fix, to refactor toolchain header file and all its use
154
+// PACKED there is not defined properly for IAR
155
+#if defined (__ICCARM__)
156
+        typedef __packed struct
157
+        {
158
+            CTHUNK_VARIABLES;
159
+            volatile uint32_t instance;
160
+            volatile uint32_t context;
161
+            volatile uint32_t callback;
162
+            volatile uint32_t trampoline;
163
+        }  CThunkTrampoline;
164
+#else
165
+        typedef struct
166
+        {
167
+            CTHUNK_VARIABLES;
168
+            volatile uint32_t instance;
169
+            volatile uint32_t context;
170
+            volatile uint32_t callback;
171
+            volatile uint32_t trampoline;
172
+        } __attribute__((__packed__)) CThunkTrampoline;
173
+#endif
174
+
175
+        static void trampoline(T* instance, void* context, CCallback* callback)
176
+        {
177
+            if(instance && *callback) {
178
+                (static_cast<T*>(instance)->**callback)(context);
179
+            }
180
+        }
181
+
182
+        volatile CThunkTrampoline m_thunk;
183
+
184
+        inline void init(T *instance, CCallback callback, void* context)
185
+        {
186
+            /* remember callback - need to add this level of redirection
187
+               as pointer size for member functions differs between platforms */
188
+            m_callback = callback;
189
+
190
+            /* populate thunking trampoline */
191
+            CTHUNK_ASSIGMENT;
192
+            m_thunk.context = (uint32_t)context;
193
+            m_thunk.instance = (uint32_t)instance;
194
+            m_thunk.callback = (uint32_t)&m_callback;
195
+            m_thunk.trampoline = (uint32_t)&trampoline;
196
+
197
+            __ISB();
198
+            __DSB();
199
+        }
200
+};
201
+
202
+#endif/*__CTHUNK_H__*/

+ 181
- 0
lib/mbed/CallChain.h View File

@@ -0,0 +1,181 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_CALLCHAIN_H
17
+#define MBED_CALLCHAIN_H
18
+
19
+#include "FunctionPointer.h"
20
+#include <string.h>
21
+
22
+namespace mbed {
23
+
24
+/** Group one or more functions in an instance of a CallChain, then call them in
25
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
26
+ * but can be used for other purposes.
27
+ *
28
+ * Example:
29
+ * @code
30
+ * #include "mbed.h"
31
+ *
32
+ * CallChain chain;
33
+ *
34
+ * void first(void) {
35
+ *     printf("'first' function.\n");
36
+ * }
37
+ *
38
+ * void second(void) {
39
+ *     printf("'second' function.\n");
40
+ * }
41
+ *
42
+ * class Test {
43
+ * public:
44
+ *     void f(void) {
45
+ *         printf("A::f (class member).\n");
46
+ *     }
47
+ * };
48
+ *
49
+ * int main() {
50
+ *     Test test;
51
+ *
52
+ *     chain.add(second);
53
+ *     chain.add_front(first);
54
+ *     chain.add(&test, &Test::f);
55
+ *     chain.call();
56
+ * }
57
+ * @endcode
58
+ */
59
+
60
+typedef FunctionPointer* pFunctionPointer_t;
61
+
62
+class CallChain {
63
+public:
64
+    /** Create an empty chain
65
+     *
66
+     *  @param size (optional) Initial size of the chain
67
+     */
68
+    CallChain(int size = 4);
69
+    virtual ~CallChain();
70
+
71
+    /** Add a function at the end of the chain
72
+     *
73
+     *  @param function A pointer to a void function
74
+     *
75
+     *  @returns
76
+     *  The function object created for 'function'
77
+     */
78
+    pFunctionPointer_t add(void (*function)(void));
79
+
80
+    /** Add a function at the end of the chain
81
+     *
82
+     *  @param tptr pointer to the object to call the member function on
83
+     *  @param mptr pointer to the member function to be called
84
+     *
85
+     *  @returns
86
+     *  The function object created for 'tptr' and 'mptr'
87
+     */
88
+    template<typename T>
89
+    pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
90
+        return common_add(new FunctionPointer(tptr, mptr));
91
+    }
92
+
93
+    /** Add a function at the beginning of the chain
94
+     *
95
+     *  @param function A pointer to a void function
96
+     *
97
+     *  @returns
98
+     *  The function object created for 'function'
99
+     */
100
+    pFunctionPointer_t add_front(void (*function)(void));
101
+
102
+    /** Add a function at the beginning of the chain
103
+     *
104
+     *  @param tptr pointer to the object to call the member function on
105
+     *  @param mptr pointer to the member function to be called
106
+     *
107
+     *  @returns
108
+     *  The function object created for 'tptr' and 'mptr'
109
+     */
110
+    template<typename T>
111
+    pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
112
+        return common_add_front(new FunctionPointer(tptr, mptr));
113
+    }
114
+
115
+    /** Get the number of functions in the chain
116
+     */
117
+    int size() const;
118
+
119
+    /** Get a function object from the chain
120
+     *
121
+     *  @param i function object index
122
+     *
123
+     *  @returns
124
+     *  The function object at position 'i' in the chain
125
+     */
126
+    pFunctionPointer_t get(int i) const;
127
+
128
+    /** Look for a function object in the call chain
129
+     *
130
+     *  @param f the function object to search
131
+     *
132
+     *  @returns
133
+     *  The index of the function object if found, -1 otherwise.
134
+     */
135
+    int find(pFunctionPointer_t f) const;
136
+
137
+    /** Clear the call chain (remove all functions in the chain).
138
+     */
139
+    void clear();
140
+
141
+    /** Remove a function object from the chain
142
+     *
143
+     *  @arg f the function object to remove
144
+     *
145
+     *  @returns
146
+     *  true if the function object was found and removed, false otherwise.
147
+     */
148
+    bool remove(pFunctionPointer_t f);
149
+
150
+    /** Call all the functions in the chain in sequence
151
+     */
152
+    void call();
153
+
154
+#ifdef MBED_OPERATORS
155
+    void operator ()(void) {
156
+        call();
157
+    }
158
+    pFunctionPointer_t operator [](int i) const {
159
+        return get(i);
160
+    }
161
+#endif
162
+
163
+private:
164
+    void _check_size();
165
+    pFunctionPointer_t common_add(pFunctionPointer_t pf);
166
+    pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
167
+
168
+    pFunctionPointer_t* _chain;
169
+    int _size;
170
+    int _elements;
171
+
172
+    /* disallow copy constructor and assignment operators */
173
+private:
174
+    CallChain(const CallChain&);
175
+    CallChain & operator = (const CallChain&);
176
+};
177
+
178
+} // namespace mbed
179
+
180
+#endif
181
+

+ 98
- 0
lib/mbed/CircularBuffer.h View File

@@ -0,0 +1,98 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_CIRCULARBUFFER_H
17
+#define MBED_CIRCULARBUFFER_H
18
+
19
+namespace mbed {
20
+
21
+/** Templated Circular buffer class
22
+ */
23
+template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
24
+class CircularBuffer {
25
+public:
26
+    CircularBuffer() : _head(0), _tail(0), _full(false) {
27
+    }
28
+
29
+    ~CircularBuffer() {
30
+    }
31
+
32
+    /** Push the transaction to the buffer. This overwrites the buffer if it's
33
+     *  full
34
+     *
35
+     * @param data Data to be pushed to the buffer
36
+     */
37
+    void push(const T& data) {
38
+        if (full()) {
39
+            _tail++;
40
+            _tail %= BufferSize;
41
+        }
42
+        _pool[_head++] = data;
43
+        _head %= BufferSize;
44
+        if (_head == _tail) {
45
+            _full = true;
46
+        }
47
+    }
48
+
49
+    /** Pop the transaction from the buffer
50
+     *
51
+     * @param data Data to be pushed to the buffer
52
+     * @return True if the buffer is not empty and data contains a transaction, false otherwise
53
+     */
54
+    bool pop(T& data) {
55
+        if (!empty()) {
56
+            data = _pool[_tail++];
57
+            _tail %= BufferSize;
58
+            _full = false;
59
+            return true;
60
+        }
61
+        return false;
62
+    }
63
+
64
+    /** Check if the buffer is empty
65
+     *
66
+     * @return True if the buffer is empty, false if not
67
+     */
68
+    bool empty() {
69
+        return (_head == _tail) && !_full;
70
+    }
71
+
72
+    /** Check if the buffer is full
73
+     *
74
+     * @return True if the buffer is full, false if not
75
+     */
76
+    bool full() {
77
+        return _full;
78
+    }
79
+
80
+    /** Reset the buffer
81
+     *
82
+     */
83
+    void reset() {
84
+        _head = 0;
85
+        _tail = 0;
86
+        _full = false;
87
+    }
88
+
89
+private:
90
+    T _pool[BufferSize];
91
+    volatile CounterType _head;
92
+    volatile CounterType _tail;
93
+    volatile bool _full;
94
+};
95
+
96
+}
97
+
98
+#endif

+ 107
- 0
lib/mbed/DigitalIn.h View File

@@ -0,0 +1,107 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_DIGITALIN_H
17
+#define MBED_DIGITALIN_H
18
+
19
+#include "platform.h"
20
+
21
+#include "gpio_api.h"
22
+
23
+namespace mbed {
24
+
25
+/** A digital input, used for reading the state of a pin
26
+ *
27
+ * Example:
28
+ * @code
29
+ * // Flash an LED while a DigitalIn is true
30
+ *
31
+ * #include "mbed.h"
32
+ *
33
+ * DigitalIn enable(p5);
34
+ * DigitalOut led(LED1);
35
+ *
36
+ * int main() {
37
+ *     while(1) {
38
+ *         if(enable) {
39
+ *             led = !led;
40
+ *         }
41
+ *         wait(0.25);
42
+ *     }
43
+ * }
44
+ * @endcode
45
+ */
46
+class DigitalIn {
47
+
48
+public:
49
+    /** Create a DigitalIn connected to the specified pin
50
+     *
51
+     *  @param pin DigitalIn pin to connect to
52
+     */
53
+    DigitalIn(PinName pin) : gpio() {
54
+        gpio_init_in(&gpio, pin);
55
+    }
56
+
57
+    /** Create a DigitalIn connected to the specified pin
58
+     *
59
+     *  @param pin DigitalIn pin to connect to
60
+     *  @param mode the initial mode of the pin
61
+     */
62
+    DigitalIn(PinName pin, PinMode mode) : gpio() {
63
+        gpio_init_in_ex(&gpio, pin, mode);
64
+    }
65
+    /** Read the input, represented as 0 or 1 (int)
66
+     *
67
+     *  @returns
68
+     *    An integer representing the state of the input pin,
69
+     *    0 for logical 0, 1 for logical 1
70
+     */
71
+    int read() {
72
+        return gpio_read(&gpio);
73
+    }
74
+
75
+    /** Set the input pin mode
76
+     *
77
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
78
+     */
79
+    void mode(PinMode pull) {
80
+        gpio_mode(&gpio, pull);
81
+    }
82
+
83
+    /** Return the output setting, represented as 0 or 1 (int)
84
+     *
85
+     *  @returns
86
+     *    Non zero value if pin is connected to uc GPIO
87
+     *    0 if gpio object was initialized with NC
88
+     */
89
+    int is_connected() {
90
+        return gpio_is_connected(&gpio);
91
+    }
92
+
93
+#ifdef MBED_OPERATORS
94
+    /** An operator shorthand for read()
95
+     */
96
+    operator int() {
97
+        return read();
98
+    }
99
+#endif
100
+
101
+protected:
102
+    gpio_t gpio;
103
+};
104
+
105
+} // namespace mbed
106
+
107
+#endif

+ 124
- 0
lib/mbed/DigitalInOut.h View File

@@ -0,0 +1,124 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_DIGITALINOUT_H
17
+#define MBED_DIGITALINOUT_H
18
+
19
+#include "platform.h"
20
+
21
+#include "gpio_api.h"
22
+
23
+namespace mbed {
24
+
25
+/** A digital input/output, used for setting or reading a bi-directional pin
26
+ */
27
+class DigitalInOut {
28
+
29
+public:
30
+    /** Create a DigitalInOut connected to the specified pin
31
+     *
32
+     *  @param pin DigitalInOut pin to connect to
33
+     */
34
+    DigitalInOut(PinName pin) : gpio() {
35
+        gpio_init_in(&gpio, pin);
36
+    }
37
+
38
+    /** Create a DigitalInOut connected to the specified pin
39
+     *
40
+     *  @param pin DigitalInOut pin to connect to
41
+     *  @param direction the initial direction of the pin
42
+     *  @param mode the initial mode of the pin
43
+     *  @param value the initial value of the pin if is an output
44
+     */
45
+    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
46
+        gpio_init_inout(&gpio, pin, direction, mode, value);
47
+    }
48
+
49
+    /** Set the output, specified as 0 or 1 (int)
50
+     *
51
+     *  @param value An integer specifying the pin output value,
52
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
53
+     */
54
+    void write(int value) {
55
+        gpio_write(&gpio, value);
56
+    }
57
+
58
+    /** Return the output setting, represented as 0 or 1 (int)
59
+     *
60
+     *  @returns
61
+     *    an integer representing the output setting of the pin if it is an output,
62
+     *    or read the input if set as an input
63
+     */
64
+    int read() {
65
+        return gpio_read(&gpio);
66
+    }
67
+
68
+    /** Set as an output
69
+     */
70
+    void output() {
71
+        gpio_dir(&gpio, PIN_OUTPUT);
72
+    }
73
+
74
+    /** Set as an input
75
+     */
76
+    void input() {
77
+        gpio_dir(&gpio, PIN_INPUT);
78
+    }
79
+
80
+    /** Set the input pin mode
81
+     *
82
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
83
+     */
84
+    void mode(PinMode pull) {
85
+        gpio_mode(&gpio, pull);
86
+    }
87
+
88
+    /** Return the output setting, represented as 0 or 1 (int)
89
+     *
90
+     *  @returns
91
+     *    Non zero value if pin is connected to uc GPIO
92
+     *    0 if gpio object was initialized with NC
93
+     */
94
+    int is_connected() {
95
+        return gpio_is_connected(&gpio);
96
+    }
97
+
98
+#ifdef MBED_OPERATORS
99
+    /** A shorthand for write()
100
+     */
101
+    DigitalInOut& operator= (int value) {
102
+        write(value);
103
+        return *this;
104
+    }
105
+
106
+    DigitalInOut& operator= (DigitalInOut& rhs) {
107
+        write(rhs.read());
108
+        return *this;
109
+    }
110
+
111
+    /** A shorthand for read()
112
+     */
113
+    operator int() {
114
+        return read();
115
+    }
116
+#endif
117
+
118
+protected:
119
+    gpio_t gpio;
120
+};
121
+
122
+} // namespace mbed
123
+
124
+#endif

+ 116
- 0
lib/mbed/DigitalOut.h View File

@@ -0,0 +1,116 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_DIGITALOUT_H
17
+#define MBED_DIGITALOUT_H
18
+
19
+#include "platform.h"
20
+#include "gpio_api.h"
21
+
22
+namespace mbed {
23
+
24
+/** A digital output, used for setting the state of a pin
25
+ *
26
+ * Example:
27
+ * @code
28
+ * // Toggle a LED
29
+ * #include "mbed.h"
30
+ *
31
+ * DigitalOut led(LED1);
32
+ *
33
+ * int main() {
34
+ *     while(1) {
35
+ *         led = !led;
36
+ *         wait(0.2);
37
+ *     }
38
+ * }
39
+ * @endcode
40
+ */
41
+class DigitalOut {
42
+
43
+public:
44
+    /** Create a DigitalOut connected to the specified pin
45
+     *
46
+     *  @param pin DigitalOut pin to connect to
47
+     */
48
+    DigitalOut(PinName pin) : gpio() {
49
+        gpio_init_out(&gpio, pin);
50
+    }
51
+
52
+    /** Create a DigitalOut connected to the specified pin
53
+     *
54
+     *  @param pin DigitalOut pin to connect to
55
+     *  @param value the initial pin value
56
+     */
57
+    DigitalOut(PinName pin, int value) : gpio() {
58
+        gpio_init_out_ex(&gpio, pin, value);
59
+    }
60
+
61
+    /** Set the output, specified as 0 or 1 (int)
62
+     *
63
+     *  @param value An integer specifying the pin output value,
64
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
65
+     */
66
+    void write(int value) {
67
+        gpio_write(&gpio, value);
68
+    }
69
+
70
+    /** Return the output setting, represented as 0 or 1 (int)
71
+     *
72
+     *  @returns
73
+     *    an integer representing the output setting of the pin,
74
+     *    0 for logical 0, 1 for logical 1
75
+     */
76
+    int read() {
77
+        return gpio_read(&gpio);
78
+    }
79
+
80
+    /** Return the output setting, represented as 0 or 1 (int)
81
+     *
82
+     *  @returns
83
+     *    Non zero value if pin is connected to uc GPIO
84
+     *    0 if gpio object was initialized with NC
85
+     */
86
+    int is_connected() {
87
+        return gpio_is_connected(&gpio);
88
+    }
89
+
90
+#ifdef MBED_OPERATORS
91
+    /** A shorthand for write()
92
+     */
93
+    DigitalOut& operator= (int value) {
94
+        write(value);
95
+        return *this;
96
+    }
97
+
98
+    DigitalOut& operator= (DigitalOut& rhs) {
99
+        write(rhs.read());
100
+        return *this;
101
+    }
102
+
103
+    /** A shorthand for read()
104
+     */
105
+    operator int() {
106
+        return read();
107
+    }
108
+#endif
109
+
110
+protected:
111
+    gpio_t gpio;
112
+};
113
+
114
+} // namespace mbed
115
+
116
+#endif

+ 104
- 0
lib/mbed/DirHandle.h View File

@@ -0,0 +1,104 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_DIRHANDLE_H
17
+#define MBED_DIRHANDLE_H
18
+
19
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
20
+#   define NAME_MAX 255
21
+typedef int mode_t;
22
+
23
+#else
24
+#   include <sys/syslimits.h>
25
+#endif
26
+
27
+#include "FileHandle.h"
28
+
29
+struct dirent {
30
+    char d_name[NAME_MAX+1];
31
+};
32
+
33
+namespace mbed {
34
+
35
+/** Represents a directory stream. Objects of this type are returned
36
+ *  by a FileSystemLike's opendir method. Implementations must define
37
+ *  at least closedir, readdir and rewinddir.
38
+ *
39
+ *  If a FileSystemLike class defines the opendir method, then the
40
+ *  directories of an object of that type can be accessed by
41
+ *  DIR *d = opendir("/example/directory") (or opendir("/example")
42
+ *  to open the root of the filesystem), and then using readdir(d) etc.
43
+ *
44
+ *  The root directory is considered to contain all FileLike and
45
+ *  FileSystemLike objects, so the DIR* returned by opendir("/") will
46
+ *  reflect this.
47
+ */
48
+class DirHandle {
49
+
50
+public:
51
+    /** Closes the directory.
52
+     *
53
+     *  @returns
54
+     *    0 on success,
55
+     *   -1 on error.
56
+     */
57
+    virtual int closedir()=0;
58
+
59
+    /** Return the directory entry at the current position, and
60
+     *  advances the position to the next entry.
61
+     *
62
+     * @returns
63
+     *  A pointer to a dirent structure representing the
64
+     *  directory entry at the current position, or NULL on reaching
65
+     *  end of directory or error.
66
+     */
67
+    virtual struct dirent *readdir()=0;
68
+
69
+    /** Resets the position to the beginning of the directory.
70
+     */
71
+    virtual void rewinddir()=0;
72
+
73
+    /** Returns the current position of the DirHandle.
74
+     *
75
+     * @returns
76
+     *   the current position,
77
+     *  -1 on error.
78
+     */
79
+    virtual off_t telldir() { return -1; }
80
+
81
+    /** Sets the position of the DirHandle.
82
+     *
83
+     *  @param location The location to seek to. Must be a value returned by telldir.
84
+     */
85
+    virtual void seekdir(off_t location) { }
86
+
87
+    virtual ~DirHandle() {}
88
+};
89
+
90
+} // namespace mbed
91
+
92
+typedef mbed::DirHandle DIR;
93
+
94
+extern "C" {
95
+    DIR *opendir(const char*);
96
+    struct dirent *readdir(DIR *);
97
+    int closedir(DIR*);
98
+    void rewinddir(DIR*);
99
+    long telldir(DIR*);
100
+    void seekdir(DIR*, long);
101
+    int mkdir(const char *name, mode_t n);
102
+};
103
+
104
+#endif /* MBED_DIRHANDLE_H */

+ 170
- 0
lib/mbed/Ethernet.h View File

@@ -0,0 +1,170 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ETHERNET_H
17
+#define MBED_ETHERNET_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_ETHERNET
22
+
23
+namespace mbed {
24
+
25
+/** An ethernet interface, to use with the ethernet pins.
26
+ *
27
+ * Example:
28
+ * @code
29
+ * // Read destination and source from every ethernet packet
30
+ *
31
+ * #include "mbed.h"
32
+ *
33
+ * Ethernet eth;
34
+ *
35
+ * int main() {
36
+ *     char buf[0x600];
37
+ *
38
+ *     while(1) {
39
+ *         int size = eth.receive();
40
+ *         if(size > 0) {
41
+ *             eth.read(buf, size);
42
+ *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
43
+ *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
44
+ *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
45
+ *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
46
+ *         }
47
+ *
48
+ *         wait(1);
49
+ *     }
50
+ * }
51
+ * @endcode
52
+ */
53
+class Ethernet {
54
+
55
+public:
56
+
57
+    /** Initialise the ethernet interface.
58
+     */
59
+    Ethernet();
60
+
61
+    /** Powers the hardware down.
62
+     */
63
+    virtual ~Ethernet();
64
+
65
+    enum Mode {
66
+        AutoNegotiate,
67
+        HalfDuplex10,
68
+        FullDuplex10,
69
+        HalfDuplex100,
70
+        FullDuplex100
71
+    };
72
+
73
+    /** Writes into an outgoing ethernet packet.
74
+     *
75
+     *  It will append size bytes of data to the previously written bytes.
76
+     *
77
+     *  @param data An array to write.
78
+     *  @param size The size of data.
79
+     *
80
+     *  @returns
81
+     *   The number of written bytes.
82
+     */
83
+    int write(const char *data, int size);
84
+
85
+    /** Send an outgoing ethernet packet.
86
+     *
87
+     *  After filling in the data in an ethernet packet it must be send.
88
+     *  Send will provide a new packet to write to.
89
+     *
90
+     *  @returns
91
+     *    0 if the sending was failed,
92
+     *    or the size of the packet successfully sent.
93
+     */
94
+    int send();
95
+
96
+    /** Recevies an arrived ethernet packet.
97
+     *
98
+     *  Receiving an ethernet packet will drop the last received ethernet packet
99
+     *  and make a new ethernet packet ready to read.
100
+     *  If no ethernet packet is arrived it will return 0.
101
+     *
102
+     *  @returns
103
+     *    0 if no ethernet packet is arrived,
104
+     *    or the size of the arrived packet.
105
+     */
106
+    int receive();
107
+
108
+    /** Read from an recevied ethernet packet.
109
+     *
110
+     *  After receive returnd a number bigger than 0it is
111
+     *  possible to read bytes from this packet.
112
+     *  Read will write up to size bytes into data.
113
+     *
114
+     *  It is possible to use read multible times.
115
+     *  Each time read will start reading after the last read byte before.
116
+     *
117
+     *  @returns
118
+     *  The number of byte read.
119
+     */
120
+    int read(char *data, int size);
121
+
122
+    /** Gives the ethernet address of the mbed.
123
+     *
124
+     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
125
+     */
126
+    void address(char *mac);
127
+
128
+    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
129
+     *
130
+     *  @returns
131
+     *   0 if no ethernet link is pressent,
132
+     *   1 if an ethernet link is pressent.
133
+     *
134
+     * Example:
135
+     * @code
136
+     * // Using the Ethernet link function
137
+     * #include "mbed.h"
138
+     *
139
+     * Ethernet eth;
140
+     *
141
+     * int main() {
142
+     *     wait(1); // Needed after startup.
143
+     *     if (eth.link()) {
144
+     *          printf("online\n");
145
+     *     } else {
146
+     *          printf("offline\n");
147
+     *     }
148
+     * }
149
+     * @endcode
150
+     */
151
+    int link();
152
+
153
+    /** Sets the speed and duplex parameters of an ethernet link
154
+     *
155
+     * - AutoNegotiate      Auto negotiate speed and duplex
156
+     * - HalfDuplex10       10 Mbit, half duplex
157
+     * - FullDuplex10       10 Mbit, full duplex
158
+     * - HalfDuplex100      100 Mbit, half duplex
159
+     * - FullDuplex100      100 Mbit, full duplex
160
+     *
161
+     *  @param mode the speed and duplex mode to set the link to:
162
+     */
163
+    void set_link(Mode mode);
164
+};
165
+
166
+} // namespace mbed
167
+
168
+#endif
169
+
170
+#endif

+ 80
- 0
lib/mbed/FileBase.h View File

@@ -0,0 +1,80 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_FILEBASE_H
17
+#define MBED_FILEBASE_H
18
+
19
+typedef int FILEHANDLE;
20
+
21
+#include <stdio.h>
22
+
23
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
24
+#    define O_RDONLY 0
25
+#    define O_WRONLY 1
26
+#    define O_RDWR   2
27
+#    define O_CREAT  0x0200
28
+#    define O_TRUNC  0x0400
29
+#    define O_APPEND 0x0008
30
+
31
+#    define NAME_MAX 255
32
+
33
+typedef int mode_t;
34
+typedef int ssize_t;
35
+typedef long off_t;
36
+
37
+#else
38
+#    include <sys/fcntl.h>
39
+#    include <sys/types.h>
40
+#    include <sys/syslimits.h>
41
+#endif
42
+
43
+#include "platform.h"
44
+
45
+namespace mbed {
46
+
47
+typedef enum {
48
+    FilePathType,
49
+    FileSystemPathType
50
+} PathType;
51
+
52
+class FileBase {
53
+public:
54
+    FileBase(const char *name, PathType t);
55
+
56
+    virtual ~FileBase();
57
+
58
+    const char* getName(void);
59
+    PathType    getPathType(void);
60
+
61
+    static FileBase *lookup(const char *name, unsigned int len);
62
+
63
+    static FileBase *get(int n);
64
+
65
+protected:
66
+    static FileBase *_head;
67
+
68
+    FileBase   *_next;
69
+    const char *_name;
70
+    PathType    _path_type;
71
+
72
+    /* disallow copy constructor and assignment operators */
73
+private:
74
+    FileBase(const FileBase&);
75
+    FileBase & operator = (const FileBase&);
76
+};
77
+
78
+} // namespace mbed
79
+
80
+#endif

+ 119
- 0
lib/mbed/FileHandle.h View File

@@ -0,0 +1,119 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_FILEHANDLE_H
17
+#define MBED_FILEHANDLE_H
18
+
19
+typedef int FILEHANDLE;
20
+
21
+#include <stdio.h>
22
+
23
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
24
+typedef int ssize_t;
25
+typedef long off_t;
26
+
27
+#else
28
+#   include <sys/types.h>
29
+#endif
30
+
31
+namespace mbed {
32
+
33
+/** An OO equivalent of the internal FILEHANDLE variable
34
+ *  and associated _sys_* functions.
35
+ *
36
+ * FileHandle is an abstract class, needing at least sys_write and
37
+ *  sys_read to be implmented for a simple interactive device.
38
+ *
39
+ * No one ever directly tals to/instanciates a FileHandle - it gets
40
+ *  created by FileSystem, and wrapped up by stdio.
41
+ */
42
+class FileHandle {
43
+
44
+public:
45
+    /** Write the contents of a buffer to the file
46
+     *
47
+     *  @param buffer the buffer to write from
48
+     *  @param length the number of characters to write
49
+     *
50
+     *  @returns
51
+     *  The number of characters written (possibly 0) on success, -1 on error.
52
+     */
53
+    virtual ssize_t write(const void* buffer, size_t length) = 0;
54
+
55
+    /** Close the file
56
+     *
57
+     *  @returns
58
+     *  Zero on success, -1 on error.
59
+     */
60
+    virtual int close() = 0;
61
+
62
+    /** Function read
63
+     *  Reads the contents of the file into a buffer
64
+     *
65
+     *  @param buffer the buffer to read in to
66
+     *  @param length the number of characters to read
67
+     *
68
+     *  @returns
69
+     *  The number of characters read (zero at end of file) on success, -1 on error.
70
+     */
71
+    virtual ssize_t read(void* buffer, size_t length) = 0;
72
+
73
+    /** Check if the handle is for a interactive terminal device.
74
+     * If so, line buffered behaviour is used by default
75
+     *
76
+     *  @returns
77
+     *    1 if it is a terminal,
78
+     *    0 otherwise
79
+     */
80
+    virtual int isatty() = 0;
81
+
82
+    /** Move the file position to a given offset from a given location.
83
+     *
84
+     *  @param offset The offset from whence to move to
85
+     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
86
+     *   current file position, or SEEK_END for the end of the file.
87
+     *
88
+     *  @returns
89
+     *    new file position on success,
90
+     *    -1 on failure or unsupported
91
+     */
92
+    virtual off_t lseek(off_t offset, int whence) = 0;
93
+
94
+    /** Flush any buffers associated with the FileHandle, ensuring it
95
+     *  is up to date on disk
96
+     *
97
+     *  @returns
98
+     *    0 on success or un-needed,
99
+     *   -1 on error
100
+     */
101
+    virtual int fsync() = 0;
102
+
103
+    virtual off_t flen() {
104
+        /* remember our current position */
105
+        off_t pos = lseek(0, SEEK_CUR);
106
+        if(pos == -1) return -1;
107
+        /* seek to the end to get the file length */
108
+        off_t res = lseek(0, SEEK_END);
109
+        /* return to our old position */
110
+        lseek(pos, SEEK_SET);
111
+        return res;
112
+    }
113
+
114
+    virtual ~FileHandle();
115
+};
116
+
117
+} // namespace mbed
118
+
119
+#endif

+ 44
- 0
lib/mbed/FileLike.h View File

@@ -0,0 +1,44 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_FILELIKE_H
17
+#define MBED_FILELIKE_H
18
+
19
+#include "FileBase.h"
20
+#include "FileHandle.h"
21
+
22
+namespace mbed {
23
+
24
+/* Class FileLike
25
+ *  A file-like object is one that can be opened with fopen by
26
+ *  fopen("/name", mode). It is intersection of the classes Base and
27
+ *  FileHandle.
28
+ */
29
+class FileLike : public FileHandle, public FileBase {
30
+
31
+public:
32
+    /* Constructor FileLike
33
+     *
34
+     * Variables
35
+     *  name - The name to use to open the file.
36
+     */
37
+    FileLike(const char *name);
38
+
39
+    virtual ~FileLike();
40
+};
41
+
42
+} // namespace mbed
43
+
44
+#endif

+ 46
- 0
lib/mbed/FilePath.h View File

@@ -0,0 +1,46 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_FILEPATH_H
17
+#define MBED_FILEPATH_H
18
+
19
+#include "platform.h"
20
+
21
+#include "FileSystemLike.h"
22
+#include "FileLike.h"
23
+
24
+namespace mbed {
25
+
26
+class FilePath {
27
+public:
28
+    FilePath(const char* file_path);
29
+
30
+    const char* fileName(void);
31
+
32
+    bool          isFileSystem(void);
33
+    FileSystemLike* fileSystem(void);
34
+
35
+    bool    isFile(void);
36
+    FileLike* file(void);
37
+    bool    exists(void);
38
+
39
+private:
40
+    const char* file_name;
41
+    FileBase* fb;
42
+};
43
+
44
+} // namespace mbed
45
+
46
+#endif

+ 104
- 0
lib/mbed/FileSystemLike.h View File

@@ -0,0 +1,104 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_FILESYSTEMLIKE_H
17
+#define MBED_FILESYSTEMLIKE_H
18
+
19
+#include "platform.h"
20
+
21
+#include "FileBase.h"
22
+#include "FileHandle.h"
23
+#include "DirHandle.h"
24
+
25
+namespace mbed {
26
+
27
+/** A filesystem-like object is one that can be used to open files
28
+ *  though it by fopen("/name/filename", mode)
29
+ *
30
+ *  Implementations must define at least open (the default definitions
31
+ *  of the rest of the functions just return error values).
32
+ */
33
+class FileSystemLike : public FileBase {
34
+
35
+public:
36
+    /** FileSystemLike constructor
37
+     *
38
+     *  @param name The name to use for the filesystem.
39
+     */
40
+    FileSystemLike(const char *name);
41
+
42
+    virtual ~FileSystemLike();
43
+
44
+    static DirHandle *opendir();
45
+    friend class BaseDirHandle;
46
+
47
+    /** Opens a file from the filesystem
48
+     *
49
+     *  @param filename The name of the file to open.
50
+     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
51
+     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
52
+     *
53
+     *  @returns
54
+     *    A pointer to a FileHandle object representing the
55
+     *   file on success, or NULL on failure.
56
+     */
57
+    virtual FileHandle *open(const char *filename, int flags) = 0;
58
+
59
+    /** Remove a file from the filesystem.
60
+     *
61
+     *  @param filename the name of the file to remove.
62
+     *  @param returns 0 on success, -1 on failure.
63
+     */
64
+    virtual int remove(const char *filename) { return -1; };
65
+
66
+    /** Rename a file in the filesystem.
67
+     *
68
+     *  @param oldname the name of the file to rename.
69
+     *  @param newname the name to rename it to.
70
+     *
71
+     *  @returns
72
+     *    0 on success,
73
+     *   -1 on failure.
74
+     */
75
+    virtual int rename(const char *oldname, const char *newname) { return -1; };
76
+
77
+    /** Opens a directory in the filesystem and returns a DirHandle
78
+     *   representing the directory stream.
79
+     *
80
+     *  @param name The name of the directory to open.
81
+     *
82
+     *  @returns
83
+     *    A DirHandle representing the directory stream, or
84
+     *   NULL on failure.
85
+     */
86
+    virtual DirHandle *opendir(const char *name) { return NULL; };
87
+
88
+    /** Creates a directory in the filesystem.
89
+     *
90
+     *  @param name The name of the directory to create.
91
+     *  @param mode The permissions to create the directory with.
92
+     *
93
+     *  @returns
94
+     *    0 on success,
95
+     *   -1 on failure.
96
+     */
97
+    virtual int mkdir(const char *name, mode_t mode) { return -1; }
98
+
99
+    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
100
+};
101
+
102
+} // namespace mbed
103
+
104
+#endif

+ 202
- 0
lib/mbed/FunctionPointer.h View File

@@ -0,0 +1,202 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_FUNCTIONPOINTER_H
17
+#define MBED_FUNCTIONPOINTER_H
18
+
19
+#include <string.h>
20
+#include <stdint.h>
21
+
22
+namespace mbed {
23
+
24
+/* If we had variaditic templates, this wouldn't be a problem, but until C++11 is enabled, we are stuck with multiple classes... */
25
+
26
+/** A class for storing and calling a pointer to a static or member function
27
+ */
28
+template <typename R, typename A1>
29
+class FunctionPointerArg1{
30
+public:
31
+    /** Create a FunctionPointer, attaching a static function
32
+     *
33
+     *  @param function The static function to attach (default is none)
34
+     */
35
+    FunctionPointerArg1(R (*function)(A1) = 0) {
36
+        attach(function);
37
+    }
38
+
39
+    /** Create a FunctionPointer, attaching a member function
40
+     *
41
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
42
+     *  @param function The address of the member function to attach
43
+     */
44
+    template<typename T>
45
+    FunctionPointerArg1(T *object, R (T::*member)(A1)) {
46
+        attach(object, member);
47
+    }
48
+
49
+    /** Attach a static function
50
+     *
51
+     *  @param function The static function to attach (default is none)
52
+     */
53
+    void attach(R (*function)(A1)) {
54
+        _p.function = function;
55
+        _membercaller = 0;
56
+    }
57
+
58
+    /** Attach a member function
59
+     *
60
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
61
+     *  @param function The address of the member function to attach
62
+     */
63
+    template<typename T>
64
+    void attach(T *object, R (T::*member)(A1)) {
65
+        _p.object = static_cast<void*>(object);
66
+        *reinterpret_cast<R (T::**)(A1)>(_member) = member;
67
+        _membercaller = &FunctionPointerArg1::membercaller<T>;
68
+    }
69
+
70
+    /** Call the attached static or member function
71
+     */
72
+    R call(A1 a) {
73
+        if (_membercaller == 0 && _p.function) {
74
+           return _p.function(a);
75
+        } else if (_membercaller && _p.object) {
76
+           return _membercaller(_p.object, _member, a);
77
+        }
78
+        return (R)0;
79
+    }
80
+
81
+    /** Get registered static function
82
+     */
83
+    R(*get_function(A1))() {
84
+        return _membercaller ? (R(*)(A1))0 : (R(*)(A1))_p.function;
85
+    }
86
+
87
+#ifdef MBED_OPERATORS
88
+    R operator ()(A1 a) {
89
+        return call(a);
90
+    }
91
+    operator bool(void) const {
92
+        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;
93
+    }
94
+#endif
95
+private:
96
+    template<typename T>
97
+    static R membercaller(void *object, uintptr_t *member, A1 a) {
98
+        T* o = static_cast<T*>(object);
99
+        R (T::**m)(A1) = reinterpret_cast<R (T::**)(A1)>(member);
100
+        return (o->**m)(a);
101
+    }
102
+
103
+    union {
104
+        R (*function)(A1); // static function pointer
105
+        void *object;      // object this pointer
106
+    } _p;
107
+    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller
108
+    R (*_membercaller)(void*, uintptr_t*, A1); // registered membercaller function to convert back and call _m.member on _object
109
+};
110
+
111
+/** A class for storing and calling a pointer to a static or member function (R ()(void))
112
+ */
113
+template <typename R>
114
+class FunctionPointerArg1<R, void>{
115
+public:
116
+    /** Create a FunctionPointer, attaching a static function
117
+     *
118
+     *  @param function The static function to attach (default is none)
119
+     */
120
+    FunctionPointerArg1(R (*function)(void) = 0) {
121
+        attach(function);
122
+    }
123
+
124
+    /** Create a FunctionPointer, attaching a member function
125
+     *
126
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
127
+     *  @param function The address of the void member function to attach
128
+     */
129
+    template<typename T>
130
+    FunctionPointerArg1(T *object, R (T::*member)(void)) {
131
+        attach(object, member);
132
+    }
133
+
134
+    /** Attach a static function
135
+     *
136
+     *  @param function The void static function to attach (default is none)
137
+     */
138
+    void attach(R (*function)(void)) {
139
+        _p.function = function;
140
+        _membercaller = 0;
141
+    }
142
+
143
+    /** Attach a member function
144
+     *
145
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
146
+     *  @param function The address of the void member function to attach
147
+     */
148
+    template<typename T>
149
+    void attach(T *object, R (T::*member)(void)) {
150
+        _p.object = static_cast<void*>(object);
151
+        *reinterpret_cast<R (T::**)(void)>(_member) = member;
152
+        _membercaller = &FunctionPointerArg1::membercaller<T>;
153
+    }
154
+
155
+    /** Call the attached static or member function
156
+     */
157
+    R call(){
158
+        if (_membercaller == 0 && _p.function) {
159
+            return _p.function();
160
+        } else if (_membercaller && _p.object) {
161
+            return _membercaller(_p.object, _member);
162
+        }
163
+        return (R)0;
164
+    }
165
+
166
+    /** Get registered static function
167
+     */
168
+    R(*get_function())() {
169
+        return _membercaller ? (R(*)())0 : (R(*)())_p.function;
170
+    }
171
+
172
+#ifdef MBED_OPERATORS
173
+    R operator ()(void) {
174
+        return call();
175
+    }
176
+    operator bool(void) const {
177
+        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;
178
+    }
179
+#endif
180
+
181
+private:
182
+    template<typename T>
183
+    static R membercaller(void *object, uintptr_t *member) {
184
+        T* o = static_cast<T*>(object);
185
+        R (T::**m)(void) = reinterpret_cast<R (T::**)(void)>(member);
186
+        return (o->**m)();
187
+    }
188
+
189
+    union {
190
+        R (*function)(void); // static function pointer
191
+        void *object;        // object this pointer
192
+    } _p;
193
+    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller
194
+    R (*_membercaller)(void*, uintptr_t*); // registered membercaller function to convert back and call _m.member on _object
195
+};
196
+
197
+typedef FunctionPointerArg1<void, void> FunctionPointer;
198
+typedef FunctionPointerArg1<void, int> event_callback_t;
199
+
200
+} // namespace mbed
201
+
202
+#endif

+ 176
- 0
lib/mbed/I2C.h View File

@@ -0,0 +1,176 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_I2C_H
17
+#define MBED_I2C_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_I2C
22
+
23
+#include "i2c_api.h"
24
+
25
+#if DEVICE_I2C_ASYNCH
26
+#include "CThunk.h"
27
+#include "dma_api.h"
28
+#include "FunctionPointer.h"
29
+#endif
30
+
31
+namespace mbed {
32
+
33
+/** An I2C Master, used for communicating with I2C slave devices
34
+ *
35
+ * Example:
36
+ * @code
37
+ * // Read from I2C slave at address 0x62
38
+ *
39
+ * #include "mbed.h"
40
+ *
41
+ * I2C i2c(p28, p27);
42
+ *
43
+ * int main() {
44
+ *     int address = 0x62;
45
+ *     char data[2];
46
+ *     i2c.read(address, data, 2);
47
+ * }
48
+ * @endcode
49
+ */
50
+class I2C {
51
+
52
+public:
53
+    enum RxStatus {
54
+        NoData,
55
+        MasterGeneralCall,
56
+        MasterWrite,
57
+        MasterRead
58
+    };
59
+
60
+    enum Acknowledge {
61
+        NoACK = 0,
62
+        ACK   = 1
63
+    };
64
+
65
+    /** Create an I2C Master interface, connected to the specified pins
66
+     *
67
+     *  @param sda I2C data line pin
68
+     *  @param scl I2C clock line pin
69
+     */
70
+    I2C(PinName sda, PinName scl);
71
+
72
+    /** Set the frequency of the I2C interface
73
+     *
74
+     *  @param hz The bus frequency in hertz
75
+     */
76
+    void frequency(int hz);
77
+
78
+    /** Read from an I2C slave
79
+     *
80
+     * Performs a complete read transaction. The bottom bit of
81
+     * the address is forced to 1 to indicate a read.
82
+     *
83
+     *  @param address 8-bit I2C slave address [ addr | 1 ]
84
+     *  @param data Pointer to the byte-array to read data in to
85
+     *  @param length Number of bytes to read
86
+     *  @param repeated Repeated start, true - don't send stop at end
87
+     *
88
+     *  @returns
89
+     *       0 on success (ack),
90
+     *   non-0 on failure (nack)
91
+     */
92
+    int read(int address, char *data, int length, bool repeated = false);
93
+
94
+    /** Read a single byte from the I2C bus
95
+     *
96
+     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
97
+     *
98
+     *  @returns
99
+     *    the byte read
100
+     */
101
+    int read(int ack);
102
+
103
+    /** Write to an I2C slave
104
+     *
105
+     * Performs a complete write transaction. The bottom bit of
106
+     * the address is forced to 0 to indicate a write.
107
+     *
108
+     *  @param address 8-bit I2C slave address [ addr | 0 ]
109
+     *  @param data Pointer to the byte-array data to send
110
+     *  @param length Number of bytes to send
111
+     *  @param repeated Repeated start, true - do not send stop at end
112
+     *
113
+     *  @returns
114
+     *       0 on success (ack),
115
+     *   non-0 on failure (nack)
116
+     */
117
+    int write(int address, const char *data, int length, bool repeated = false);
118
+
119
+    /** Write single byte out on the I2C bus
120
+     *
121
+     *  @param data data to write out on bus
122
+     *
123
+     *  @returns
124
+     *    '1' if an ACK was received,
125
+     *    '0' otherwise
126
+     */
127
+    int write(int data);
128
+
129
+    /** Creates a start condition on the I2C bus
130
+     */
131
+
132
+    void start(void);
133
+
134
+    /** Creates a stop condition on the I2C bus
135
+     */
136
+    void stop(void);
137
+
138
+#if DEVICE_I2C_ASYNCH
139
+
140
+    /** Start non-blocking I2C transfer.
141
+     *
142
+     * @param address   8/10 bit I2c slave address
143
+     * @param tx_buffer The TX buffer with data to be transfered
144
+     * @param tx_length The length of TX buffer in bytes
145
+     * @param rx_buffer The RX buffer which is used for received data
146
+     * @param rx_length The length of RX buffer in bytes
147
+     * @param event     The logical OR of events to modify
148
+     * @param callback  The event callback function
149
+     * @param repeated Repeated start, true - do not send stop at end
150
+     * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
151
+     */
152
+    int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
153
+
154
+    /** Abort the on-going I2C transfer
155
+     */
156
+    void abort_transfer();
157
+protected:
158
+    void irq_handler_asynch(void);
159
+    event_callback_t _callback;
160
+    CThunk<I2C> _irq;
161
+    DMAUsage _usage;
162
+#endif
163
+
164
+protected:
165
+    void aquire();
166
+
167
+    i2c_t _i2c;
168
+    static I2C  *_owner;
169
+    int         _hz;
170
+};
171
+
172
+} // namespace mbed
173
+
174
+#endif
175
+
176
+#endif

+ 154
- 0
lib/mbed/I2CSlave.h View File

@@ -0,0 +1,154 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_I2C_SLAVE_H
17
+#define MBED_I2C_SLAVE_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_I2CSLAVE
22
+
23
+#include "i2c_api.h"
24
+
25
+namespace mbed {
26
+
27
+/** An I2C Slave, used for communicating with an I2C Master device
28
+ *
29
+ * Example:
30
+ * @code
31
+ * // Simple I2C responder
32
+ * #include <mbed.h>
33
+ *
34
+ * I2CSlave slave(p9, p10);
35
+ *
36
+ * int main() {
37
+ *     char buf[10];
38
+ *     char msg[] = "Slave!";
39
+ *
40
+ *     slave.address(0xA0);
41
+ *     while (1) {
42
+ *         int i = slave.receive();
43
+ *         switch (i) {
44
+ *             case I2CSlave::ReadAddressed:
45
+ *                 slave.write(msg, strlen(msg) + 1); // Includes null char
46
+ *                 break;
47
+ *             case I2CSlave::WriteGeneral:
48
+ *                 slave.read(buf, 10);
49
+ *                 printf("Read G: %s\n", buf);
50
+ *                 break;
51
+ *             case I2CSlave::WriteAddressed:
52
+ *                 slave.read(buf, 10);
53
+ *                 printf("Read A: %s\n", buf);
54
+ *                 break;
55
+ *         }
56
+ *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
57
+ *     }
58
+ * }
59
+ * @endcode
60
+ */
61
+class I2CSlave {
62
+
63
+public:
64
+    enum RxStatus {
65
+        NoData         = 0,
66
+        ReadAddressed  = 1,
67
+        WriteGeneral   = 2,
68
+        WriteAddressed = 3
69
+    };
70
+
71
+    /** Create an I2C Slave interface, connected to the specified pins.
72
+     *
73
+     *  @param sda I2C data line pin
74
+     *  @param scl I2C clock line pin
75
+     */
76
+    I2CSlave(PinName sda, PinName scl);
77
+
78
+    /** Set the frequency of the I2C interface
79
+     *
80
+     *  @param hz The bus frequency in hertz
81
+     */
82
+    void frequency(int hz);
83
+
84
+    /** Checks to see if this I2C Slave has been addressed.
85
+     *
86
+     *  @returns
87
+     *  A status indicating if the device has been addressed, and how
88
+     *  - NoData            - the slave has not been addressed
89
+     *  - ReadAddressed     - the master has requested a read from this slave
90
+     *  - WriteAddressed    - the master is writing to this slave
91
+     *  - WriteGeneral      - the master is writing to all slave
92
+     */
93
+    int receive(void);
94
+
95
+    /** Read from an I2C master.
96
+     *
97
+     *  @param data pointer to the byte array to read data in to
98
+     *  @param length maximum number of bytes to read
99
+     *
100
+     *  @returns
101
+     *       0 on success,
102
+     *   non-0 otherwise
103
+     */
104
+    int read(char *data, int length);
105
+
106
+    /** Read a single byte from an I2C master.
107
+     *
108
+     *  @returns
109
+     *    the byte read
110
+     */
111
+    int read(void);
112
+
113
+    /** Write to an I2C master.
114
+     *
115
+     *  @param data pointer to the byte array to be transmitted
116
+     *  @param length the number of bytes to transmite
117
+     *
118
+     *  @returns
119
+     *       0 on success,
120
+     *   non-0 otherwise
121
+     */
122
+    int write(const char *data, int length);
123
+
124
+    /** Write a single byte to an I2C master.
125
+     *
126
+     *  @data the byte to write
127
+     *
128
+     *  @returns
129
+     *    '1' if an ACK was received,
130
+     *    '0' otherwise
131
+     */
132
+    int write(int data);
133
+
134
+    /** Sets the I2C slave address.
135
+     *
136
+     *  @param address The address to set for the slave (ignoring the least
137
+     *  signifcant bit). If set to 0, the slave will only respond to the
138
+     *  general call address.
139
+     */
140
+    void address(int address);
141
+
142
+    /** Reset the I2C slave back into the known ready receiving state.
143
+     */
144
+    void stop(void);
145
+
146
+protected:
147
+    i2c_t _i2c;
148
+};
149
+
150
+} // namespace mbed
151
+
152
+#endif
153
+
154
+#endif

+ 135
- 0
lib/mbed/InterruptIn.h View File

@@ -0,0 +1,135 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_INTERRUPTIN_H
17
+#define MBED_INTERRUPTIN_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_INTERRUPTIN
22
+
23
+#include "gpio_api.h"
24
+#include "gpio_irq_api.h"
25
+#include "FunctionPointer.h"
26
+
27
+namespace mbed {
28
+
29
+/** A digital interrupt input, used to call a function on a rising or falling edge
30
+ *
31
+ * Example:
32
+ * @code
33
+ * // Flash an LED while waiting for events
34
+ *
35
+ * #include "mbed.h"
36
+ *
37
+ * InterruptIn event(p16);
38
+ * DigitalOut led(LED1);
39
+ *
40
+ * void trigger() {
41
+ *     printf("triggered!\n");
42
+ * }
43
+ *
44
+ * int main() {
45
+ *     event.rise(&trigger);
46
+ *     while(1) {
47
+ *         led = !led;
48
+ *         wait(0.25);
49
+ *     }
50
+ * }
51
+ * @endcode
52
+ */
53
+class InterruptIn {
54
+
55
+public:
56
+
57
+    /** Create an InterruptIn connected to the specified pin
58
+     *
59
+     *  @param pin InterruptIn pin to connect to
60
+     *  @param name (optional) A string to identify the object
61
+     */
62
+    InterruptIn(PinName pin);
63
+    virtual ~InterruptIn();
64
+
65
+     int read();
66
+#ifdef MBED_OPERATORS
67
+    operator int();
68
+
69
+#endif
70
+
71
+    /** Attach a function to call when a rising edge occurs on the input
72
+     *
73
+     *  @param fptr A pointer to a void function, or 0 to set as none
74
+     */
75
+    void rise(void (*fptr)(void));
76
+
77
+    /** Attach a member function to call when a rising edge occurs on the input
78
+     *
79
+     *  @param tptr pointer to the object to call the member function on
80
+     *  @param mptr pointer to the member function to be called
81
+     */
82
+    template<typename T>
83
+    void rise(T* tptr, void (T::*mptr)(void)) {
84
+        _rise.attach(tptr, mptr);
85
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
86
+    }
87
+
88
+    /** Attach a function to call when a falling edge occurs on the input
89
+     *
90
+     *  @param fptr A pointer to a void function, or 0 to set as none
91
+     */
92
+    void fall(void (*fptr)(void));
93
+
94
+    /** Attach a member function to call when a falling edge occurs on the input
95
+     *
96
+     *  @param tptr pointer to the object to call the member function on
97
+     *  @param mptr pointer to the member function to be called
98
+     */
99
+    template<typename T>
100
+    void fall(T* tptr, void (T::*mptr)(void)) {
101
+        _fall.attach(tptr, mptr);
102
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
103
+    }
104
+
105
+    /** Set the input pin mode
106
+     *
107
+     *  @param mode PullUp, PullDown, PullNone
108
+     */
109
+    void mode(PinMode pull);
110
+
111
+    /** Enable IRQ. This method depends on hw implementation, might enable one
112
+     *  port interrupts. For further information, check gpio_irq_enable().
113
+     */
114
+    void enable_irq();
115
+
116
+    /** Disable IRQ. This method depends on hw implementation, might disable one
117
+     *  port interrupts. For further information, check gpio_irq_disable().
118
+     */
119
+    void disable_irq();
120
+
121
+    static void _irq_handler(uint32_t id, gpio_irq_event event);
122
+
123
+protected:
124
+    gpio_t gpio;
125
+    gpio_irq_t gpio_irq;
126
+
127
+    FunctionPointer _rise;
128
+    FunctionPointer _fall;
129
+};
130
+
131
+} // namespace mbed
132
+
133
+#endif
134
+
135
+#endif

+ 143
- 0
lib/mbed/InterruptManager.h View File

@@ -0,0 +1,143 @@
1
+#ifndef MBED_INTERRUPTMANAGER_H
2
+#define MBED_INTERRUPTMANAGER_H
3
+
4
+#include "cmsis.h"
5
+#include "CallChain.h"
6
+#include <string.h>
7
+
8
+namespace mbed {
9
+
10
+/** Use this singleton if you need to chain interrupt handlers.
11
+ *
12
+ * Example (for LPC1768):
13
+ * @code
14
+ * #include "InterruptManager.h"
15
+ * #include "mbed.h"
16
+ *
17
+ * Ticker flipper;
18
+ * DigitalOut led1(LED1);
19
+ * DigitalOut led2(LED2);
20
+ *
21
+ * void flip(void) {
22
+ *     led1 = !led1;
23
+ * }
24
+ *
25
+ * void handler(void) {
26
+ *     led2 = !led1;
27
+ * }
28
+ *
29
+ * int main() {
30
+ *     led1 = led2 = 0;
31
+ *     flipper.attach(&flip, 1.0);
32
+ *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
33
+ * }
34
+ * @endcode
35
+ */
36
+class InterruptManager {
37
+public:
38
+    /** Return the only instance of this class
39
+     */
40
+    static InterruptManager* get();
41
+
42
+    /** Destroy the current instance of the interrupt manager
43
+     */
44
+    static void destroy();
45
+
46
+    /** Add a handler for an interrupt at the end of the handler list
47
+     *
48
+     *  @param function the handler to add
49
+     *  @param irq interrupt number
50
+     *
51
+     *  @returns
52
+     *  The function object created for 'function'
53
+     */
54
+    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
55
+        return add_common(function, irq);
56
+    }
57
+
58
+    /** Add a handler for an interrupt at the beginning of the handler list
59
+     *
60
+     *  @param function the handler to add
61
+     *  @param irq interrupt number
62
+     *
63
+     *  @returns
64
+     *  The function object created for 'function'
65
+     */
66
+    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
67
+        return add_common(function, irq, true);
68
+    }
69
+
70
+    /** Add a handler for an interrupt at the end of the handler list
71
+     *
72
+     *  @param tptr pointer to the object that has the handler function
73
+     *  @param mptr pointer to the actual handler function
74
+     *  @param irq interrupt number
75
+     *
76
+     *  @returns
77
+     *  The function object created for 'tptr' and 'mptr'
78
+     */
79
+    template<typename T>
80
+    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
81
+        return add_common(tptr, mptr, irq);
82
+    }
83
+
84
+    /** Add a handler for an interrupt at the beginning of the handler list
85
+     *
86
+     *  @param tptr pointer to the object that has the handler function
87
+     *  @param mptr pointer to the actual handler function
88
+     *  @param irq interrupt number
89
+     *
90
+     *  @returns
91
+     *  The function object created for 'tptr' and 'mptr'
92
+     */
93
+    template<typename T>
94
+    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
95
+        return add_common(tptr, mptr, irq, true);
96
+    }
97
+
98
+    /** Remove a handler from an interrupt
99
+     *
100
+     *  @param handler the function object for the handler to remove
101
+     *  @param irq the interrupt number
102
+     *
103
+     *  @returns
104
+     *  true if the handler was found and removed, false otherwise
105
+     */
106
+    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
107
+
108
+private:
109
+    InterruptManager();
110
+    ~InterruptManager();
111
+
112
+    // We declare the copy contructor and the assignment operator, but we don't
113
+    // implement them. This way, if someone tries to copy/assign our instance,
114
+    // he will get an error at compile time.
115
+    InterruptManager(const InterruptManager&);
116
+    InterruptManager& operator =(const InterruptManager&);
117
+
118
+    template<typename T>
119
+    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
120
+        int irq_pos = get_irq_index(irq);
121
+        bool change = must_replace_vector(irq);
122
+
123
+        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
124
+        if (change)
125
+            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
126
+        return pf;
127
+    }
128
+
129
+    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
130
+    bool must_replace_vector(IRQn_Type irq);
131
+    int get_irq_index(IRQn_Type irq);
132
+    void irq_helper();
133
+    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
134
+    static void static_irq_helper();
135
+
136
+    CallChain* _chains[NVIC_NUM_VECTORS];
137
+    static InterruptManager* _instance;
138
+};
139
+
140
+} // namespace mbed
141
+
142
+#endif
143
+

+ 103
- 0
lib/mbed/LocalFileSystem.h View File

@@ -0,0 +1,103 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_LOCALFILESYSTEM_H
17
+#define MBED_LOCALFILESYSTEM_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_LOCALFILESYSTEM
22
+
23
+#include "FileSystemLike.h"
24
+
25
+namespace mbed {
26
+
27
+FILEHANDLE local_file_open(const char* name, int flags);
28
+
29
+class LocalFileHandle : public FileHandle {
30
+
31
+public:
32
+    LocalFileHandle(FILEHANDLE fh);
33
+
34
+    virtual int close();
35
+
36
+    virtual ssize_t write(const void *buffer, size_t length);
37
+
38
+    virtual ssize_t read(void *buffer, size_t length);
39
+
40
+    virtual int isatty();
41
+
42
+    virtual off_t lseek(off_t position, int whence);
43
+
44
+    virtual int fsync();
45
+
46
+    virtual off_t flen();
47
+
48
+protected:
49
+    FILEHANDLE _fh;
50
+    int pos;
51
+};
52
+
53
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
54
+ *
55
+ *  This allows programs to read and write files on the same disk drive that is used to program the
56
+ *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
57
+ *  read and write files.
58
+ *
59
+ * Example:
60
+ * @code
61
+ * #include "mbed.h"
62
+ *
63
+ * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
64
+ *
65
+ * int main() {
66
+ *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
67
+ *     fprintf(fp, "Hello World!");
68
+ *     fclose(fp);
69
+ *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
70
+ *
71
+ *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
72
+ *     struct dirent *p;
73
+ *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
74
+ *       printf("%s\n", p->d_name);              // to stdout.
75
+ *     }
76
+ *     closedir(d);
77
+ * }
78
+ * @endcode
79
+ *
80
+ * @note
81
+ *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
82
+ *  on the Host computer. This means it is no longer accessible from the Host Computer.
83
+ *
84
+ *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
85
+ *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
86
+ */
87
+class LocalFileSystem : public FileSystemLike {
88
+
89
+public:
90
+    LocalFileSystem(const char* n) : FileSystemLike(n) {
91
+
92
+    }
93
+
94
+    virtual FileHandle *open(const char* name, int flags);
95
+    virtual int remove(const char *filename);
96
+    virtual DirHandle *opendir(const char *name);
97
+};
98
+
99
+} // namespace mbed
100
+
101
+#endif
102
+
103
+#endif

+ 44
- 0
lib/mbed/LowPowerTicker.h View File

@@ -0,0 +1,44 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_LOWPOWERTICKER_H
17
+#define MBED_LOWPOWERTICKER_H
18
+
19
+#include "platform.h"
20
+#include "Ticker.h"
21
+
22
+#if DEVICE_LOWPOWERTIMER
23
+
24
+#include "lp_ticker_api.h"
25
+
26
+namespace mbed {
27
+
28
+/** Low Power Ticker
29
+ */
30
+class LowPowerTicker : public Ticker {
31
+
32
+public:
33
+    LowPowerTicker() : Ticker(get_lp_ticker_data()) {
34
+    }
35
+
36
+    virtual ~LowPowerTicker() {
37
+    }
38
+};
39
+
40
+} // namespace mbed
41
+
42
+#endif
43
+
44
+#endif

+ 42
- 0
lib/mbed/LowPowerTimeout.h View File

@@ -0,0 +1,42 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_LOWPOWERTIMEOUT_H
17
+#define MBED_LOWPOWERTIMEOUT_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_LOWPOWERTIMER
22
+
23
+#include "lp_ticker_api.h"
24
+#include "LowPowerTicker.h"
25
+
26
+namespace mbed {
27
+
28
+/** Low Power Timout
29
+ */
30
+class LowPowerTimeout : public LowPowerTicker {
31
+
32
+private:
33
+    virtual void handler(void) {
34
+        _function.call();
35
+    }
36
+};
37
+
38
+}
39
+
40
+#endif
41
+
42
+#endif

+ 42
- 0
lib/mbed/LowPowerTimer.h View File

@@ -0,0 +1,42 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_LOWPOWERTIMER_H
17
+#define MBED_LOWPOWERTIMER_H
18
+
19
+#include "platform.h"
20
+#include "Timer.h"
21
+
22
+#if DEVICE_LOWPOWERTIMER
23
+
24
+#include "lp_ticker_api.h"
25
+
26
+namespace mbed {
27
+
28
+/** Low power timer
29
+ */
30
+class LowPowerTimer : public Timer {
31
+
32
+public:
33
+    LowPowerTimer() : Timer(get_lp_ticker_data()) {
34
+    }
35
+
36
+};
37
+
38
+} // namespace mbed
39
+
40
+#endif
41
+
42
+#endif

+ 93
- 0
lib/mbed/PortIn.h View File

@@ -0,0 +1,93 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PORTIN_H
17
+#define MBED_PORTIN_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_PORTIN
22
+
23
+#include "port_api.h"
24
+
25
+namespace mbed {
26
+
27
+/** A multiple pin digital input
28
+ *
29
+ *  Example:
30
+ * @code
31
+ * // Switch on an LED if any of mbed pins 21-26 is high
32
+ *
33
+ * #include "mbed.h"
34
+ *
35
+ * PortIn     p(Port2, 0x0000003F);   // p21-p26
36
+ * DigitalOut ind(LED4);
37
+ *
38
+ * int main() {
39
+ *     while(1) {
40
+ *         int pins = p.read();
41
+ *         if(pins) {
42
+ *             ind = 1;
43
+ *         } else {
44
+ *             ind = 0;
45
+ *         }
46
+ *     }
47
+ * }
48
+ * @endcode
49
+ */
50
+class PortIn {
51
+public:
52
+
53
+    /** Create an PortIn, connected to the specified port
54
+     *
55
+     *  @param port Port to connect to (Port0-Port5)
56
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
57
+        */
58
+    PortIn(PortName port, int mask = 0xFFFFFFFF) {
59
+        port_init(&_port, port, mask, PIN_INPUT);
60
+    }
61
+
62
+    /** Read the value currently output on the port
63
+     *
64
+     *  @returns
65
+     *    An integer with each bit corresponding to associated port pin setting
66
+     */
67
+    int read() {
68
+        return port_read(&_port);
69
+    }
70
+
71
+    /** Set the input pin mode
72
+     *
73
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
74
+     */
75
+    void mode(PinMode mode) {
76
+        port_mode(&_port, mode);
77
+    }
78
+
79
+    /** A shorthand for read()
80
+     */
81
+    operator int() {
82
+        return read();
83
+    }
84
+
85
+private:
86
+    port_t _port;
87
+};
88
+
89
+} // namespace mbed
90
+
91
+#endif
92
+
93
+#endif

+ 104
- 0
lib/mbed/PortInOut.h View File

@@ -0,0 +1,104 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PORTINOUT_H
17
+#define MBED_PORTINOUT_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_PORTINOUT
22
+
23
+#include "port_api.h"
24
+
25
+namespace mbed {
26
+
27
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
28
+ */
29
+class PortInOut {
30
+public:
31
+
32
+    /** Create an PortInOut, connected to the specified port
33
+     *
34
+     *  @param port Port to connect to (Port0-Port5)
35
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
36
+     */
37
+    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
38
+        port_init(&_port, port, mask, PIN_INPUT);
39
+    }
40
+
41
+    /** Write the value to the output port
42
+     *
43
+     *  @param value An integer specifying a bit to write for every corresponding port pin
44
+     */
45
+    void write(int value) {
46
+        port_write(&_port, value);
47
+    }
48
+
49
+    /** Read the value currently output on the port
50
+     *
51
+     *  @returns
52
+     *    An integer with each bit corresponding to associated port pin setting
53
+     */
54
+    int read() {
55
+        return port_read(&_port);
56
+    }
57
+
58
+    /** Set as an output
59
+     */
60
+    void output() {
61
+        port_dir(&_port, PIN_OUTPUT);
62
+    }
63
+
64
+    /** Set as an input
65
+     */
66
+    void input() {
67
+        port_dir(&_port, PIN_INPUT);
68
+    }
69
+
70
+    /** Set the input pin mode
71
+     *
72
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
73
+     */
74
+    void mode(PinMode mode) {
75
+        port_mode(&_port, mode);
76
+    }
77
+
78
+    /** A shorthand for write()
79
+     */
80
+    PortInOut& operator= (int value) {
81
+        write(value);
82
+        return *this;
83
+    }
84
+
85
+    PortInOut& operator= (PortInOut& rhs) {
86
+        write(rhs.read());
87
+        return *this;
88
+    }
89
+
90
+    /** A shorthand for read()
91
+     */
92
+    operator int() {
93
+        return read();
94
+    }
95
+
96
+private:
97
+    port_t _port;
98
+};
99
+
100
+} // namespace mbed
101
+
102
+#endif
103
+
104
+#endif

+ 104
- 0
lib/mbed/PortOut.h View File

@@ -0,0 +1,104 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PORTOUT_H
17
+#define MBED_PORTOUT_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_PORTOUT
22
+
23
+#include "port_api.h"
24
+
25
+namespace mbed {
26
+/** A multiple pin digital out
27
+ *
28
+ * Example:
29
+ * @code
30
+ * // Toggle all four LEDs
31
+ *
32
+ * #include "mbed.h"
33
+ *
34
+ * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
35
+ * #define LED_MASK 0x00B40000
36
+ *
37
+ * PortOut ledport(Port1, LED_MASK);
38
+ *
39
+ * int main() {
40
+ *     while(1) {
41
+ *         ledport = LED_MASK;
42
+ *         wait(1);
43
+ *         ledport = 0;
44
+ *         wait(1);
45
+ *     }
46
+ * }
47
+ * @endcode
48
+ */
49
+class PortOut {
50
+public:
51
+
52
+    /** Create an PortOut, connected to the specified port
53
+     *
54
+     *  @param port Port to connect to (Port0-Port5)
55
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
56
+     */
57
+    PortOut(PortName port, int mask = 0xFFFFFFFF) {
58
+        port_init(&_port, port, mask, PIN_OUTPUT);
59
+    }
60
+
61
+    /** Write the value to the output port
62
+     *
63
+     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
64
+     */
65
+    void write(int value) {
66
+        port_write(&_port, value);
67
+    }
68
+
69
+    /** Read the value currently output on the port
70
+     *
71
+     *  @returns
72
+     *    An integer with each bit corresponding to associated PortOut pin setting
73
+     */
74
+    int read() {
75
+        return port_read(&_port);
76
+    }
77
+
78
+    /** A shorthand for write()
79
+     */
80
+    PortOut& operator= (int value) {
81
+        write(value);
82
+        return *this;
83
+    }
84
+
85
+    PortOut& operator= (PortOut& rhs) {
86
+        write(rhs.read());
87
+        return *this;
88
+    }
89
+
90
+    /** A shorthand for read()
91
+     */
92
+    operator int() {
93
+        return read();
94
+    }
95
+
96
+private:
97
+    port_t _port;
98
+};
99
+
100
+} // namespace mbed
101
+
102
+#endif
103
+
104
+#endif

+ 158
- 0
lib/mbed/PwmOut.h View File

@@ -0,0 +1,158 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PWMOUT_H
17
+#define MBED_PWMOUT_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_PWMOUT
22
+#include "pwmout_api.h"
23
+
24
+namespace mbed {
25
+
26
+/** A pulse-width modulation digital output
27
+ *
28
+ * Example
29
+ * @code
30
+ * // Fade a led on.
31
+ * #include "mbed.h"
32
+ *
33
+ * PwmOut led(LED1);
34
+ *
35
+ * int main() {
36
+ *     while(1) {
37
+ *         led = led + 0.01;
38
+ *         wait(0.2);
39
+ *         if(led == 1.0) {
40
+ *             led = 0;
41
+ *         }
42
+ *     }
43
+ * }
44
+ * @endcode
45
+ *
46
+ * @note
47
+ *  On the LPC1768 and LPC2368, the PWMs all share the same
48
+ *  period - if you change the period for one, you change it for all.
49
+ *  Although routines that change the period maintain the duty cycle
50
+ *  for its PWM, all other PWMs will require their duty cycle to be
51
+ *  refreshed.
52
+ */
53
+class PwmOut {
54
+
55
+public:
56
+
57
+    /** Create a PwmOut connected to the specified pin
58
+     *
59
+     *  @param pin PwmOut pin to connect to
60
+     */
61
+    PwmOut(PinName pin) {
62
+        pwmout_init(&_pwm, pin);
63
+    }
64
+
65
+    /** Set the ouput duty-cycle, specified as a percentage (float)
66
+     *
67
+     *  @param value A floating-point value representing the output duty-cycle,
68
+     *    specified as a percentage. The value should lie between
69
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
70
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
71
+     */
72
+    void write(float value) {
73
+        pwmout_write(&_pwm, value);
74
+    }
75
+
76
+    /** Return the current output duty-cycle setting, measured as a percentage (float)
77
+     *
78
+     *  @returns
79
+     *    A floating-point value representing the current duty-cycle being output on the pin,
80
+     *    measured as a percentage. The returned value will lie between
81
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
82
+     *
83
+     *  @note
84
+     *  This value may not match exactly the value set by a previous <write>.
85
+     */
86
+    float read() {
87
+        return pwmout_read(&_pwm);
88
+    }
89
+
90
+    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
91
+     *
92
+     *  @note
93
+     *   The resolution is currently in microseconds; periods smaller than this
94
+     *   will be set to zero.
95
+     */
96
+    void period(float seconds) {
97
+        pwmout_period(&_pwm, seconds);
98
+    }
99
+
100
+    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
101
+     */
102
+    void period_ms(int ms) {
103
+        pwmout_period_ms(&_pwm, ms);
104
+    }
105
+
106
+    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
107
+     */
108
+    void period_us(int us) {
109
+        pwmout_period_us(&_pwm, us);
110
+    }
111
+
112
+    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
113
+     */
114
+    void pulsewidth(float seconds) {
115
+        pwmout_pulsewidth(&_pwm, seconds);
116
+    }
117
+
118
+    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
119
+     */
120
+    void pulsewidth_ms(int ms) {
121
+        pwmout_pulsewidth_ms(&_pwm, ms);
122
+    }
123
+
124
+    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
125
+     */
126
+    void pulsewidth_us(int us) {
127
+        pwmout_pulsewidth_us(&_pwm, us);
128
+    }
129
+
130
+#ifdef MBED_OPERATORS
131
+    /** A operator shorthand for write()
132
+     */
133
+    PwmOut& operator= (float value) {
134
+        write(value);
135
+        return *this;
136
+    }
137
+
138
+    PwmOut& operator= (PwmOut& rhs) {
139
+        write(rhs.read());
140
+        return *this;
141
+    }
142
+
143
+    /** An operator shorthand for read()
144
+     */
145
+    operator float() {
146
+        return read();
147
+    }
148
+#endif
149
+
150
+protected:
151
+    pwmout_t _pwm;
152
+};
153
+
154
+} // namespace mbed
155
+
156
+#endif
157
+
158
+#endif

+ 90
- 0
lib/mbed/RawSerial.h View File

@@ -0,0 +1,90 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_RAW_SERIAL_H
17
+#define MBED_RAW_SERIAL_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_SERIAL
22
+
23
+#include "SerialBase.h"
24
+#include "serial_api.h"
25
+
26
+namespace mbed {
27
+
28
+/** A serial port (UART) for communication with other serial devices
29
+ * This is a variation of the Serial class that doesn't use streams,
30
+ * thus making it safe to use in interrupt handlers with the RTOS.
31
+ *
32
+ * Can be used for Full Duplex communication, or Simplex by specifying
33
+ * one pin as NC (Not Connected)
34
+ *
35
+ * Example:
36
+ * @code
37
+ * // Send a char to the PC
38
+ *
39
+ * #include "mbed.h"
40
+ *
41
+ * RawSerial pc(USBTX, USBRX);
42
+ *
43
+ * int main() {
44
+ *     pc.putc('A');
45
+ * }
46
+ * @endcode
47
+ */
48
+class RawSerial: public SerialBase {
49
+
50
+public:
51
+    /** Create a RawSerial port, connected to the specified transmit and receive pins
52
+     *
53
+     *  @param tx Transmit pin
54
+     *  @param rx Receive pin
55
+     *
56
+     *  @note
57
+     *    Either tx or rx may be specified as NC if unused
58
+     */
59
+    RawSerial(PinName tx, PinName rx);
60
+
61
+    /** Write a char to the serial port
62
+     *
63
+     * @param c The char to write
64
+     *
65
+     * @returns The written char or -1 if an error occured
66
+     */
67
+    int putc(int c);
68
+
69
+    /** Read a char from the serial port
70
+     *
71
+     * @returns The char read from the serial port
72
+     */
73
+    int getc();
74
+
75
+    /** Write a string to the serial port
76
+     *
77
+     * @param str The string to write
78
+     *
79
+     * @returns 0 if the write succeeds, EOF for error
80
+     */
81
+    int puts(const char *str);
82
+
83
+    int printf(const char *format, ...);
84
+};
85
+
86
+} // namespace mbed
87
+
88
+#endif
89
+
90
+#endif

+ 245
- 0
lib/mbed/SPI.h View File

@@ -0,0 +1,245 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_SPI_H
17
+#define MBED_SPI_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_SPI
22
+
23
+#include "spi_api.h"
24
+
25
+#if DEVICE_SPI_ASYNCH
26
+#include "CThunk.h"
27
+#include "dma_api.h"
28
+#include "CircularBuffer.h"
29
+#include "FunctionPointer.h"
30
+#include "Transaction.h"
31
+#endif
32
+
33
+namespace mbed {
34
+
35
+/** A SPI Master, used for communicating with SPI slave devices
36
+ *
37
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
38
+ *
39
+ * Most SPI devices will also require Chip Select and Reset signals. These
40
+ * can be controlled using <DigitalOut> pins
41
+ *
42
+ * Example:
43
+ * @code
44
+ * // Send a byte to a SPI slave, and record the response
45
+ *
46
+ * #include "mbed.h"
47
+ *
48
+ * // hardware ssel (where applicable)
49
+ * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
50
+ *
51
+ * // software ssel
52
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
53
+ * DigitalOut cs(p8); // ssel
54
+ *
55
+ * int main() {
56
+ *     // hardware ssel (where applicable)
57
+ *     //int response = device.write(0xFF);
58
+ *
59
+ *     // software ssel
60
+ *     cs = 0;
61
+ *     int response = device.write(0xFF);
62
+ *     cs = 1;
63
+ * }
64
+ * @endcode
65
+ */
66
+class SPI {
67
+
68
+public:
69
+
70
+    /** Create a SPI master connected to the specified pins
71
+     *
72
+     *  mosi or miso can be specfied as NC if not used
73
+     *
74
+     *  @param mosi SPI Master Out, Slave In pin
75
+     *  @param miso SPI Master In, Slave Out pin
76
+     *  @param sclk SPI Clock pin
77
+     *  @param ssel SPI chip select pin
78
+     */
79
+    SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
80
+
81
+    /** Configure the data transmission format
82
+     *
83
+     *  @param bits Number of bits per SPI frame (4 - 16)
84
+     *  @param mode Clock polarity and phase mode (0 - 3)
85
+     *
86
+     * @code
87
+     * mode | POL PHA
88
+     * -----+--------
89
+     *   0  |  0   0
90
+     *   1  |  0   1
91
+     *   2  |  1   0
92
+     *   3  |  1   1
93
+     * @endcode
94
+     */
95
+    void format(int bits, int mode = 0);
96
+
97
+    /** Set the spi bus clock frequency
98
+     *
99
+     *  @param hz SCLK frequency in hz (default = 1MHz)
100
+     */
101
+    void frequency(int hz = 1000000);
102
+
103
+    /** Write to the SPI Slave and return the response
104
+     *
105
+     *  @param value Data to be sent to the SPI slave
106
+     *
107
+     *  @returns
108
+     *    Response from the SPI slave
109
+    */
110
+    virtual int write(int value);
111
+
112
+#if DEVICE_SPI_ASYNCH
113
+
114
+    /** Start non-blocking SPI transfer using 8bit buffers.
115
+     *
116
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
117
+     *                  the default SPI value is sent
118
+     * @param tx_length The length of TX buffer in bytes
119
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
120
+     *                  received data are ignored
121
+     * @param rx_length The length of RX buffer in bytes
122
+     * @param callback  The event callback function
123
+     * @param event     The logical OR of events to modify. Look at spi hal header file for SPI events.
124
+     * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
125
+     */
126
+    template<typename Type>
127
+    int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
128
+        if (spi_active(&_spi)) {
129
+            return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
130
+        }
131
+        start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
132
+        return 0;
133
+    }
134
+
135
+    /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
136
+     */
137
+    void abort_transfer();
138
+
139
+    /** Clear the transaction buffer
140
+     */
141
+    void clear_transfer_buffer();
142
+
143
+    /** Clear the transaction buffer and abort on-going transfer.
144
+     */
145
+    void abort_all_transfers();
146
+
147
+    /** Configure DMA usage suggestion for non-blocking transfers
148
+     *
149
+     *  @param usage The usage DMA hint for peripheral
150
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
151
+    */
152
+    int set_dma_usage(DMAUsage usage);
153
+
154
+protected:
155
+    /** SPI IRQ handler
156
+     *
157
+    */
158
+    void irq_handler_asynch(void);
159
+
160
+    /** Common transfer method
161
+     *
162
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
163
+     *                  the default SPI value is sent
164
+     * @param tx_length The length of TX buffer in bytes
165
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
166
+     *                  received data are ignored
167
+     * @param rx_length The length of RX buffer in bytes
168
+     * @param bit_width The buffers element width
169
+     * @param callback  The event callback function
170
+     * @param event     The logical OR of events to modify
171
+     * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
172
+    */
173
+    int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
174
+
175
+    /**
176
+     *
177
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
178
+     *                  the default SPI value is sent
179
+     * @param tx_length The length of TX buffer in bytes
180
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
181
+     *                  received data are ignored
182
+     * @param rx_length The length of RX buffer in bytes
183
+     * @param bit_width The buffers element width
184
+     * @param callback  The event callback function
185
+     * @param event     The logical OR of events to modify
186
+     * @return Zero if a transfer was added to the queue, or -1 if the queue is full
187
+    */
188
+    int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
189
+
190
+    /** Configures a callback, spi peripheral and initiate a new transfer
191
+     *
192
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
193
+     *                  the default SPI value is sent
194
+     * @param tx_length The length of TX buffer in bytes
195
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
196
+     *                  received data are ignored
197
+     * @param rx_length The length of RX buffer in bytes
198
+     * @param bit_width The buffers element width
199
+     * @param callback  The event callback function
200
+     * @param event     The logical OR of events to modify
201
+    */
202
+    void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
203
+
204
+#if TRANSACTION_QUEUE_SIZE_SPI
205
+
206
+    /** Start a new transaction
207
+     *
208
+     *  @param data Transaction data
209
+    */
210
+    void start_transaction(transaction_t *data);
211
+
212
+    /** Dequeue a transaction
213
+     *
214
+    */
215
+    void dequeue_transaction();
216
+    static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
217
+#endif
218
+
219
+#endif
220
+
221
+public:
222
+    virtual ~SPI() {
223
+    }
224
+
225
+protected:
226
+    spi_t _spi;
227
+
228
+#if DEVICE_SPI_ASYNCH
229
+    CThunk<SPI> _irq;
230
+    event_callback_t _callback;
231
+    DMAUsage _usage;
232
+#endif
233
+
234
+    void aquire(void);
235
+    static SPI *_owner;
236
+    int _bits;
237
+    int _mode;
238
+    int _hz;
239
+};
240
+
241
+} // namespace mbed
242
+
243
+#endif
244
+
245
+#endif

+ 122
- 0
lib/mbed/SPISlave.h View File

@@ -0,0 +1,122 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_SPISLAVE_H
17
+#define MBED_SPISLAVE_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_SPISLAVE
22
+
23
+#include "spi_api.h"
24
+
25
+namespace mbed {
26
+
27
+/** A SPI slave, used for communicating with a SPI Master device
28
+ *
29
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
30
+ *
31
+ * Example:
32
+ * @code
33
+ * // Reply to a SPI master as slave
34
+ *
35
+ * #include "mbed.h"
36
+ *
37
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
38
+ *
39
+ * int main() {
40
+ *     device.reply(0x00);              // Prime SPI with first reply
41
+ *     while(1) {
42
+ *         if(device.receive()) {
43
+ *             int v = device.read();   // Read byte from master
44
+ *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
45
+ *             device.reply(v);         // Make this the next reply
46
+ *         }
47
+ *     }
48
+ * }
49
+ * @endcode
50
+ */
51
+class SPISlave {
52
+
53
+public:
54
+
55
+    /** Create a SPI slave connected to the specified pins
56
+     *
57
+     *  mosi or miso can be specfied as NC if not used
58
+     *
59
+     *  @param mosi SPI Master Out, Slave In pin
60
+     *  @param miso SPI Master In, Slave Out pin
61
+     *  @param sclk SPI Clock pin
62
+     *  @param ssel SPI chip select pin
63
+     */
64
+    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
65
+
66
+    /** Configure the data transmission format
67
+     *
68
+     *  @param bits Number of bits per SPI frame (4 - 16)
69
+     *  @param mode Clock polarity and phase mode (0 - 3)
70
+     *
71
+     * @code
72
+     * mode | POL PHA
73
+     * -----+--------
74
+     *   0  |  0   0
75
+     *   1  |  0   1
76
+     *   2  |  1   0
77
+     *   3  |  1   1
78
+     * @endcode
79
+     */
80
+    void format(int bits, int mode = 0);
81
+
82
+    /** Set the spi bus clock frequency
83
+     *
84
+     *  @param hz SCLK frequency in hz (default = 1MHz)
85
+     */
86
+    void frequency(int hz = 1000000);
87
+
88
+    /** Polls the SPI to see if data has been received
89
+     *
90
+     *  @returns
91
+     *    0 if no data,
92
+     *    1 otherwise
93
+     */
94
+    int receive(void);
95
+
96
+    /** Retrieve  data from receive buffer as slave
97
+     *
98
+     *  @returns
99
+     *    the data in the receive buffer
100
+     */
101
+    int read(void);
102
+
103
+    /** Fill the transmission buffer with the value to be written out
104
+     *  as slave on the next received message from the master.
105
+     *
106
+     *  @param value the data to be transmitted next
107
+     */
108
+    void reply(int value);
109
+
110
+protected:
111
+    spi_t _spi;
112
+
113
+    int _bits;
114
+    int _mode;
115
+    int _hz;
116
+};
117
+
118
+} // namespace mbed
119
+
120
+#endif
121
+
122
+#endif

+ 74
- 0
lib/mbed/Serial.h View File

@@ -0,0 +1,74 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_SERIAL_H
17
+#define MBED_SERIAL_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_SERIAL
22
+
23
+#include "Stream.h"
24
+#include "SerialBase.h"
25
+#include "serial_api.h"
26
+
27
+namespace mbed {
28
+
29
+/** A serial port (UART) for communication with other serial devices
30
+ *
31
+ * Can be used for Full Duplex communication, or Simplex by specifying
32
+ * one pin as NC (Not Connected)
33
+ *
34
+ * Example:
35
+ * @code
36
+ * // Print "Hello World" to the PC
37
+ *
38
+ * #include "mbed.h"
39
+ *
40
+ * Serial pc(USBTX, USBRX);
41
+ *
42
+ * int main() {
43
+ *     pc.printf("Hello World\n");
44
+ * }
45
+ * @endcode
46
+ */
47
+class Serial : public SerialBase, public Stream {
48
+
49
+public:
50
+#if DEVICE_SERIAL_ASYNCH
51
+    using SerialBase::read;
52
+    using SerialBase::write;
53
+#endif
54
+
55
+    /** Create a Serial port, connected to the specified transmit and receive pins
56
+     *
57
+     *  @param tx Transmit pin
58
+     *  @param rx Receive pin
59
+     *
60
+     *  @note
61
+     *    Either tx or rx may be specified as NC if unused
62
+     */
63
+    Serial(PinName tx, PinName rx, const char *name=NULL);
64
+
65
+protected:
66
+    virtual int _getc();
67
+    virtual int _putc(int c);
68
+};
69
+
70
+} // namespace mbed
71
+
72
+#endif
73
+
74
+#endif

+ 223
- 0
lib/mbed/SerialBase.h View File

@@ -0,0 +1,223 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_SERIALBASE_H
17
+#define MBED_SERIALBASE_H
18
+
19
+#include "platform.h"
20
+
21
+#if DEVICE_SERIAL
22
+
23
+#include "Stream.h"
24
+#include "FunctionPointer.h"
25
+#include "serial_api.h"
26
+
27
+#if DEVICE_SERIAL_ASYNCH
28
+#include "CThunk.h"
29
+#include "dma_api.h"
30
+#endif
31
+
32
+namespace mbed {
33
+
34
+/** A base class for serial port implementations
35
+ * Can't be instantiated directly (use Serial or RawSerial)
36
+ */
37
+class SerialBase {
38
+
39
+public:
40
+    /** Set the baud rate of the serial port
41
+     *
42
+     *  @param baudrate The baudrate of the serial port (default = 9600).
43
+     */
44
+    void baud(int baudrate);
45
+
46
+    enum Parity {
47
+        None = 0,
48
+        Odd,
49
+        Even,
50
+        Forced1,
51
+        Forced0
52
+    };
53
+
54
+    enum IrqType {
55
+        RxIrq = 0,
56
+        TxIrq
57
+    };
58
+
59
+    enum Flow {
60
+        Disabled = 0,
61
+        RTS,
62
+        CTS,
63
+        RTSCTS
64
+    };
65
+
66
+    /** Set the transmission format used by the serial port
67
+     *
68
+     *  @param bits The number of bits in a word (5-8; default = 8)
69
+     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
70
+     *  @param stop The number of stop bits (1 or 2; default = 1)
71
+     */
72
+    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
73
+
74
+    /** Determine if there is a character available to read
75
+     *
76
+     *  @returns
77
+     *    1 if there is a character available to read,
78
+     *    0 otherwise
79
+     */
80
+    int readable();
81
+
82
+    /** Determine if there is space available to write a character
83
+     *
84
+     *  @returns
85
+     *    1 if there is space to write a character,
86
+     *    0 otherwise
87
+     */
88
+    int writeable();
89
+
90
+    /** Attach a function to call whenever a serial interrupt is generated
91
+     *
92
+     *  @param fptr A pointer to a void function, or 0 to set as none
93
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
94
+     */
95
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
96
+
97
+    /** Attach a member function to call whenever a serial interrupt is generated
98
+     *
99
+     *  @param tptr pointer to the object to call the member function on
100
+     *  @param mptr pointer to the member function to be called
101
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
102
+     */
103
+    template<typename T>
104
+    void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
105
+        if((mptr != NULL) && (tptr != NULL)) {
106
+            _irq[type].attach(tptr, mptr);
107
+            serial_irq_set(&_serial, (SerialIrq)type, 1);
108
+        } else {
109
+            serial_irq_set(&_serial, (SerialIrq)type, 0);
110
+        }
111
+    }
112
+
113
+    /** Generate a break condition on the serial line
114
+     */
115
+    void send_break();
116
+
117
+#if DEVICE_SERIAL_FC
118
+    /** Set the flow control type on the serial port
119
+     *
120
+     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
121
+     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
122
+     *  @param flow2 the second flow control pin (CTS for RTSCTS)
123
+     */
124
+    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
125
+#endif
126
+
127
+    static void _irq_handler(uint32_t id, SerialIrq irq_type);
128
+
129
+#if DEVICE_SERIAL_ASYNCH
130
+
131
+    /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
132
+     *
133
+     *  @param buffer   The buffer where received data will be stored
134
+     *  @param length   The buffer length in bytes
135
+     *  @param callback The event callback function
136
+     *  @param event    The logical OR of TX events
137
+     */
138
+    int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
139
+
140
+    /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
141
+     *
142
+     *  @param buffer   The buffer where received data will be stored
143
+     *  @param length   The buffer length in bytes
144
+     *  @param callback The event callback function
145
+     *  @param event    The logical OR of TX events
146
+     */
147
+    int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
148
+
149
+    /** Abort the on-going write transfer
150
+     */
151
+    void abort_write();
152
+
153
+    /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
154
+     *
155
+     *  @param buffer     The buffer where received data will be stored
156
+     *  @param length     The buffer length in bytes
157
+     *  @param callback   The event callback function
158
+     *  @param event      The logical OR of RX events
159
+     *  @param char_match The matching character
160
+     */
161
+    int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
162
+
163
+    /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
164
+     *
165
+     *  @param buffer     The buffer where received data will be stored
166
+     *  @param length     The buffer length in bytes
167
+     *  @param callback   The event callback function
168
+     *  @param event      The logical OR of RX events
169
+     *  @param char_match The matching character
170
+     */
171
+    int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
172
+
173
+    /** Abort the on-going read transfer
174
+     */
175
+    void abort_read();
176
+
177
+    /** Configure DMA usage suggestion for non-blocking TX transfers
178
+     *
179
+     *  @param usage The usage DMA hint for peripheral
180
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
181
+     */
182
+    int set_dma_usage_tx(DMAUsage usage);
183
+
184
+    /** Configure DMA usage suggestion for non-blocking RX transfers
185
+     *
186
+     *  @param usage The usage DMA hint for peripheral
187
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
188
+     */
189
+    int set_dma_usage_rx(DMAUsage usage);
190
+
191
+protected:
192
+    void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
193
+    void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
194
+    void interrupt_handler_asynch(void);
195
+#endif
196
+
197
+protected:
198
+    SerialBase(PinName tx, PinName rx);
199
+    virtual ~SerialBase() {
200
+    }
201
+
202
+    int _base_getc();
203
+    int _base_putc(int c);
204
+
205
+#if DEVICE_SERIAL_ASYNCH
206
+    CThunk<SerialBase> _thunk_irq;
207
+    event_callback_t _tx_callback;
208
+    event_callback_t _rx_callback;
209
+    DMAUsage _tx_usage;
210
+    DMAUsage _rx_usage;
211
+#endif
212
+
213
+    serial_t        _serial;
214
+    FunctionPointer _irq[2];
215
+    int             _baud;
216
+
217
+};
218
+
219
+} // namespace mbed
220
+
221
+#endif
222
+
223
+#endif

+ 68
- 0
lib/mbed/Stream.h View File

@@ -0,0 +1,68 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_STREAM_H
17
+#define MBED_STREAM_H
18
+
19
+#include "platform.h"
20
+#include "FileLike.h"
21
+#include <cstdarg>
22
+
23
+namespace mbed {
24
+
25
+extern void mbed_set_unbuffered_stream(FILE *_file);
26
+extern int mbed_getc(FILE *_file);
27
+extern char* mbed_gets(char *s, int size, FILE *_file);
28
+
29
+class Stream : public FileLike {
30
+
31
+public:
32
+    Stream(const char *name=NULL);
33
+    virtual ~Stream();
34
+
35
+    int putc(int c);
36
+    int puts(const char *s);
37
+    int getc();
38
+    char *gets(char *s, int size);
39
+    int printf(const char* format, ...);
40
+    int scanf(const char* format, ...);
41
+    int vprintf(const char* format, std::va_list args);
42
+    int vscanf(const char* format, std::va_list args);
43
+
44
+    operator std::FILE*() {return _file;}
45
+
46
+protected:
47
+    virtual int close();
48
+    virtual ssize_t write(const void* buffer, size_t length);
49
+    virtual ssize_t read(void* buffer, size_t length);
50
+    virtual off_t lseek(off_t offset, int whence);
51
+    virtual int isatty();
52
+    virtual int fsync();
53
+    virtual off_t flen();
54
+
55
+    virtual int _putc(int c) = 0;
56
+    virtual int _getc() = 0;
57
+
58
+    std::FILE *_file;
59
+
60
+    /* disallow copy constructor and assignment operators */
61
+private:
62
+    Stream(const Stream&);
63
+    Stream & operator = (const Stream&);
64
+};
65
+
66
+} // namespace mbed
67
+
68
+#endif

+ 1035
- 0
lib/mbed/TARGET_LPC1768/LPC17xx.h
File diff suppressed because it is too large
View File


+ 111
- 0
lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PeripheralNames.h View File

@@ -0,0 +1,111 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PERIPHERALNAMES_H
17
+#define MBED_PERIPHERALNAMES_H
18
+
19
+#include "cmsis.h"
20
+#include "PinNames.h"
21
+
22
+#ifdef __cplusplus
23
+extern "C" {
24
+#endif
25
+
26
+typedef enum {
27
+    UART_0 = (int)LPC_UART0_BASE,
28
+    UART_1 = (int)LPC_UART1_BASE,
29
+    UART_2 = (int)LPC_UART2_BASE,
30
+    UART_3 = (int)LPC_UART3_BASE
31
+} UARTName;
32
+
33
+typedef enum {
34
+    ADC0_0 = 0,
35
+    ADC0_1,
36
+    ADC0_2,
37
+    ADC0_3,
38
+    ADC0_4,
39
+    ADC0_5,
40
+    ADC0_6,
41
+    ADC0_7
42
+} ADCName;
43
+
44
+typedef enum {
45
+    DAC_0 = 0
46
+} DACName;
47
+
48
+typedef enum {
49
+    SPI_0 = (int)LPC_SSP0_BASE,
50
+    SPI_1 = (int)LPC_SSP1_BASE
51
+} SPIName;
52
+
53
+typedef enum {
54
+    I2C_0 = (int)LPC_I2C0_BASE,
55
+    I2C_1 = (int)LPC_I2C1_BASE,
56
+    I2C_2 = (int)LPC_I2C2_BASE
57
+} I2CName;
58
+
59
+typedef enum {
60
+    PWM_1 = 1,
61
+    PWM_2,
62
+    PWM_3,
63
+    PWM_4,
64
+    PWM_5,
65
+    PWM_6
66
+} PWMName;
67
+
68
+typedef enum {
69
+     CAN_1 = (int)LPC_CAN1_BASE,
70
+     CAN_2 = (int)LPC_CAN2_BASE
71
+} CANName;
72
+
73
+#define STDIO_UART_TX     USBTX
74
+#define STDIO_UART_RX     USBRX
75
+#define STDIO_UART        UART_0
76
+
77
+// Default peripherals
78
+#define MBED_SPI0         p5, p6, p7, p8
79
+#define MBED_SPI1         p11, p12, p13, p14
80
+
81
+#define MBED_UART0        p9, p10
82
+#define MBED_UART1        p13, p14
83
+#define MBED_UART2        p28, p27
84
+#define MBED_UARTUSB      USBTX, USBRX
85
+
86
+#define MBED_I2C0         p28, p27
87
+#define MBED_I2C1         p9, p10
88
+
89
+#define MBED_CAN0         p30, p29
90
+
91
+#define MBED_ANALOGOUT0   p18
92
+
93
+#define MBED_ANALOGIN0    p15
94
+#define MBED_ANALOGIN1    p16
95
+#define MBED_ANALOGIN2    p17
96
+#define MBED_ANALOGIN3    p18
97
+#define MBED_ANALOGIN4    p19
98
+#define MBED_ANALOGIN5    p20
99
+
100
+#define MBED_PWMOUT0      p26
101
+#define MBED_PWMOUT1      p25
102
+#define MBED_PWMOUT2      p24
103
+#define MBED_PWMOUT3      p23
104
+#define MBED_PWMOUT4      p22
105
+#define MBED_PWMOUT5      p21
106
+
107
+#ifdef __cplusplus
108
+}
109
+#endif
110
+
111
+#endif

+ 34
- 0
lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/PortNames.h View File

@@ -0,0 +1,34 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PORTNAMES_H
17
+#define MBED_PORTNAMES_H
18
+
19
+#ifdef __cplusplus
20
+extern "C" {
21
+#endif
22
+
23
+typedef enum {
24
+    Port0 = 0,
25
+    Port1 = 1,
26
+    Port2 = 2,
27
+    Port3 = 3,
28
+    Port4 = 4
29
+} PortName;
30
+
31
+#ifdef __cplusplus
32
+}
33
+#endif
34
+#endif

+ 139
- 0
lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/PinNames.h View File

@@ -0,0 +1,139 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PINNAMES_H
17
+#define MBED_PINNAMES_H
18
+
19
+#include "cmsis.h"
20
+
21
+#ifdef __cplusplus
22
+extern "C" {
23
+#endif
24
+
25
+typedef enum {
26
+    PIN_INPUT,
27
+    PIN_OUTPUT
28
+} PinDirection;
29
+
30
+#define PORT_SHIFT  5
31
+
32
+typedef enum {
33
+    // LPC Pin Names
34
+    P0_0 = LPC_GPIO0_BASE,
35
+          P0_1, P0_2, P0_3, P0_4, P0_5, P0_6, P0_7, P0_8, P0_9, P0_10, P0_11, P0_12, P0_13, P0_14, P0_15, P0_16, P0_17, P0_18, P0_19, P0_20, P0_21, P0_22, P0_23, P0_24, P0_25, P0_26, P0_27, P0_28, P0_29, P0_30, P0_31,
36
+    P1_0, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15, P1_16, P1_17, P1_18, P1_19, P1_20, P1_21, P1_22, P1_23, P1_24, P1_25, P1_26, P1_27, P1_28, P1_29, P1_30, P1_31,
37
+    P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15, P2_16, P2_17, P2_18, P2_19, P2_20, P2_21, P2_22, P2_23, P2_24, P2_25, P2_26, P2_27, P2_28, P2_29, P2_30, P2_31,
38
+    P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15, P3_16, P3_17, P3_18, P3_19, P3_20, P3_21, P3_22, P3_23, P3_24, P3_25, P3_26, P3_27, P3_28, P3_29, P3_30, P3_31,
39
+    P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15, P4_16, P4_17, P4_18, P4_19, P4_20, P4_21, P4_22, P4_23, P4_24, P4_25, P4_26, P4_27, P4_28, P4_29, P4_30, P4_31,
40
+
41
+    // mbed DIP Pin Names
42
+    p5 = P0_9,
43
+    p6 = P0_8,
44
+    p7 = P0_7,
45
+    p8 = P0_6,
46
+    p9 = P0_0,
47
+    p10 = P0_1,
48
+    p11 = P0_18,
49
+    p12 = P0_17,
50
+    p13 = P0_15,
51
+    p14 = P0_16,
52
+    p15 = P0_23,
53
+    p16 = P0_24,
54
+    p17 = P0_25,
55
+    p18 = P0_26,
56
+    p19 = P1_30,
57
+    p20 = P1_31,
58
+    p21 = P2_5,
59
+    p22 = P2_4,
60
+    p23 = P2_3,
61
+    p24 = P2_2,
62
+    p25 = P2_1,
63
+    p26 = P2_0,
64
+    p27 = P0_11,
65
+    p28 = P0_10,
66
+    p29 = P0_5,
67
+    p30 = P0_4,
68
+
69
+    // Other mbed Pin Names
70
+#ifdef MCB1700
71
+    LED1 = P1_28,
72
+    LED2 = P1_29,
73
+    LED3 = P1_31,
74
+    LED4 = P2_2,
75
+#else
76
+    LED1 = P1_18,
77
+    LED2 = P1_20,
78
+    LED3 = P1_21,
79
+    LED4 = P1_23,
80
+#endif
81
+    USBTX = P0_2,
82
+    USBRX = P0_3,
83
+
84
+    // Arch Pro Pin Names
85
+    D0 = P4_29,
86
+    D1 = P4_28,
87
+    D2 = P0_4,
88
+    D3 = P0_5,
89
+    D4 = P2_2,
90
+    D5 = P2_3,
91
+    D6 = P2_4,
92
+    D7 = P2_5,
93
+    D8 = P0_0,
94
+    D9 = P0_1,
95
+    D10 = P0_6,
96
+    D11 = P0_9,
97
+    D12 = P0_8,
98
+    D13 = P0_7,
99
+    D14 = P0_27,
100
+    D15 = P0_28,
101
+
102
+    A0 = P0_23,
103
+    A1 = P0_24,
104
+    A2 = P0_25,
105
+    A3 = P0_26,
106
+    A4 = P1_30,
107
+    A5 = P1_31,
108
+
109
+    I2C_SCL = D15,
110
+    I2C_SDA = D14,
111
+
112
+    // Not connected
113
+    NC = (int)0xFFFFFFFF
114
+} PinName;
115
+
116
+typedef enum {
117
+    PullUp = 0,
118
+    PullDown = 3,
119
+    PullNone = 2,
120
+    Repeater = 1,
121
+    OpenDrain = 4,
122
+    PullDefault = PullDown
123
+} PinMode;
124
+
125
+// version of PINCON_TypeDef using register arrays
126
+typedef struct {
127
+  __IO uint32_t PINSEL[11];
128
+       uint32_t RESERVED0[5];
129
+  __IO uint32_t PINMODE[10];
130
+  __IO uint32_t PINMODE_OD[5];
131
+} PINCONARRAY_TypeDef;
132
+
133
+#define PINCONARRAY ((PINCONARRAY_TypeDef *)LPC_PINCON_BASE)
134
+
135
+#ifdef __cplusplus
136
+}
137
+#endif
138
+
139
+#endif

+ 60
- 0
lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/device.h View File

@@ -0,0 +1,60 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_DEVICE_H
17
+#define MBED_DEVICE_H
18
+
19
+#define DEVICE_PORTIN           1
20
+#define DEVICE_PORTOUT          1
21
+#define DEVICE_PORTINOUT        1
22
+
23
+#define DEVICE_INTERRUPTIN      1
24
+
25
+#define DEVICE_ANALOGIN         1
26
+#define DEVICE_ANALOGOUT        1
27
+
28
+#define DEVICE_SERIAL           1
29
+#define DEVICE_SERIAL_FC        1
30
+
31
+#define DEVICE_I2C              1
32
+#define DEVICE_I2CSLAVE         1
33
+
34
+#define DEVICE_SPI              1
35
+#define DEVICE_SPISLAVE         1
36
+
37
+#define DEVICE_CAN              1
38
+
39
+#define DEVICE_RTC              1
40
+
41
+#define DEVICE_ETHERNET         1
42
+
43
+#define DEVICE_PWMOUT           1
44
+
45
+#define DEVICE_SEMIHOST         1
46
+#define DEVICE_LOCALFILESYSTEM  1
47
+#define DEVICE_ID_LENGTH       32
48
+#define DEVICE_MAC_OFFSET      20
49
+
50
+#define DEVICE_SLEEP            1
51
+
52
+#define DEVICE_DEBUG_AWARENESS  1
53
+
54
+#define DEVICE_STDIO_MESSAGES   1
55
+
56
+#define DEVICE_ERROR_PATTERN    1
57
+
58
+#include "objects.h"
59
+
60
+#endif

+ 8
- 0
lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/TARGET_MBED_LPC1768/reserved_pins.h View File

@@ -0,0 +1,8 @@
1
+// List of reserved pins for MBED LPC1768
2
+
3
+#ifndef RESERVED_PINS_H
4
+#define RESERVED_PINS_H
5
+
6
+#define TARGET_RESERVED_PINS {}
7
+
8
+#endif

+ 56
- 0
lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/gpio_object.h View File

@@ -0,0 +1,56 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_GPIO_OBJECT_H
17
+#define MBED_GPIO_OBJECT_H
18
+
19
+#include "mbed_assert.h"
20
+
21
+#ifdef __cplusplus
22
+extern "C" {
23
+#endif
24
+
25
+typedef struct {
26
+    PinName  pin;
27
+    uint32_t mask;
28
+
29
+    __IO uint32_t *reg_dir;
30
+    __IO uint32_t *reg_set;
31
+    __IO uint32_t *reg_clr;
32
+    __I  uint32_t *reg_in;
33
+} gpio_t;
34
+
35
+static inline void gpio_write(gpio_t *obj, int value) {
36
+    MBED_ASSERT(obj->pin != (PinName)NC);
37
+    if (value)
38
+        *obj->reg_set = obj->mask;
39
+    else
40
+        *obj->reg_clr = obj->mask;
41
+}
42
+
43
+static inline int gpio_read(gpio_t *obj) {
44
+    MBED_ASSERT(obj->pin != (PinName)NC);
45
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
46
+}
47
+
48
+static inline int gpio_is_connected(const gpio_t *obj) {
49
+    return obj->pin != (PinName)NC;
50
+}
51
+
52
+#ifdef __cplusplus
53
+}
54
+#endif
55
+
56
+#endif

+ 78
- 0
lib/mbed/TARGET_LPC1768/TARGET_NXP/TARGET_LPC176X/objects.h View File

@@ -0,0 +1,78 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_OBJECTS_H
17
+#define MBED_OBJECTS_H
18
+
19
+#include "cmsis.h"
20
+#include "PortNames.h"
21
+#include "PeripheralNames.h"
22
+#include "PinNames.h"
23
+#include "gpio_object.h"
24
+
25
+#ifdef __cplusplus
26
+extern "C" {
27
+#endif
28
+
29
+struct gpio_irq_s {
30
+    uint32_t port;
31
+    uint32_t pin;
32
+    uint32_t ch;
33
+};
34
+
35
+struct port_s {
36
+    __IO uint32_t *reg_dir;
37
+    __IO uint32_t *reg_out;
38
+    __I  uint32_t *reg_in;
39
+    PortName port;
40
+    uint32_t mask;
41
+};
42
+
43
+struct pwmout_s {
44
+    __IO uint32_t *MR;
45
+    PWMName pwm;
46
+};
47
+
48
+struct serial_s {
49
+    LPC_UART_TypeDef *uart;
50
+    int index;
51
+};
52
+
53
+struct analogin_s {
54
+    ADCName adc;
55
+};
56
+
57
+struct dac_s {
58
+    DACName dac;
59
+};
60
+
61
+struct can_s {
62
+    LPC_CAN_TypeDef *dev;
63
+    int index;
64
+};
65
+
66
+struct i2c_s {
67
+    LPC_I2C_TypeDef *i2c;
68
+};
69
+
70
+struct spi_s {
71
+    LPC_SSP_TypeDef *spi;
72
+};
73
+
74
+#ifdef __cplusplus
75
+}
76
+#endif
77
+
78
+#endif

+ 172
- 0
lib/mbed/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/LPC1768.ld View File

@@ -0,0 +1,172 @@
1
+/* Linker script for mbed LPC1768 */
2
+
3
+/* Linker script to configure memory regions. */
4
+MEMORY
5
+{
6
+  FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
7
+  RAM (rwx) : ORIGIN = 0x100000C8, LENGTH = (32K - 0xC8)
8
+
9
+  USB_RAM(rwx) : ORIGIN = 0x2007C000, LENGTH = 16K
10
+  ETH_RAM(rwx) : ORIGIN = 0x20080000, LENGTH = 16K
11
+}
12
+
13
+/* Linker script to place sections and symbol values. Should be used together
14
+ * with other linker script that defines memory regions FLASH and RAM.
15
+ * It references following symbols, which must be defined in code:
16
+ *   Reset_Handler : Entry of reset handler
17
+ * 
18
+ * It defines following symbols, which code can use without definition:
19
+ *   __exidx_start
20
+ *   __exidx_end
21
+ *   __etext
22
+ *   __data_start__
23
+ *   __preinit_array_start
24
+ *   __preinit_array_end
25
+ *   __init_array_start
26
+ *   __init_array_end
27
+ *   __fini_array_start
28
+ *   __fini_array_end
29
+ *   __data_end__
30
+ *   __bss_start__
31
+ *   __bss_end__
32
+ *   __end__
33
+ *   end
34
+ *   __HeapLimit
35
+ *   __StackLimit
36
+ *   __StackTop
37
+ *   __stack
38
+ */
39
+ENTRY(Reset_Handler)
40
+
41
+SECTIONS
42
+{
43
+    .text :
44
+    {
45
+        KEEP(*(.isr_vector))
46
+        *(.text*)
47
+
48
+        KEEP(*(.init))
49
+        KEEP(*(.fini))
50
+
51
+        /* .ctors */
52
+        *crtbegin.o(.ctors)
53
+        *crtbegin?.o(.ctors)
54
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
55
+        *(SORT(.ctors.*))
56
+        *(.ctors)
57
+
58
+        /* .dtors */
59
+        *crtbegin.o(.dtors)
60
+        *crtbegin?.o(.dtors)
61
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
62
+        *(SORT(.dtors.*))
63
+        *(.dtors)
64
+
65
+        *(.rodata*)
66
+
67
+        KEEP(*(.eh_frame*))
68
+    } > FLASH
69
+
70
+    .ARM.extab : 
71
+    {
72
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
73
+    } > FLASH
74
+
75
+    __exidx_start = .;
76
+    .ARM.exidx :
77
+    {
78
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
79
+    } > FLASH
80
+    __exidx_end = .;
81
+
82
+    __etext = .;
83
+        
84
+    .data : AT (__etext)
85
+    {
86
+        __data_start__ = .;
87
+        Image$$RW_IRAM1$$Base = .;
88
+        *(vtable)
89
+        *(.data*)
90
+
91
+        . = ALIGN(4);
92
+        /* preinit data */
93
+        PROVIDE (__preinit_array_start = .);
94
+        KEEP(*(.preinit_array))
95
+        PROVIDE (__preinit_array_end = .);
96
+
97
+        . = ALIGN(4);
98
+        /* init data */
99
+        PROVIDE (__init_array_start = .);
100
+        KEEP(*(SORT(.init_array.*)))
101
+        KEEP(*(.init_array))
102
+        PROVIDE (__init_array_end = .);
103
+
104
+
105
+        . = ALIGN(4);
106
+        /* finit data */
107
+        PROVIDE (__fini_array_start = .);
108
+        KEEP(*(SORT(.fini_array.*)))
109
+        KEEP(*(.fini_array))
110
+        PROVIDE (__fini_array_end = .);
111
+
112
+        . = ALIGN(4);
113
+        /* All data end */
114
+        __data_end__ = .;
115
+
116
+    } > RAM
117
+
118
+    
119
+    .bss :
120
+    {
121
+        __bss_start__ = .;
122
+        *(.bss*)
123
+        *(COMMON)
124
+        __bss_end__ = .;
125
+        Image$$RW_IRAM1$$ZI$$Limit = . ;
126
+    } > RAM
127
+
128
+    
129
+    .heap :
130
+    {
131
+        __end__ = .;
132
+        end = __end__;
133
+        *(.heap*)
134
+        __HeapLimit = .;
135
+    } > RAM
136
+
137
+    /* .stack_dummy section doesn't contains any symbols. It is only
138
+     * used for linker to calculate size of stack sections, and assign
139
+     * values to stack symbols later */
140
+    .stack_dummy :
141
+    {
142
+        *(.stack)
143
+    } > RAM
144
+
145
+    /* Set stack top to end of RAM, and stack limit move down by
146
+     * size of stack_dummy section */
147
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
148
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
149
+    PROVIDE(__stack = __StackTop);
150
+    
151
+    /* Check if data + heap + stack exceeds RAM limit */
152
+    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
153
+
154
+
155
+    /* Code can explicitly ask for data to be 
156
+       placed in these higher RAM banks where
157
+       they will be left uninitialized. 
158
+    */
159
+    .AHBSRAM0 (NOLOAD):
160
+    {
161
+        Image$$RW_IRAM2$$Base = . ;
162
+        *(AHBSRAM0)
163
+        Image$$RW_IRAM2$$ZI$$Limit = .;
164
+    } > USB_RAM
165
+
166
+    .AHBSRAM1 (NOLOAD):
167
+    {
168
+        Image$$RW_IRAM3$$Base = . ;
169
+        *(AHBSRAM1)
170
+        Image$$RW_IRAM3$$ZI$$Limit = .;
171
+    } > ETH_RAM
172
+}

BIN
lib/mbed/TARGET_LPC1768/TOOLCHAIN_GCC_ARM/libmbed.a View File


+ 136
- 0
lib/mbed/TARGET_LPC1768/arm_common_tables.h View File

@@ -0,0 +1,136 @@
1
+/* ----------------------------------------------------------------------
2
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
3
+*
4
+* $Date:        19. March 2015
5
+* $Revision: 	V.1.4.5
6
+*
7
+* Project: 	    CMSIS DSP Library
8
+* Title:	    arm_common_tables.h
9
+*
10
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
11
+*
12
+* Target Processor: Cortex-M4/Cortex-M3
13
+*
14
+* Redistribution and use in source and binary forms, with or without
15
+* modification, are permitted provided that the following conditions
16
+* are met:
17
+*   - Redistributions of source code must retain the above copyright
18
+*     notice, this list of conditions and the following disclaimer.
19
+*   - Redistributions in binary form must reproduce the above copyright
20
+*     notice, this list of conditions and the following disclaimer in
21
+*     the documentation and/or other materials provided with the
22
+*     distribution.
23
+*   - Neither the name of ARM LIMITED nor the names of its contributors
24
+*     may be used to endorse or promote products derived from this
25
+*     software without specific prior written permission.
26
+*
27
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
33
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38
+* POSSIBILITY OF SUCH DAMAGE.
39
+* -------------------------------------------------------------------- */
40
+
41
+#ifndef _ARM_COMMON_TABLES_H
42
+#define _ARM_COMMON_TABLES_H
43
+
44
+#include "arm_math.h"
45
+
46
+extern const uint16_t armBitRevTable[1024];
47
+extern const q15_t armRecipTableQ15[64];
48
+extern const q31_t armRecipTableQ31[64];
49
+//extern const q31_t realCoefAQ31[1024];
50
+//extern const q31_t realCoefBQ31[1024];
51
+extern const float32_t twiddleCoef_16[32];
52
+extern const float32_t twiddleCoef_32[64];
53
+extern const float32_t twiddleCoef_64[128];
54
+extern const float32_t twiddleCoef_128[256];
55
+extern const float32_t twiddleCoef_256[512];
56
+extern const float32_t twiddleCoef_512[1024];
57
+extern const float32_t twiddleCoef_1024[2048];
58
+extern const float32_t twiddleCoef_2048[4096];
59
+extern const float32_t twiddleCoef_4096[8192];
60
+#define twiddleCoef twiddleCoef_4096
61
+extern const q31_t twiddleCoef_16_q31[24];
62
+extern const q31_t twiddleCoef_32_q31[48];
63
+extern const q31_t twiddleCoef_64_q31[96];
64
+extern const q31_t twiddleCoef_128_q31[192];
65
+extern const q31_t twiddleCoef_256_q31[384];
66
+extern const q31_t twiddleCoef_512_q31[768];
67
+extern const q31_t twiddleCoef_1024_q31[1536];
68
+extern const q31_t twiddleCoef_2048_q31[3072];
69
+extern const q31_t twiddleCoef_4096_q31[6144];
70
+extern const q15_t twiddleCoef_16_q15[24];
71
+extern const q15_t twiddleCoef_32_q15[48];
72
+extern const q15_t twiddleCoef_64_q15[96];
73
+extern const q15_t twiddleCoef_128_q15[192];
74
+extern const q15_t twiddleCoef_256_q15[384];
75
+extern const q15_t twiddleCoef_512_q15[768];
76
+extern const q15_t twiddleCoef_1024_q15[1536];
77
+extern const q15_t twiddleCoef_2048_q15[3072];
78
+extern const q15_t twiddleCoef_4096_q15[6144];
79
+extern const float32_t twiddleCoef_rfft_32[32];
80
+extern const float32_t twiddleCoef_rfft_64[64];
81
+extern const float32_t twiddleCoef_rfft_128[128];
82
+extern const float32_t twiddleCoef_rfft_256[256];
83
+extern const float32_t twiddleCoef_rfft_512[512];
84
+extern const float32_t twiddleCoef_rfft_1024[1024];
85
+extern const float32_t twiddleCoef_rfft_2048[2048];
86
+extern const float32_t twiddleCoef_rfft_4096[4096];
87
+
88
+
89
+/* floating-point bit reversal tables */
90
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
91
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
92
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
93
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
94
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
95
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
96
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
97
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
98
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
99
+
100
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
101
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
102
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
103
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
104
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
105
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
106
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
107
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
108
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
109
+
110
+/* fixed-point bit reversal tables */
111
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
112
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
113
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
114
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
115
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
116
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
117
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
118
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
119
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
120
+
121
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
122
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
123
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
124
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
125
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
126
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
127
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
128
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
129
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
130
+
131
+/* Tables for Fast Math Sine and Cosine */
132
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
133
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
134
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
135
+
136
+#endif /*  ARM_COMMON_TABLES_H */

+ 79
- 0
lib/mbed/TARGET_LPC1768/arm_const_structs.h View File

@@ -0,0 +1,79 @@
1
+/* ----------------------------------------------------------------------
2
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
3
+*
4
+* $Date:        19. March 2015
5
+* $Revision: 	V.1.4.5
6
+*
7
+* Project: 	    CMSIS DSP Library
8
+* Title:	    arm_const_structs.h
9
+*
10
+* Description:	This file has constant structs that are initialized for
11
+*              user convenience.  For example, some can be given as
12
+*              arguments to the arm_cfft_f32() function.
13
+*
14
+* Target Processor: Cortex-M4/Cortex-M3
15
+*
16
+* Redistribution and use in source and binary forms, with or without
17
+* modification, are permitted provided that the following conditions
18
+* are met:
19
+*   - Redistributions of source code must retain the above copyright
20
+*     notice, this list of conditions and the following disclaimer.
21
+*   - Redistributions in binary form must reproduce the above copyright
22
+*     notice, this list of conditions and the following disclaimer in
23
+*     the documentation and/or other materials provided with the
24
+*     distribution.
25
+*   - Neither the name of ARM LIMITED nor the names of its contributors
26
+*     may be used to endorse or promote products derived from this
27
+*     software without specific prior written permission.
28
+*
29
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
32
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
33
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
34
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
35
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
36
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
39
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
40
+* POSSIBILITY OF SUCH DAMAGE.
41
+* -------------------------------------------------------------------- */
42
+
43
+#ifndef _ARM_CONST_STRUCTS_H
44
+#define _ARM_CONST_STRUCTS_H
45
+
46
+#include "arm_math.h"
47
+#include "arm_common_tables.h"
48
+
49
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
50
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
51
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
52
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
53
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
54
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
55
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
56
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
57
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
58
+
59
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
60
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
61
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
62
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
63
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
64
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
65
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
66
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
67
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
68
+
69
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
70
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
71
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
72
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
73
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
74
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
75
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
76
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
77
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
78
+
79
+#endif

+ 7556
- 0
lib/mbed/TARGET_LPC1768/arm_math.h
File diff suppressed because it is too large
View File


+ 13
- 0
lib/mbed/TARGET_LPC1768/cmsis.h View File

@@ -0,0 +1,13 @@
1
+/* mbed Microcontroller Library - CMSIS
2
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
3
+ * 
4
+ * A generic CMSIS include header, pulling in LPC1768 specifics
5
+ */
6
+
7
+#ifndef MBED_CMSIS_H
8
+#define MBED_CMSIS_H
9
+
10
+#include "LPC17xx.h"
11
+#include "cmsis_nvic.h"
12
+
13
+#endif

+ 51
- 0
lib/mbed/TARGET_LPC1768/cmsis_nvic.h View File

@@ -0,0 +1,51 @@
1
+/* mbed Microcontroller Library
2
+ * CMSIS-style functionality to support dynamic vectors
3
+ *******************************************************************************
4
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
5
+ * All rights reserved.
6
+ *
7
+ * Redistribution and use in source and binary forms, with or without
8
+ * modification, are permitted provided that the following conditions are met:
9
+ *
10
+ * 1. Redistributions of source code must retain the above copyright notice,
11
+ *    this list of conditions and the following disclaimer.
12
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
13
+ *    this list of conditions and the following disclaimer in the documentation
14
+ *    and/or other materials provided with the distribution.
15
+ * 3. Neither the name of ARM Limited nor the names of its contributors
16
+ *    may be used to endorse or promote products derived from this software
17
+ *    without specific prior written permission.
18
+ *
19
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
23
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
26
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29
+ *******************************************************************************
30
+ */
31
+
32
+#ifndef MBED_CMSIS_NVIC_H
33
+#define MBED_CMSIS_NVIC_H
34
+
35
+#include "cmsis.h"
36
+
37
+#define NVIC_NUM_VECTORS      (16 + 33)
38
+#define NVIC_USER_IRQ_OFFSET  16
39
+
40
+#ifdef __cplusplus
41
+extern "C" {
42
+#endif
43
+
44
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
45
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
46
+
47
+#ifdef __cplusplus
48
+}
49
+#endif
50
+
51
+#endif

+ 276
- 0
lib/mbed/TARGET_LPC1768/core_ca9.h View File

@@ -0,0 +1,276 @@
1
+/**************************************************************************//**
2
+ * @file     core_ca9.h
3
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
4
+ * @version
5
+ * @date     25 March 2013
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2012 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#if defined ( __ICCARM__ )
39
+ #pragma system_include  /* treat file as system include file for MISRA check */
40
+#endif
41
+
42
+#ifdef __cplusplus
43
+ extern "C" {
44
+#endif
45
+
46
+#ifndef __CORE_CA9_H_GENERIC
47
+#define __CORE_CA9_H_GENERIC
48
+
49
+
50
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
51
+  CMSIS violates the following MISRA-C:2004 rules:
52
+
53
+   \li Required Rule 8.5, object/function definition in header file.<br>
54
+     Function definitions in header files are used to allow 'inlining'.
55
+
56
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
57
+     Unions are used for effective representation of core registers.
58
+
59
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
60
+     Function-like macros are used to allow more efficient code.
61
+ */
62
+
63
+
64
+/*******************************************************************************
65
+ *                 CMSIS definitions
66
+ ******************************************************************************/
67
+/** \ingroup Cortex_A9
68
+  @{
69
+ */
70
+
71
+/*  CMSIS CA9 definitions */
72
+#define __CA9_CMSIS_VERSION_MAIN  (0x03)                                   /*!< [31:16] CMSIS HAL main version   */
73
+#define __CA9_CMSIS_VERSION_SUB   (0x10)                                   /*!< [15:0]  CMSIS HAL sub version    */
74
+#define __CA9_CMSIS_VERSION       ((__CA9_CMSIS_VERSION_MAIN << 16) | \
75
+                                    __CA9_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
76
+
77
+#define __CORTEX_A                (0x09)                                   /*!< Cortex-A Core                    */
78
+
79
+
80
+#if   defined ( __CC_ARM )
81
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
82
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
83
+  #define __STATIC_INLINE  static __inline
84
+  #define __STATIC_ASM     static __asm
85
+
86
+#elif defined ( __ICCARM__ )
87
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
88
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
89
+  #define __STATIC_INLINE  static inline
90
+  #define __STATIC_ASM     static __asm
91
+
92
+#include <stdint.h>
93
+inline uint32_t __get_PSR(void) {
94
+	__ASM("mrs r0, cpsr");
95
+}
96
+
97
+#elif defined ( __TMS470__ )
98
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
99
+  #define __STATIC_INLINE  static inline
100
+  #define __STATIC_ASM     static __asm
101
+
102
+#elif defined ( __GNUC__ )
103
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
104
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
105
+  #define __STATIC_INLINE  static inline
106
+  #define __STATIC_ASM     static __asm
107
+
108
+#elif defined ( __TASKING__ )
109
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
110
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
111
+  #define __STATIC_INLINE  static inline
112
+  #define __STATIC_ASM     static __asm
113
+
114
+#endif
115
+
116
+/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
117
+*/
118
+#if defined ( __CC_ARM )
119
+  #if defined __TARGET_FPU_VFP
120
+    #if (__FPU_PRESENT == 1)
121
+      #define __FPU_USED       1
122
+    #else
123
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124
+      #define __FPU_USED       0
125
+    #endif
126
+  #else
127
+    #define __FPU_USED         0
128
+  #endif
129
+
130
+#elif defined ( __ICCARM__ )
131
+  #if defined __ARMVFP__
132
+    #if (__FPU_PRESENT == 1)
133
+      #define __FPU_USED       1
134
+    #else
135
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
136
+      #define __FPU_USED       0
137
+    #endif
138
+  #else
139
+    #define __FPU_USED         0
140
+  #endif
141
+
142
+#elif defined ( __TMS470__ )
143
+  #if defined __TI_VFP_SUPPORT__
144
+    #if (__FPU_PRESENT == 1)
145
+      #define __FPU_USED       1
146
+    #else
147
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
148
+      #define __FPU_USED       0
149
+    #endif
150
+  #else
151
+    #define __FPU_USED         0
152
+  #endif
153
+
154
+#elif defined ( __GNUC__ )
155
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
156
+    #if (__FPU_PRESENT == 1)
157
+      #define __FPU_USED       1
158
+    #else
159
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
160
+      #define __FPU_USED       0
161
+    #endif
162
+  #else
163
+    #define __FPU_USED         0
164
+  #endif
165
+
166
+#elif defined ( __TASKING__ )
167
+  #if defined __FPU_VFP__
168
+    #if (__FPU_PRESENT == 1)
169
+      #define __FPU_USED       1
170
+    #else
171
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
172
+      #define __FPU_USED       0
173
+    #endif
174
+  #else
175
+    #define __FPU_USED         0
176
+  #endif
177
+#endif
178
+
179
+#include <stdint.h>                      /*!< standard types definitions                      */
180
+#include "core_caInstr.h"                /*!< Core Instruction Access                         */
181
+#include "core_caFunc.h"                 /*!< Core Function Access                            */
182
+#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
183
+
184
+#endif /* __CORE_CA9_H_GENERIC */
185
+
186
+#ifndef __CMSIS_GENERIC
187
+
188
+#ifndef __CORE_CA9_H_DEPENDANT
189
+#define __CORE_CA9_H_DEPENDANT
190
+
191
+/* check device defines and use defaults */
192
+#if defined __CHECK_DEVICE_DEFINES
193
+  #ifndef __CA9_REV
194
+    #define __CA9_REV               0x0000
195
+    #warning "__CA9_REV not defined in device header file; using default!"
196
+  #endif
197
+
198
+  #ifndef __FPU_PRESENT
199
+    #define __FPU_PRESENT             1
200
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
201
+  #endif
202
+
203
+  #ifndef __Vendor_SysTickConfig
204
+    #define __Vendor_SysTickConfig    1
205
+  #endif
206
+
207
+  #if __Vendor_SysTickConfig == 0
208
+    #error "__Vendor_SysTickConfig set to 0, but vendor systick timer must be supplied for Cortex-A9"
209
+  #endif
210
+#endif
211
+
212
+/* IO definitions (access restrictions to peripheral registers) */
213
+/**
214
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
215
+
216
+    <strong>IO Type Qualifiers</strong> are used
217
+    \li to specify the access to peripheral variables.
218
+    \li for automatic generation of peripheral register debug information.
219
+*/
220
+#ifdef __cplusplus
221
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
222
+#else
223
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
224
+#endif
225
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
226
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
227
+
228
+/*@} end of group Cortex_A9 */
229
+
230
+
231
+/*******************************************************************************
232
+ *                 Register Abstraction
233
+ ******************************************************************************/
234
+/** \defgroup CMSIS_core_register Defines and Type Definitions
235
+    \brief Type definitions and defines for Cortex-A processor based devices.
236
+*/
237
+
238
+/** \ingroup    CMSIS_core_register
239
+    \defgroup   CMSIS_CORE  Status and Control Registers
240
+    \brief  Core Register type definitions.
241
+  @{
242
+ */
243
+
244
+/** \brief  Union type to access the Application Program Status Register (APSR).
245
+ */
246
+typedef union
247
+{
248
+  struct
249
+  {
250
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
251
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
252
+    uint32_t reserved1:7;                /*!< bit: 20..23  Reserved                           */
253
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
254
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
255
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
256
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
257
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
258
+  } b;                                   /*!< Structure used for bit  access                  */
259
+  uint32_t w;                            /*!< Type      used for word access                  */ 
260
+} APSR_Type;
261
+
262
+
263
+/*@} end of group CMSIS_CORE */
264
+
265
+/*@} end of CMSIS_Core_FPUFunctions */
266
+
267
+
268
+#endif /* __CORE_CA9_H_GENERIC */
269
+
270
+#endif /* __CMSIS_GENERIC */
271
+
272
+#ifdef __cplusplus
273
+}
274
+
275
+
276
+#endif

+ 1418
- 0
lib/mbed/TARGET_LPC1768/core_caFunc.h
File diff suppressed because it is too large
View File


+ 45
- 0
lib/mbed/TARGET_LPC1768/core_caInstr.h View File

@@ -0,0 +1,45 @@
1
+/**************************************************************************//**
2
+ * @file     core_caInstr.h
3
+ * @brief    CMSIS Cortex-A9 Core Peripheral Access Layer Header File
4
+ * @version
5
+ * @date     04. December 2012
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2012 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+#ifndef __CORE_CAINSTR_H__
38
+#define __CORE_CAINSTR_H__
39
+
40
+#define __CORTEX_M 0x3
41
+#include "core_cmInstr.h"
42
+#undef  __CORTEX_M
43
+
44
+#endif
45
+

+ 847
- 0
lib/mbed/TARGET_LPC1768/core_ca_mmu.h View File

@@ -0,0 +1,847 @@
1
+;/**************************************************************************//**
2
+; * @file     core_ca_mmu.h
3
+; * @brief    MMU Startup File for A9_MP Device Series
4
+; * @version  V1.01
5
+; * @date     10 Sept 2014
6
+; *
7
+; * @note
8
+; *
9
+; ******************************************************************************/
10
+;/* Copyright (c) 2012-2014 ARM LIMITED
11
+;
12
+;   All rights reserved.
13
+;   Redistribution and use in source and binary forms, with or without
14
+;   modification, are permitted provided that the following conditions are met:
15
+;   - Redistributions of source code must retain the above copyright
16
+;     notice, this list of conditions and the following disclaimer.
17
+;   - Redistributions in binary form must reproduce the above copyright
18
+;     notice, this list of conditions and the following disclaimer in the
19
+;     documentation and/or other materials provided with the distribution.
20
+;   - Neither the name of ARM nor the names of its contributors may be used
21
+;     to endorse or promote products derived from this software without
22
+;     specific prior written permission.
23
+;   *
24
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+;   POSSIBILITY OF SUCH DAMAGE.
35
+;   ---------------------------------------------------------------------------*/
36
+
37
+#ifdef __cplusplus
38
+ extern "C" {
39
+#endif
40
+
41
+#ifndef _MMU_FUNC_H
42
+#define _MMU_FUNC_H
43
+
44
+#define SECTION_DESCRIPTOR      (0x2)
45
+#define SECTION_MASK            (0xFFFFFFFC)
46
+
47
+#define SECTION_TEXCB_MASK      (0xFFFF8FF3)
48
+#define SECTION_B_SHIFT         (2)
49
+#define SECTION_C_SHIFT         (3)
50
+#define SECTION_TEX0_SHIFT      (12)
51
+#define SECTION_TEX1_SHIFT      (13)
52
+#define SECTION_TEX2_SHIFT      (14)
53
+
54
+#define SECTION_XN_MASK         (0xFFFFFFEF)
55
+#define SECTION_XN_SHIFT        (4)
56
+
57
+#define SECTION_DOMAIN_MASK     (0xFFFFFE1F)
58
+#define SECTION_DOMAIN_SHIFT    (5)
59
+
60
+#define SECTION_P_MASK          (0xFFFFFDFF)
61
+#define SECTION_P_SHIFT         (9)
62
+
63
+#define SECTION_AP_MASK         (0xFFFF73FF)
64
+#define SECTION_AP_SHIFT        (10)
65
+#define SECTION_AP2_SHIFT       (15)
66
+
67
+#define SECTION_S_MASK          (0xFFFEFFFF)
68
+#define SECTION_S_SHIFT         (16)
69
+
70
+#define SECTION_NG_MASK         (0xFFFDFFFF)
71
+#define SECTION_NG_SHIFT        (17)
72
+
73
+#define SECTION_NS_MASK         (0xFFF7FFFF)
74
+#define SECTION_NS_SHIFT        (19)
75
+
76
+
77
+#define PAGE_L1_DESCRIPTOR      (0x1)
78
+#define PAGE_L1_MASK            (0xFFFFFFFC)
79
+
80
+#define PAGE_L2_4K_DESC         (0x2)
81
+#define PAGE_L2_4K_MASK         (0xFFFFFFFD)
82
+
83
+#define PAGE_L2_64K_DESC        (0x1)
84
+#define PAGE_L2_64K_MASK        (0xFFFFFFFC)
85
+
86
+#define PAGE_4K_TEXCB_MASK      (0xFFFFFE33)
87
+#define PAGE_4K_B_SHIFT         (2)
88
+#define PAGE_4K_C_SHIFT         (3)
89
+#define PAGE_4K_TEX0_SHIFT      (6)
90
+#define PAGE_4K_TEX1_SHIFT      (7)
91
+#define PAGE_4K_TEX2_SHIFT      (8)
92
+
93
+#define PAGE_64K_TEXCB_MASK     (0xFFFF8FF3)
94
+#define PAGE_64K_B_SHIFT        (2)
95
+#define PAGE_64K_C_SHIFT        (3)
96
+#define PAGE_64K_TEX0_SHIFT     (12)
97
+#define PAGE_64K_TEX1_SHIFT     (13)
98
+#define PAGE_64K_TEX2_SHIFT     (14)
99
+
100
+#define PAGE_TEXCB_MASK         (0xFFFF8FF3)
101
+#define PAGE_B_SHIFT            (2)
102
+#define PAGE_C_SHIFT            (3)
103
+#define PAGE_TEX_SHIFT          (12)
104
+
105
+#define PAGE_XN_4K_MASK         (0xFFFFFFFE)
106
+#define PAGE_XN_4K_SHIFT        (0)
107
+#define PAGE_XN_64K_MASK        (0xFFFF7FFF)
108
+#define PAGE_XN_64K_SHIFT       (15)
109
+
110
+
111
+#define PAGE_DOMAIN_MASK        (0xFFFFFE1F)
112
+#define PAGE_DOMAIN_SHIFT       (5)
113
+
114
+#define PAGE_P_MASK             (0xFFFFFDFF)
115
+#define PAGE_P_SHIFT            (9)
116
+
117
+#define PAGE_AP_MASK            (0xFFFFFDCF)
118
+#define PAGE_AP_SHIFT           (4)
119
+#define PAGE_AP2_SHIFT          (9)
120
+
121
+#define PAGE_S_MASK             (0xFFFFFBFF)
122
+#define PAGE_S_SHIFT            (10)
123
+
124
+#define PAGE_NG_MASK            (0xFFFFF7FF)
125
+#define PAGE_NG_SHIFT           (11)
126
+
127
+#define PAGE_NS_MASK            (0xFFFFFFF7)
128
+#define PAGE_NS_SHIFT           (3)
129
+
130
+#define OFFSET_1M               (0x00100000)
131
+#define OFFSET_64K              (0x00010000)
132
+#define OFFSET_4K               (0x00001000)
133
+
134
+#define DESCRIPTOR_FAULT        (0x00000000)
135
+
136
+/* ###########################  MMU Function Access  ########################### */
137
+/** \ingroup  MMU_FunctionInterface
138
+    \defgroup MMU_Functions MMU Functions Interface
139
+  @{
140
+ */
141
+
142
+/* Attributes enumerations */
143
+
144
+/* Region size attributes */
145
+typedef enum
146
+{
147
+   SECTION,
148
+   PAGE_4k,
149
+   PAGE_64k,
150
+} mmu_region_size_Type;
151
+
152
+/* Region type attributes */
153
+typedef enum
154
+{
155
+   NORMAL,
156
+   DEVICE,
157
+   SHARED_DEVICE,
158
+   NON_SHARED_DEVICE,
159
+   STRONGLY_ORDERED
160
+} mmu_memory_Type;
161
+
162
+/* Region cacheability attributes */
163
+typedef enum
164
+{
165
+   NON_CACHEABLE,
166
+   WB_WA,
167
+   WT,
168
+   WB_NO_WA,
169
+} mmu_cacheability_Type;
170
+
171
+/* Region parity check attributes */
172
+typedef enum
173
+{
174
+   ECC_DISABLED,
175
+   ECC_ENABLED,
176
+} mmu_ecc_check_Type;
177
+
178
+/* Region execution attributes */
179
+typedef enum
180
+{
181
+   EXECUTE,
182
+   NON_EXECUTE,
183
+} mmu_execute_Type;
184
+
185
+/* Region global attributes */
186
+typedef enum
187
+{
188
+   GLOBAL,
189
+   NON_GLOBAL,
190
+} mmu_global_Type;
191
+
192
+/* Region shareability attributes */
193
+typedef enum
194
+{
195
+   NON_SHARED,
196
+   SHARED,
197
+} mmu_shared_Type;
198
+
199
+/* Region security attributes */
200
+typedef enum
201
+{
202
+   SECURE,
203
+   NON_SECURE,
204
+} mmu_secure_Type;
205
+
206
+/* Region access attributes */
207
+typedef enum
208
+{
209
+   NO_ACCESS,
210
+   RW,
211
+   READ,
212
+} mmu_access_Type;
213
+
214
+/* Memory Region definition */
215
+typedef struct RegionStruct {
216
+    mmu_region_size_Type rg_t;
217
+    mmu_memory_Type mem_t;
218
+    uint8_t domain;
219
+    mmu_cacheability_Type inner_norm_t;
220
+    mmu_cacheability_Type outer_norm_t;
221
+    mmu_ecc_check_Type e_t;
222
+    mmu_execute_Type xn_t;
223
+    mmu_global_Type g_t;
224
+    mmu_secure_Type sec_t;
225
+    mmu_access_Type priv_t;
226
+    mmu_access_Type user_t;
227
+    mmu_shared_Type sh_t;
228
+
229
+} mmu_region_attributes_Type;
230
+
231
+/** \brief  Set section execution-never attribute
232
+
233
+    The function sets section execution-never attribute
234
+
235
+    \param [out]    descriptor_l1  L1 descriptor.
236
+    \param [in]                xn  Section execution-never attribute : EXECUTE , NON_EXECUTE.
237
+
238
+    \return          0  
239
+ */
240
+__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
241
+{
242
+    *descriptor_l1 &= SECTION_XN_MASK;
243
+    *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
244
+    return 0;
245
+}
246
+
247
+/** \brief  Set section domain
248
+
249
+    The function sets section domain
250
+
251
+    \param [out]    descriptor_l1  L1 descriptor.
252
+    \param [in]            domain  Section domain
253
+
254
+    \return          0  
255
+ */
256
+__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
257
+{
258
+    *descriptor_l1 &= SECTION_DOMAIN_MASK;
259
+    *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
260
+    return 0;
261
+}
262
+
263
+/** \brief  Set section parity check
264
+
265
+    The function sets section parity check
266
+
267
+    \param [out]    descriptor_l1  L1 descriptor.
268
+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
269
+
270
+    \return          0  
271
+ */
272
+__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
273
+{
274
+    *descriptor_l1 &= SECTION_P_MASK;
275
+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
276
+    return 0;
277
+}
278
+
279
+/** \brief  Set section access privileges
280
+
281
+    The function sets section access privileges
282
+
283
+    \param [out]    descriptor_l1  L1 descriptor.
284
+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
285
+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
286
+    \param [in]               afe  Access flag enable
287
+
288
+    \return          0  
289
+ */
290
+__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
291
+{
292
+    uint32_t ap = 0;
293
+
294
+    if (afe == 0) { //full access
295
+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
296
+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
297
+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
298
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
299
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
300
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
301
+    }
302
+
303
+    else { //Simplified access
304
+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
305
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
306
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
307
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
308
+    }
309
+
310
+    *descriptor_l1 &= SECTION_AP_MASK;
311
+    *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
312
+    *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
313
+
314
+    return 0;
315
+}
316
+
317
+/** \brief  Set section shareability
318
+
319
+    The function sets section shareability
320
+
321
+    \param [out]    descriptor_l1  L1 descriptor.
322
+    \param [in]             s_bit  Section shareability: NON_SHARED, SHARED
323
+
324
+    \return          0  
325
+ */
326
+__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
327
+{
328
+    *descriptor_l1 &= SECTION_S_MASK;
329
+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
330
+    return 0;
331
+}
332
+
333
+/** \brief  Set section Global attribute
334
+
335
+    The function sets section Global attribute
336
+
337
+    \param [out]    descriptor_l1  L1 descriptor.
338
+    \param [in]             g_bit  Section attribute: GLOBAL, NON_GLOBAL
339
+
340
+    \return          0  
341
+ */
342
+__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
343
+{
344
+    *descriptor_l1 &= SECTION_NG_MASK;
345
+    *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
346
+    return 0;
347
+}
348
+
349
+/** \brief  Set section Security attribute
350
+
351
+    The function sets section Global attribute
352
+
353
+    \param [out]    descriptor_l1  L1 descriptor.
354
+    \param [in]             s_bit  Section Security attribute: SECURE, NON_SECURE
355
+
356
+    \return          0  
357
+ */
358
+__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
359
+{
360
+    *descriptor_l1 &= SECTION_NS_MASK;
361
+    *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
362
+    return 0;
363
+}
364
+
365
+/* Page 4k or 64k */
366
+/** \brief  Set 4k/64k page execution-never attribute
367
+
368
+    The function sets 4k/64k page execution-never attribute
369
+
370
+    \param [out]    descriptor_l2  L2 descriptor.
371
+    \param [in]                xn  Page execution-never attribute : EXECUTE , NON_EXECUTE.
372
+    \param [in]              page  Page size: PAGE_4k, PAGE_64k,
373
+   
374
+    \return          0  
375
+ */
376
+__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
377
+{
378
+    if (page == PAGE_4k)
379
+    {
380
+        *descriptor_l2 &= PAGE_XN_4K_MASK;
381
+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
382
+    }
383
+    else
384
+    {
385
+        *descriptor_l2 &= PAGE_XN_64K_MASK;
386
+        *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
387
+    }
388
+    return 0;
389
+}
390
+
391
+/** \brief  Set 4k/64k page domain
392
+
393
+    The function sets 4k/64k page domain
394
+
395
+    \param [out]    descriptor_l1  L1 descriptor.
396
+    \param [in]            domain  Page domain
397
+
398
+    \return          0  
399
+ */
400
+__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
401
+{
402
+    *descriptor_l1 &= PAGE_DOMAIN_MASK;
403
+    *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
404
+    return 0;
405
+}
406
+
407
+/** \brief  Set 4k/64k page parity check
408
+
409
+    The function sets 4k/64k page parity check
410
+
411
+    \param [out]    descriptor_l1  L1 descriptor.
412
+    \param [in]              p_bit Parity check: ECC_DISABLED, ECC_ENABLED
413
+
414
+    \return          0  
415
+ */
416
+__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
417
+{
418
+    *descriptor_l1 &= SECTION_P_MASK;
419
+    *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
420
+    return 0;
421
+}
422
+
423
+/** \brief  Set 4k/64k page access privileges
424
+
425
+    The function sets 4k/64k page access privileges
426
+
427
+    \param [out]    descriptor_l2  L2 descriptor.
428
+    \param [in]              user  User Level Access: NO_ACCESS, RW, READ
429
+    \param [in]              priv  Privilege Level Access: NO_ACCESS, RW, READ
430
+    \param [in]               afe  Access flag enable
431
+
432
+    \return          0  
433
+ */
434
+__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv,  uint32_t afe)
435
+{
436
+    uint32_t ap = 0;
437
+
438
+    if (afe == 0) { //full access
439
+        if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
440
+        else if ((priv == RW) && (user == NO_ACCESS))   { ap = 0x1; }
441
+        else if ((priv == RW) && (user == READ))        { ap = 0x2; }
442
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
443
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
444
+        else if ((priv == READ) && (user == READ))      { ap = 0x6; }
445
+    }
446
+
447
+    else { //Simplified access
448
+        if ((priv == RW) && (user == NO_ACCESS))        { ap = 0x1; }
449
+        else if ((priv == RW) && (user == RW))          { ap = 0x3; }
450
+        else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
451
+        else if ((priv == READ) && (user == READ))      { ap = 0x7; }
452
+    }
453
+
454
+    *descriptor_l2 &= PAGE_AP_MASK;
455
+    *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
456
+    *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
457
+
458
+    return 0;
459
+}
460
+
461
+/** \brief  Set 4k/64k page shareability
462
+
463
+    The function sets 4k/64k page shareability
464
+
465
+    \param [out]    descriptor_l2  L2 descriptor.
466
+    \param [in]             s_bit  4k/64k page shareability: NON_SHARED, SHARED
467
+
468
+    \return          0  
469
+ */
470
+__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
471
+{
472
+    *descriptor_l2 &= PAGE_S_MASK;
473
+    *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
474
+    return 0;
475
+}
476
+
477
+/** \brief  Set 4k/64k page Global attribute
478
+
479
+    The function sets 4k/64k page Global attribute
480
+
481
+    \param [out]    descriptor_l2  L2 descriptor.
482
+    \param [in]             g_bit  4k/64k page attribute: GLOBAL, NON_GLOBAL
483
+
484
+    \return          0  
485
+ */
486
+__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
487
+{
488
+    *descriptor_l2 &= PAGE_NG_MASK;
489
+    *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
490
+    return 0;
491
+}
492
+
493
+/** \brief  Set 4k/64k page Security attribute
494
+
495
+    The function sets 4k/64k page Global attribute
496
+
497
+    \param [out]    descriptor_l1  L1 descriptor.
498
+    \param [in]             s_bit  4k/64k page Security attribute: SECURE, NON_SECURE
499
+
500
+    \return          0  
501
+ */
502
+__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
503
+{
504
+    *descriptor_l1 &= PAGE_NS_MASK;
505
+    *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
506
+    return 0;
507
+}
508
+
509
+
510
+/** \brief  Set Section memory attributes
511
+
512
+    The function sets section memory attributes
513
+
514
+    \param [out]    descriptor_l1  L1 descriptor.
515
+    \param [in]               mem  Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
516
+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
517
+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
518
+
519
+    \return          0  
520
+ */
521
+__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
522
+{
523
+    *descriptor_l1 &= SECTION_TEXCB_MASK;
524
+
525
+    if (STRONGLY_ORDERED == mem)
526
+    {
527
+        return 0;
528
+    }
529
+    else if (SHARED_DEVICE == mem)
530
+    {
531
+        *descriptor_l1 |= (1 << SECTION_B_SHIFT);
532
+    }
533
+    else if (NON_SHARED_DEVICE == mem)
534
+    {
535
+        *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
536
+    }
537
+    else if (NORMAL == mem)
538
+    {
539
+           *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
540
+           switch(inner)
541
+           {
542
+            case NON_CACHEABLE:
543
+            break;
544
+            case WB_WA:
545
+                *descriptor_l1 |= (1 << SECTION_B_SHIFT);
546
+                break;
547
+            case WT:
548
+                *descriptor_l1 |= 1 << SECTION_C_SHIFT;
549
+                break;
550
+            case WB_NO_WA:
551
+                *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
552
+                break;
553
+        }
554
+        switch(outer)
555
+        {
556
+            case NON_CACHEABLE:
557
+             break;
558
+            case WB_WA:
559
+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
560
+                break;
561
+            case WT:
562
+                *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
563
+                break;
564
+            case WB_NO_WA:
565
+                *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
566
+                break;
567
+        }
568
+    }
569
+
570
+    return 0;
571
+}
572
+
573
+/** \brief  Set 4k/64k page memory attributes
574
+
575
+    The function sets 4k/64k page memory attributes
576
+
577
+    \param [out]    descriptor_l2  L2 descriptor.
578
+    \param [in]               mem  4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
579
+    \param [in]             outer  Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
580
+    \param [in]             inner  Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
581
+
582
+    \return          0  
583
+ */
584
+__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
585
+{
586
+    *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
587
+
588
+    if (page == PAGE_64k)
589
+    {
590
+        //same as section
591
+        __memory_section(descriptor_l2, mem, outer, inner);
592
+    }
593
+    else
594
+    {
595
+        if (STRONGLY_ORDERED == mem)
596
+        {
597
+            return 0;
598
+        }
599
+        else if (SHARED_DEVICE == mem)
600
+        {
601
+            *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
602
+        }
603
+        else if (NON_SHARED_DEVICE == mem)
604
+        {
605
+             *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
606
+        }
607
+        else if (NORMAL == mem)
608
+        {
609
+            *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
610
+            switch(inner)
611
+            {
612
+                case NON_CACHEABLE:
613
+                break;
614
+                case WB_WA:
615
+                     *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
616
+                     break;
617
+                case WT:
618
+                    *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
619
+                     break;
620
+                case WB_NO_WA:
621
+                    *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
622
+                    break;
623
+            }
624
+            switch(outer)
625
+            {
626
+                case NON_CACHEABLE:
627
+                break;
628
+                case WB_WA:
629
+                      *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
630
+                    break;
631
+                case WT:
632
+                     *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
633
+                    break;
634
+                case WB_NO_WA:
635
+                    *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
636
+                    break;
637
+            }
638
+        }
639
+    }
640
+
641
+    return 0;
642
+}
643
+
644
+/** \brief  Create a L1 section descriptor
645
+
646
+    The function creates a section descriptor.
647
+    
648
+    Assumptions:
649
+    - 16MB super sections not supported
650
+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
651
+    - Functions always return 0
652
+
653
+    \param [out]       descriptor  L1 descriptor
654
+    \param [out]      descriptor2  L2 descriptor
655
+    \param [in]               reg  Section attributes
656
+
657
+    \return          0  
658
+ */
659
+__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
660
+{
661
+    *descriptor  = 0;
662
+
663
+   __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
664
+   __xn_section(descriptor,reg.xn_t);
665
+   __domain_section(descriptor, reg.domain);
666
+   __p_section(descriptor, reg.e_t);
667
+   __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
668
+   __shared_section(descriptor,reg.sh_t);
669
+   __global_section(descriptor,reg.g_t);
670
+   __secure_section(descriptor,reg.sec_t);
671
+   *descriptor &= SECTION_MASK;
672
+   *descriptor |= SECTION_DESCRIPTOR;
673
+
674
+   return 0;
675
+
676
+}
677
+
678
+
679
+/** \brief  Create a L1 and L2 4k/64k page descriptor
680
+
681
+    The function creates a 4k/64k page descriptor.
682
+    Assumptions:
683
+    - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
684
+    - Functions always return 0
685
+
686
+    \param [out]       descriptor  L1 descriptor
687
+    \param [out]      descriptor2  L2 descriptor
688
+    \param [in]               reg  4k/64k page attributes
689
+
690
+    \return          0  
691
+ */
692
+__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
693
+{
694
+    *descriptor  = 0;
695
+    *descriptor2 = 0;
696
+
697
+    switch (reg.rg_t)
698
+    {
699
+        case PAGE_4k:
700
+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
701
+            __xn_page(descriptor2, reg.xn_t, PAGE_4k);
702
+            __domain_page(descriptor, reg.domain);
703
+            __p_page(descriptor, reg.e_t);
704
+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
705
+            __shared_page(descriptor2,reg.sh_t);
706
+            __global_page(descriptor2,reg.g_t);
707
+            __secure_page(descriptor,reg.sec_t);
708
+            *descriptor &= PAGE_L1_MASK;
709
+            *descriptor |= PAGE_L1_DESCRIPTOR;
710
+            *descriptor2 &= PAGE_L2_4K_MASK;
711
+            *descriptor2 |= PAGE_L2_4K_DESC;
712
+            break;
713
+
714
+        case PAGE_64k:
715
+            __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
716
+            __xn_page(descriptor2, reg.xn_t, PAGE_64k);
717
+            __domain_page(descriptor, reg.domain);
718
+            __p_page(descriptor, reg.e_t);
719
+            __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
720
+            __shared_page(descriptor2,reg.sh_t);
721
+            __global_page(descriptor2,reg.g_t);
722
+            __secure_page(descriptor,reg.sec_t);
723
+            *descriptor &= PAGE_L1_MASK;
724
+            *descriptor |= PAGE_L1_DESCRIPTOR;
725
+            *descriptor2 &= PAGE_L2_64K_MASK;
726
+            *descriptor2 |= PAGE_L2_64K_DESC;
727
+            break;
728
+
729
+        case SECTION:
730
+            //error
731
+            break;    
732
+
733
+    }
734
+
735
+   return 0;
736
+
737
+}
738
+
739
+/** \brief  Create a 1MB Section
740
+
741
+    \param [in]               ttb  Translation table base address
742
+    \param [in]      base_address  Section base address
743
+    \param [in]             count  Number of sections to create
744
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
745
+
746
+ */
747
+__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
748
+{
749
+    uint32_t offset;
750
+    uint32_t entry;
751
+    uint32_t i;
752
+
753
+    offset = base_address >> 20;
754
+    entry  = (base_address & 0xFFF00000) | descriptor_l1;
755
+
756
+    //4 bytes aligned
757
+    ttb = ttb + offset;
758
+
759
+    for (i = 0; i < count; i++ )
760
+    {
761
+        //4 bytes aligned
762
+       *ttb++ = entry;
763
+       entry += OFFSET_1M;
764
+    }
765
+}
766
+
767
+/** \brief  Create a 4k page entry
768
+
769
+    \param [in]               ttb  L1 table base address
770
+    \param [in]      base_address  4k base address
771
+    \param [in]             count  Number of 4k pages to create
772
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
773
+    \param [in]            ttb_l2  L2 table base address
774
+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
775
+
776
+ */
777
+__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
778
+{
779
+
780
+    uint32_t offset, offset2;
781
+    uint32_t entry, entry2;
782
+    uint32_t i;
783
+
784
+
785
+    offset = base_address >> 20;
786
+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
787
+
788
+    //4 bytes aligned
789
+    ttb += offset;
790
+    //create l1_entry
791
+    *ttb = entry;
792
+
793
+    offset2 = (base_address & 0xff000) >> 12;
794
+    ttb_l2 += offset2;
795
+    entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
796
+    for (i = 0; i < count; i++ )
797
+    {
798
+        //4 bytes aligned
799
+       *ttb_l2++ = entry2;
800
+       entry2 += OFFSET_4K;
801
+    }
802
+}
803
+
804
+/** \brief  Create a 64k page entry
805
+
806
+    \param [in]               ttb  L1 table base address
807
+    \param [in]      base_address  64k base address
808
+    \param [in]             count  Number of 64k pages to create
809
+    \param [in]     descriptor_l1  L1 descriptor (region attributes) 
810
+    \param [in]            ttb_l2  L2 table base address
811
+    \param [in]     descriptor_l2  L2 descriptor (region attributes) 
812
+
813
+ */
814
+__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
815
+{
816
+    uint32_t offset, offset2;
817
+    uint32_t entry, entry2;
818
+    uint32_t i,j;
819
+
820
+
821
+    offset = base_address >> 20;
822
+    entry  = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
823
+
824
+    //4 bytes aligned
825
+    ttb += offset;
826
+    //create l1_entry
827
+    *ttb = entry;
828
+
829
+    offset2 = (base_address & 0xff000) >> 12;
830
+    ttb_l2 += offset2;
831
+    entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
832
+    for (i = 0; i < count; i++ )
833
+    {
834
+        //create 16 entries
835
+        for (j = 0; j < 16; j++)
836
+            //4 bytes aligned
837
+            *ttb_l2++ = entry2;
838
+        entry2 += OFFSET_64K;
839
+    }
840
+}
841
+
842
+/*@} end of MMU_Functions */
843
+#endif
844
+
845
+#ifdef __cplusplus
846
+}
847
+#endif

+ 740
- 0
lib/mbed/TARGET_LPC1768/core_cm0.h View File

@@ -0,0 +1,740 @@
1
+/**************************************************************************//**
2
+ * @file     core_cm0.h
3
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4
+ * @version  V4.10
5
+ * @date     18. March 2015
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2015 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#if defined ( __ICCARM__ )
39
+ #pragma system_include  /* treat file as system include file for MISRA check */
40
+#endif
41
+
42
+#ifndef __CORE_CM0_H_GENERIC
43
+#define __CORE_CM0_H_GENERIC
44
+
45
+#ifdef __cplusplus
46
+ extern "C" {
47
+#endif
48
+
49
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
50
+  CMSIS violates the following MISRA-C:2004 rules:
51
+
52
+   \li Required Rule 8.5, object/function definition in header file.<br>
53
+     Function definitions in header files are used to allow 'inlining'.
54
+
55
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56
+     Unions are used for effective representation of core registers.
57
+
58
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
59
+     Function-like macros are used to allow more efficient code.
60
+ */
61
+
62
+
63
+/*******************************************************************************
64
+ *                 CMSIS definitions
65
+ ******************************************************************************/
66
+/** \ingroup Cortex_M0
67
+  @{
68
+ */
69
+
70
+/*  CMSIS CM0 definitions */
71
+#define __CM0_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version   */
72
+#define __CM0_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version    */
73
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | \
74
+                                    __CM0_CMSIS_VERSION_SUB          )     /*!< CMSIS HAL version number         */
75
+
76
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
77
+
78
+
79
+#if   defined ( __CC_ARM )
80
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
81
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
82
+  #define __STATIC_INLINE  static __inline
83
+
84
+#elif defined ( __GNUC__ )
85
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
86
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
87
+  #define __STATIC_INLINE  static inline
88
+
89
+#elif defined ( __ICCARM__ )
90
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
91
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92
+  #define __STATIC_INLINE  static inline
93
+
94
+#elif defined ( __TMS470__ )
95
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
96
+  #define __STATIC_INLINE  static inline
97
+
98
+#elif defined ( __TASKING__ )
99
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
100
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
101
+  #define __STATIC_INLINE  static inline
102
+
103
+#elif defined ( __CSMC__ )
104
+  #define __packed
105
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
106
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
107
+  #define __STATIC_INLINE  static inline
108
+
109
+#endif
110
+
111
+/** __FPU_USED indicates whether an FPU is used or not.
112
+    This core does not support an FPU at all
113
+*/
114
+#define __FPU_USED       0
115
+
116
+#if defined ( __CC_ARM )
117
+  #if defined __TARGET_FPU_VFP
118
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119
+  #endif
120
+
121
+#elif defined ( __GNUC__ )
122
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124
+  #endif
125
+
126
+#elif defined ( __ICCARM__ )
127
+  #if defined __ARMVFP__
128
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129
+  #endif
130
+
131
+#elif defined ( __TMS470__ )
132
+  #if defined __TI__VFP_SUPPORT____
133
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134
+  #endif
135
+
136
+#elif defined ( __TASKING__ )
137
+  #if defined __FPU_VFP__
138
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139
+  #endif
140
+
141
+#elif defined ( __CSMC__ )		/* Cosmic */
142
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
143
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144
+  #endif
145
+#endif
146
+
147
+#include <stdint.h>                      /* standard types definitions                      */
148
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
149
+#include <core_cmFunc.h>                 /* Core Function Access                            */
150
+
151
+#ifdef __cplusplus
152
+}
153
+#endif
154
+
155
+#endif /* __CORE_CM0_H_GENERIC */
156
+
157
+#ifndef __CMSIS_GENERIC
158
+
159
+#ifndef __CORE_CM0_H_DEPENDANT
160
+#define __CORE_CM0_H_DEPENDANT
161
+
162
+#ifdef __cplusplus
163
+ extern "C" {
164
+#endif
165
+
166
+/* check device defines and use defaults */
167
+#if defined __CHECK_DEVICE_DEFINES
168
+  #ifndef __CM0_REV
169
+    #define __CM0_REV               0x0000
170
+    #warning "__CM0_REV not defined in device header file; using default!"
171
+  #endif
172
+
173
+  #ifndef __NVIC_PRIO_BITS
174
+    #define __NVIC_PRIO_BITS          2
175
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
176
+  #endif
177
+
178
+  #ifndef __Vendor_SysTickConfig
179
+    #define __Vendor_SysTickConfig    0
180
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
181
+  #endif
182
+#endif
183
+
184
+/* IO definitions (access restrictions to peripheral registers) */
185
+/**
186
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
187
+
188
+    <strong>IO Type Qualifiers</strong> are used
189
+    \li to specify the access to peripheral variables.
190
+    \li for automatic generation of peripheral register debug information.
191
+*/
192
+#ifdef __cplusplus
193
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
194
+#else
195
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
196
+#endif
197
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
198
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
199
+
200
+/*@} end of group Cortex_M0 */
201
+
202
+
203
+
204
+/*******************************************************************************
205
+ *                 Register Abstraction
206
+  Core Register contain:
207
+  - Core Register
208
+  - Core NVIC Register
209
+  - Core SCB Register
210
+  - Core SysTick Register
211
+ ******************************************************************************/
212
+/** \defgroup CMSIS_core_register Defines and Type Definitions
213
+    \brief Type definitions and defines for Cortex-M processor based devices.
214
+*/
215
+
216
+/** \ingroup    CMSIS_core_register
217
+    \defgroup   CMSIS_CORE  Status and Control Registers
218
+    \brief  Core Register type definitions.
219
+  @{
220
+ */
221
+
222
+/** \brief  Union type to access the Application Program Status Register (APSR).
223
+ */
224
+typedef union
225
+{
226
+  struct
227
+  {
228
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
229
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
230
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
231
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
232
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
233
+  } b;                                   /*!< Structure used for bit  access                  */
234
+  uint32_t w;                            /*!< Type      used for word access                  */
235
+} APSR_Type;
236
+
237
+/* APSR Register Definitions */
238
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
239
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
240
+
241
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
242
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
243
+
244
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
245
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
246
+
247
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
248
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
249
+
250
+
251
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
252
+ */
253
+typedef union
254
+{
255
+  struct
256
+  {
257
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
258
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
259
+  } b;                                   /*!< Structure used for bit  access                  */
260
+  uint32_t w;                            /*!< Type      used for word access                  */
261
+} IPSR_Type;
262
+
263
+/* IPSR Register Definitions */
264
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
265
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
266
+
267
+
268
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
269
+ */
270
+typedef union
271
+{
272
+  struct
273
+  {
274
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
275
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
276
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
277
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
278
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
279
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
280
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
281
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
282
+  } b;                                   /*!< Structure used for bit  access                  */
283
+  uint32_t w;                            /*!< Type      used for word access                  */
284
+} xPSR_Type;
285
+
286
+/* xPSR Register Definitions */
287
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
288
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
289
+
290
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
291
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
292
+
293
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
294
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
295
+
296
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
297
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
298
+
299
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
300
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
301
+
302
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
303
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
304
+
305
+
306
+/** \brief  Union type to access the Control Registers (CONTROL).
307
+ */
308
+typedef union
309
+{
310
+  struct
311
+  {
312
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
313
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
314
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
315
+  } b;                                   /*!< Structure used for bit  access                  */
316
+  uint32_t w;                            /*!< Type      used for word access                  */
317
+} CONTROL_Type;
318
+
319
+/* CONTROL Register Definitions */
320
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
321
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
322
+
323
+/*@} end of group CMSIS_CORE */
324
+
325
+
326
+/** \ingroup    CMSIS_core_register
327
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
328
+    \brief      Type definitions for the NVIC Registers
329
+  @{
330
+ */
331
+
332
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
333
+ */
334
+typedef struct
335
+{
336
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
337
+       uint32_t RESERVED0[31];
338
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
339
+       uint32_t RSERVED1[31];
340
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
341
+       uint32_t RESERVED2[31];
342
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
343
+       uint32_t RESERVED3[31];
344
+       uint32_t RESERVED4[64];
345
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
346
+}  NVIC_Type;
347
+
348
+/*@} end of group CMSIS_NVIC */
349
+
350
+
351
+/** \ingroup  CMSIS_core_register
352
+    \defgroup CMSIS_SCB     System Control Block (SCB)
353
+    \brief      Type definitions for the System Control Block Registers
354
+  @{
355
+ */
356
+
357
+/** \brief  Structure type to access the System Control Block (SCB).
358
+ */
359
+typedef struct
360
+{
361
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
362
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
363
+       uint32_t RESERVED0;
364
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
365
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
366
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
367
+       uint32_t RESERVED1;
368
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
369
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
370
+} SCB_Type;
371
+
372
+/* SCB CPUID Register Definitions */
373
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
374
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
375
+
376
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
377
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
378
+
379
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
380
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
381
+
382
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
383
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
384
+
385
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
386
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
387
+
388
+/* SCB Interrupt Control State Register Definitions */
389
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
390
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
391
+
392
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
393
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
394
+
395
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
396
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
397
+
398
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
399
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
400
+
401
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
402
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
403
+
404
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
405
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
406
+
407
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
408
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
409
+
410
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
411
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
412
+
413
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
414
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
415
+
416
+/* SCB Application Interrupt and Reset Control Register Definitions */
417
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
418
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
419
+
420
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
421
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
422
+
423
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
424
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
425
+
426
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
427
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
428
+
429
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
430
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
431
+
432
+/* SCB System Control Register Definitions */
433
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
434
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
435
+
436
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
437
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
438
+
439
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
440
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
441
+
442
+/* SCB Configuration Control Register Definitions */
443
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
444
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
445
+
446
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
447
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
448
+
449
+/* SCB System Handler Control and State Register Definitions */
450
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
451
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
452
+
453
+/*@} end of group CMSIS_SCB */
454
+
455
+
456
+/** \ingroup  CMSIS_core_register
457
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
458
+    \brief      Type definitions for the System Timer Registers.
459
+  @{
460
+ */
461
+
462
+/** \brief  Structure type to access the System Timer (SysTick).
463
+ */
464
+typedef struct
465
+{
466
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
467
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
468
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
469
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
470
+} SysTick_Type;
471
+
472
+/* SysTick Control / Status Register Definitions */
473
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
474
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
475
+
476
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
477
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
478
+
479
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
480
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
481
+
482
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
483
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
484
+
485
+/* SysTick Reload Register Definitions */
486
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
487
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
488
+
489
+/* SysTick Current Register Definitions */
490
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
491
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
492
+
493
+/* SysTick Calibration Register Definitions */
494
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
495
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
496
+
497
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
498
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
499
+
500
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
501
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
502
+
503
+/*@} end of group CMSIS_SysTick */
504
+
505
+
506
+/** \ingroup  CMSIS_core_register
507
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
508
+    \brief      Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
509
+                are only accessible over DAP and not via processor. Therefore
510
+                they are not covered by the Cortex-M0 header file.
511
+  @{
512
+ */
513
+/*@} end of group CMSIS_CoreDebug */
514
+
515
+
516
+/** \ingroup    CMSIS_core_register
517
+    \defgroup   CMSIS_core_base     Core Definitions
518
+    \brief      Definitions for base addresses, unions, and structures.
519
+  @{
520
+ */
521
+
522
+/* Memory mapping of Cortex-M0 Hardware */
523
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
524
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
525
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
526
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
527
+
528
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
529
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
530
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
531
+
532
+
533
+/*@} */
534
+
535
+
536
+
537
+/*******************************************************************************
538
+ *                Hardware Abstraction Layer
539
+  Core Function Interface contains:
540
+  - Core NVIC Functions
541
+  - Core SysTick Functions
542
+  - Core Register Access Functions
543
+ ******************************************************************************/
544
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
545
+*/
546
+
547
+
548
+
549
+/* ##########################   NVIC functions  #################################### */
550
+/** \ingroup  CMSIS_Core_FunctionInterface
551
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
552
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
553
+    @{
554
+ */
555
+
556
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
557
+/* The following MACROS handle generation of the register offset and byte masks */
558
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
559
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
560
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
561
+
562
+
563
+/** \brief  Enable External Interrupt
564
+
565
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
566
+
567
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
568
+ */
569
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
570
+{
571
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
572
+}
573
+
574
+
575
+/** \brief  Disable External Interrupt
576
+
577
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
578
+
579
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
580
+ */
581
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
582
+{
583
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
584
+}
585
+
586
+
587
+/** \brief  Get Pending Interrupt
588
+
589
+    The function reads the pending register in the NVIC and returns the pending bit
590
+    for the specified interrupt.
591
+
592
+    \param [in]      IRQn  Interrupt number.
593
+
594
+    \return             0  Interrupt status is not pending.
595
+    \return             1  Interrupt status is pending.
596
+ */
597
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
598
+{
599
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
600
+}
601
+
602
+
603
+/** \brief  Set Pending Interrupt
604
+
605
+    The function sets the pending bit of an external interrupt.
606
+
607
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
608
+ */
609
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
610
+{
611
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
612
+}
613
+
614
+
615
+/** \brief  Clear Pending Interrupt
616
+
617
+    The function clears the pending bit of an external interrupt.
618
+
619
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
620
+ */
621
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
622
+{
623
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
624
+}
625
+
626
+
627
+/** \brief  Set Interrupt Priority
628
+
629
+    The function sets the priority of an interrupt.
630
+
631
+    \note The priority cannot be set for every core interrupt.
632
+
633
+    \param [in]      IRQn  Interrupt number.
634
+    \param [in]  priority  Priority to set.
635
+ */
636
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
637
+{
638
+  if((int32_t)(IRQn) < 0) {
639
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
640
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
641
+  }
642
+  else {
643
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
644
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
645
+  }
646
+}
647
+
648
+
649
+/** \brief  Get Interrupt Priority
650
+
651
+    The function reads the priority of an interrupt. The interrupt
652
+    number can be positive to specify an external (device specific)
653
+    interrupt, or negative to specify an internal (core) interrupt.
654
+
655
+
656
+    \param [in]   IRQn  Interrupt number.
657
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
658
+                        priority bits of the microcontroller.
659
+ */
660
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
661
+{
662
+
663
+  if((int32_t)(IRQn) < 0) {
664
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
665
+  }
666
+  else {
667
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
668
+  }
669
+}
670
+
671
+
672
+/** \brief  System Reset
673
+
674
+    The function initiates a system reset request to reset the MCU.
675
+ */
676
+__STATIC_INLINE void NVIC_SystemReset(void)
677
+{
678
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
679
+                                                                  buffered write are completed before reset */
680
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
681
+                 SCB_AIRCR_SYSRESETREQ_Msk);
682
+  __DSB();                                                     /* Ensure completion of memory access */
683
+  while(1) { __NOP(); }                                        /* wait until reset */
684
+}
685
+
686
+/*@} end of CMSIS_Core_NVICFunctions */
687
+
688
+
689
+
690
+/* ##################################    SysTick function  ############################################ */
691
+/** \ingroup  CMSIS_Core_FunctionInterface
692
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
693
+    \brief      Functions that configure the System.
694
+  @{
695
+ */
696
+
697
+#if (__Vendor_SysTickConfig == 0)
698
+
699
+/** \brief  System Tick Configuration
700
+
701
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
702
+    Counter is in free running mode to generate periodic interrupts.
703
+
704
+    \param [in]  ticks  Number of ticks between two interrupts.
705
+
706
+    \return          0  Function succeeded.
707
+    \return          1  Function failed.
708
+
709
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
710
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
711
+    must contain a vendor-specific implementation of this function.
712
+
713
+ */
714
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
715
+{
716
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); }    /* Reload value impossible */
717
+
718
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
719
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
720
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
721
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
722
+                   SysTick_CTRL_TICKINT_Msk   |
723
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
724
+  return (0UL);                                                     /* Function successful */
725
+}
726
+
727
+#endif
728
+
729
+/*@} end of CMSIS_Core_SysTickFunctions */
730
+
731
+
732
+
733
+
734
+#ifdef __cplusplus
735
+}
736
+#endif
737
+
738
+#endif /* __CORE_CM0_H_DEPENDANT */
739
+
740
+#endif /* __CMSIS_GENERIC */

+ 854
- 0
lib/mbed/TARGET_LPC1768/core_cm0plus.h View File

@@ -0,0 +1,854 @@
1
+/**************************************************************************//**
2
+ * @file     core_cm0plus.h
3
+ * @brief    CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
4
+ * @version  V4.10
5
+ * @date     18. March 2015
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2015 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#if defined ( __ICCARM__ )
39
+ #pragma system_include  /* treat file as system include file for MISRA check */
40
+#endif
41
+
42
+#ifndef __CORE_CM0PLUS_H_GENERIC
43
+#define __CORE_CM0PLUS_H_GENERIC
44
+
45
+#ifdef __cplusplus
46
+ extern "C" {
47
+#endif
48
+
49
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
50
+  CMSIS violates the following MISRA-C:2004 rules:
51
+
52
+   \li Required Rule 8.5, object/function definition in header file.<br>
53
+     Function definitions in header files are used to allow 'inlining'.
54
+
55
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56
+     Unions are used for effective representation of core registers.
57
+
58
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
59
+     Function-like macros are used to allow more efficient code.
60
+ */
61
+
62
+
63
+/*******************************************************************************
64
+ *                 CMSIS definitions
65
+ ******************************************************************************/
66
+/** \ingroup Cortex-M0+
67
+  @{
68
+ */
69
+
70
+/*  CMSIS CM0P definitions */
71
+#define __CM0PLUS_CMSIS_VERSION_MAIN (0x04)                                /*!< [31:16] CMSIS HAL main version   */
72
+#define __CM0PLUS_CMSIS_VERSION_SUB  (0x00)                                /*!< [15:0]  CMSIS HAL sub version    */
73
+#define __CM0PLUS_CMSIS_VERSION      ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
74
+                                       __CM0PLUS_CMSIS_VERSION_SUB)        /*!< CMSIS HAL version number         */
75
+
76
+#define __CORTEX_M                (0x00)                                   /*!< Cortex-M Core                    */
77
+
78
+
79
+#if   defined ( __CC_ARM )
80
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
81
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
82
+  #define __STATIC_INLINE  static __inline
83
+
84
+#elif defined ( __GNUC__ )
85
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
86
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
87
+  #define __STATIC_INLINE  static inline
88
+
89
+#elif defined ( __ICCARM__ )
90
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
91
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92
+  #define __STATIC_INLINE  static inline
93
+
94
+#elif defined ( __TMS470__ )
95
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
96
+  #define __STATIC_INLINE  static inline
97
+
98
+#elif defined ( __TASKING__ )
99
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
100
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
101
+  #define __STATIC_INLINE  static inline
102
+
103
+#elif defined ( __CSMC__ )
104
+  #define __packed
105
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
106
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
107
+  #define __STATIC_INLINE  static inline
108
+
109
+#endif
110
+
111
+/** __FPU_USED indicates whether an FPU is used or not.
112
+    This core does not support an FPU at all
113
+*/
114
+#define __FPU_USED       0
115
+
116
+#if defined ( __CC_ARM )
117
+  #if defined __TARGET_FPU_VFP
118
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119
+  #endif
120
+
121
+#elif defined ( __GNUC__ )
122
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124
+  #endif
125
+
126
+#elif defined ( __ICCARM__ )
127
+  #if defined __ARMVFP__
128
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129
+  #endif
130
+
131
+#elif defined ( __TMS470__ )
132
+  #if defined __TI__VFP_SUPPORT____
133
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134
+  #endif
135
+
136
+#elif defined ( __TASKING__ )
137
+  #if defined __FPU_VFP__
138
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139
+  #endif
140
+
141
+#elif defined ( __CSMC__ )		/* Cosmic */
142
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
143
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144
+  #endif
145
+#endif
146
+
147
+#include <stdint.h>                      /* standard types definitions                      */
148
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
149
+#include <core_cmFunc.h>                 /* Core Function Access                            */
150
+
151
+#ifdef __cplusplus
152
+}
153
+#endif
154
+
155
+#endif /* __CORE_CM0PLUS_H_GENERIC */
156
+
157
+#ifndef __CMSIS_GENERIC
158
+
159
+#ifndef __CORE_CM0PLUS_H_DEPENDANT
160
+#define __CORE_CM0PLUS_H_DEPENDANT
161
+
162
+#ifdef __cplusplus
163
+ extern "C" {
164
+#endif
165
+
166
+/* check device defines and use defaults */
167
+#if defined __CHECK_DEVICE_DEFINES
168
+  #ifndef __CM0PLUS_REV
169
+    #define __CM0PLUS_REV             0x0000
170
+    #warning "__CM0PLUS_REV not defined in device header file; using default!"
171
+  #endif
172
+
173
+  #ifndef __MPU_PRESENT
174
+    #define __MPU_PRESENT             0
175
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
176
+  #endif
177
+
178
+  #ifndef __VTOR_PRESENT
179
+    #define __VTOR_PRESENT            0
180
+    #warning "__VTOR_PRESENT not defined in device header file; using default!"
181
+  #endif
182
+
183
+  #ifndef __NVIC_PRIO_BITS
184
+    #define __NVIC_PRIO_BITS          2
185
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
186
+  #endif
187
+
188
+  #ifndef __Vendor_SysTickConfig
189
+    #define __Vendor_SysTickConfig    0
190
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
191
+  #endif
192
+#endif
193
+
194
+/* IO definitions (access restrictions to peripheral registers) */
195
+/**
196
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
197
+
198
+    <strong>IO Type Qualifiers</strong> are used
199
+    \li to specify the access to peripheral variables.
200
+    \li for automatic generation of peripheral register debug information.
201
+*/
202
+#ifdef __cplusplus
203
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
204
+#else
205
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
206
+#endif
207
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
208
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
209
+
210
+/*@} end of group Cortex-M0+ */
211
+
212
+
213
+
214
+/*******************************************************************************
215
+ *                 Register Abstraction
216
+  Core Register contain:
217
+  - Core Register
218
+  - Core NVIC Register
219
+  - Core SCB Register
220
+  - Core SysTick Register
221
+  - Core MPU Register
222
+ ******************************************************************************/
223
+/** \defgroup CMSIS_core_register Defines and Type Definitions
224
+    \brief Type definitions and defines for Cortex-M processor based devices.
225
+*/
226
+
227
+/** \ingroup    CMSIS_core_register
228
+    \defgroup   CMSIS_CORE  Status and Control Registers
229
+    \brief  Core Register type definitions.
230
+  @{
231
+ */
232
+
233
+/** \brief  Union type to access the Application Program Status Register (APSR).
234
+ */
235
+typedef union
236
+{
237
+  struct
238
+  {
239
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
240
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
241
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
242
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
243
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
244
+  } b;                                   /*!< Structure used for bit  access                  */
245
+  uint32_t w;                            /*!< Type      used for word access                  */
246
+} APSR_Type;
247
+
248
+/* APSR Register Definitions */
249
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
250
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
251
+
252
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
253
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
254
+
255
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
256
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
257
+
258
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
259
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
260
+
261
+
262
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
263
+ */
264
+typedef union
265
+{
266
+  struct
267
+  {
268
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
269
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
270
+  } b;                                   /*!< Structure used for bit  access                  */
271
+  uint32_t w;                            /*!< Type      used for word access                  */
272
+} IPSR_Type;
273
+
274
+/* IPSR Register Definitions */
275
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
276
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
277
+
278
+
279
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
280
+ */
281
+typedef union
282
+{
283
+  struct
284
+  {
285
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
286
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
287
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
288
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
289
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
290
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
291
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
292
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
293
+  } b;                                   /*!< Structure used for bit  access                  */
294
+  uint32_t w;                            /*!< Type      used for word access                  */
295
+} xPSR_Type;
296
+
297
+/* xPSR Register Definitions */
298
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
299
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
300
+
301
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
302
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
303
+
304
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
305
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
306
+
307
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
308
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
309
+
310
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
311
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
312
+
313
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
314
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
315
+
316
+
317
+/** \brief  Union type to access the Control Registers (CONTROL).
318
+ */
319
+typedef union
320
+{
321
+  struct
322
+  {
323
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
324
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
325
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
326
+  } b;                                   /*!< Structure used for bit  access                  */
327
+  uint32_t w;                            /*!< Type      used for word access                  */
328
+} CONTROL_Type;
329
+
330
+/* CONTROL Register Definitions */
331
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
332
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
333
+
334
+#define CONTROL_nPRIV_Pos                   0                                             /*!< CONTROL: nPRIV Position */
335
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
336
+
337
+/*@} end of group CMSIS_CORE */
338
+
339
+
340
+/** \ingroup    CMSIS_core_register
341
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
342
+    \brief      Type definitions for the NVIC Registers
343
+  @{
344
+ */
345
+
346
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
347
+ */
348
+typedef struct
349
+{
350
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
351
+       uint32_t RESERVED0[31];
352
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
353
+       uint32_t RSERVED1[31];
354
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
355
+       uint32_t RESERVED2[31];
356
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
357
+       uint32_t RESERVED3[31];
358
+       uint32_t RESERVED4[64];
359
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
360
+}  NVIC_Type;
361
+
362
+/*@} end of group CMSIS_NVIC */
363
+
364
+
365
+/** \ingroup  CMSIS_core_register
366
+    \defgroup CMSIS_SCB     System Control Block (SCB)
367
+    \brief      Type definitions for the System Control Block Registers
368
+  @{
369
+ */
370
+
371
+/** \brief  Structure type to access the System Control Block (SCB).
372
+ */
373
+typedef struct
374
+{
375
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
376
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
377
+#if (__VTOR_PRESENT == 1)
378
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
379
+#else
380
+       uint32_t RESERVED0;
381
+#endif
382
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
383
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
384
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
385
+       uint32_t RESERVED1;
386
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
387
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
388
+} SCB_Type;
389
+
390
+/* SCB CPUID Register Definitions */
391
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
392
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
393
+
394
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
395
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
396
+
397
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
398
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
399
+
400
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
401
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
402
+
403
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
404
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
405
+
406
+/* SCB Interrupt Control State Register Definitions */
407
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
408
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
409
+
410
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
411
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
412
+
413
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
414
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
415
+
416
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
417
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
418
+
419
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
420
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
421
+
422
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
423
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
424
+
425
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
426
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
427
+
428
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
429
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
430
+
431
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
432
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
433
+
434
+#if (__VTOR_PRESENT == 1)
435
+/* SCB Interrupt Control State Register Definitions */
436
+#define SCB_VTOR_TBLOFF_Pos                 8                                             /*!< SCB VTOR: TBLOFF Position */
437
+#define SCB_VTOR_TBLOFF_Msk                (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
438
+#endif
439
+
440
+/* SCB Application Interrupt and Reset Control Register Definitions */
441
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
442
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
443
+
444
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
445
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
446
+
447
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
448
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
449
+
450
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
451
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
452
+
453
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
454
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
455
+
456
+/* SCB System Control Register Definitions */
457
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
458
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
459
+
460
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
461
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
462
+
463
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
464
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
465
+
466
+/* SCB Configuration Control Register Definitions */
467
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
468
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
469
+
470
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
471
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
472
+
473
+/* SCB System Handler Control and State Register Definitions */
474
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
475
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
476
+
477
+/*@} end of group CMSIS_SCB */
478
+
479
+
480
+/** \ingroup  CMSIS_core_register
481
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
482
+    \brief      Type definitions for the System Timer Registers.
483
+  @{
484
+ */
485
+
486
+/** \brief  Structure type to access the System Timer (SysTick).
487
+ */
488
+typedef struct
489
+{
490
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
491
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
492
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
493
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
494
+} SysTick_Type;
495
+
496
+/* SysTick Control / Status Register Definitions */
497
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
498
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
499
+
500
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
501
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
502
+
503
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
504
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
505
+
506
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
507
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
508
+
509
+/* SysTick Reload Register Definitions */
510
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
511
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
512
+
513
+/* SysTick Current Register Definitions */
514
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
515
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
516
+
517
+/* SysTick Calibration Register Definitions */
518
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
519
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
520
+
521
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
522
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
523
+
524
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
525
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
526
+
527
+/*@} end of group CMSIS_SysTick */
528
+
529
+#if (__MPU_PRESENT == 1)
530
+/** \ingroup  CMSIS_core_register
531
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
532
+    \brief      Type definitions for the Memory Protection Unit (MPU)
533
+  @{
534
+ */
535
+
536
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
537
+ */
538
+typedef struct
539
+{
540
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
541
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
542
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
543
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
544
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
545
+} MPU_Type;
546
+
547
+/* MPU Type Register */
548
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
549
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
550
+
551
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
552
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
553
+
554
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
555
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
556
+
557
+/* MPU Control Register */
558
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
559
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
560
+
561
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
562
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
563
+
564
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
565
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
566
+
567
+/* MPU Region Number Register */
568
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
569
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
570
+
571
+/* MPU Region Base Address Register */
572
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
573
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
574
+
575
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
576
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
577
+
578
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
579
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
580
+
581
+/* MPU Region Attribute and Size Register */
582
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
583
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
584
+
585
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
586
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
587
+
588
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
589
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
590
+
591
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
592
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
593
+
594
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
595
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
596
+
597
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
598
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
599
+
600
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
601
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
602
+
603
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
604
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
605
+
606
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
607
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
608
+
609
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
610
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
611
+
612
+/*@} end of group CMSIS_MPU */
613
+#endif
614
+
615
+
616
+/** \ingroup  CMSIS_core_register
617
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
618
+    \brief      Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
619
+                are only accessible over DAP and not via processor. Therefore
620
+                they are not covered by the Cortex-M0 header file.
621
+  @{
622
+ */
623
+/*@} end of group CMSIS_CoreDebug */
624
+
625
+
626
+/** \ingroup    CMSIS_core_register
627
+    \defgroup   CMSIS_core_base     Core Definitions
628
+    \brief      Definitions for base addresses, unions, and structures.
629
+  @{
630
+ */
631
+
632
+/* Memory mapping of Cortex-M0+ Hardware */
633
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
634
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
635
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
636
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
637
+
638
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
639
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
640
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
641
+
642
+#if (__MPU_PRESENT == 1)
643
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
644
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
645
+#endif
646
+
647
+/*@} */
648
+
649
+
650
+
651
+/*******************************************************************************
652
+ *                Hardware Abstraction Layer
653
+  Core Function Interface contains:
654
+  - Core NVIC Functions
655
+  - Core SysTick Functions
656
+  - Core Register Access Functions
657
+ ******************************************************************************/
658
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
659
+*/
660
+
661
+
662
+
663
+/* ##########################   NVIC functions  #################################### */
664
+/** \ingroup  CMSIS_Core_FunctionInterface
665
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
666
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
667
+    @{
668
+ */
669
+
670
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
671
+/* The following MACROS handle generation of the register offset and byte masks */
672
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
673
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
674
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
675
+
676
+
677
+/** \brief  Enable External Interrupt
678
+
679
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
680
+
681
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
682
+ */
683
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
684
+{
685
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
686
+}
687
+
688
+
689
+/** \brief  Disable External Interrupt
690
+
691
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
692
+
693
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
694
+ */
695
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
696
+{
697
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
698
+}
699
+
700
+
701
+/** \brief  Get Pending Interrupt
702
+
703
+    The function reads the pending register in the NVIC and returns the pending bit
704
+    for the specified interrupt.
705
+
706
+    \param [in]      IRQn  Interrupt number.
707
+
708
+    \return             0  Interrupt status is not pending.
709
+    \return             1  Interrupt status is pending.
710
+ */
711
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
712
+{
713
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
714
+}
715
+
716
+
717
+/** \brief  Set Pending Interrupt
718
+
719
+    The function sets the pending bit of an external interrupt.
720
+
721
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
722
+ */
723
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
724
+{
725
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
726
+}
727
+
728
+
729
+/** \brief  Clear Pending Interrupt
730
+
731
+    The function clears the pending bit of an external interrupt.
732
+
733
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
734
+ */
735
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
736
+{
737
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
738
+}
739
+
740
+
741
+/** \brief  Set Interrupt Priority
742
+
743
+    The function sets the priority of an interrupt.
744
+
745
+    \note The priority cannot be set for every core interrupt.
746
+
747
+    \param [in]      IRQn  Interrupt number.
748
+    \param [in]  priority  Priority to set.
749
+ */
750
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
751
+{
752
+  if((int32_t)(IRQn) < 0) {
753
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
754
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
755
+  }
756
+  else {
757
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
758
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
759
+  }
760
+}
761
+
762
+
763
+/** \brief  Get Interrupt Priority
764
+
765
+    The function reads the priority of an interrupt. The interrupt
766
+    number can be positive to specify an external (device specific)
767
+    interrupt, or negative to specify an internal (core) interrupt.
768
+
769
+
770
+    \param [in]   IRQn  Interrupt number.
771
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
772
+                        priority bits of the microcontroller.
773
+ */
774
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
775
+{
776
+
777
+  if((int32_t)(IRQn) < 0) {
778
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
779
+  }
780
+  else {
781
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
782
+  }
783
+}
784
+
785
+
786
+/** \brief  System Reset
787
+
788
+    The function initiates a system reset request to reset the MCU.
789
+ */
790
+__STATIC_INLINE void NVIC_SystemReset(void)
791
+{
792
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
793
+                                                                  buffered write are completed before reset */
794
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
795
+                 SCB_AIRCR_SYSRESETREQ_Msk);
796
+  __DSB();                                                     /* Ensure completion of memory access */
797
+  while(1) { __NOP(); }                                        /* wait until reset */
798
+}
799
+
800
+/*@} end of CMSIS_Core_NVICFunctions */
801
+
802
+
803
+
804
+/* ##################################    SysTick function  ############################################ */
805
+/** \ingroup  CMSIS_Core_FunctionInterface
806
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
807
+    \brief      Functions that configure the System.
808
+  @{
809
+ */
810
+
811
+#if (__Vendor_SysTickConfig == 0)
812
+
813
+/** \brief  System Tick Configuration
814
+
815
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
816
+    Counter is in free running mode to generate periodic interrupts.
817
+
818
+    \param [in]  ticks  Number of ticks between two interrupts.
819
+
820
+    \return          0  Function succeeded.
821
+    \return          1  Function failed.
822
+
823
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
824
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
825
+    must contain a vendor-specific implementation of this function.
826
+
827
+ */
828
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
829
+{
830
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
831
+
832
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
833
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
834
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
835
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
836
+                   SysTick_CTRL_TICKINT_Msk   |
837
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
838
+  return (0UL);                                                     /* Function successful */
839
+}
840
+
841
+#endif
842
+
843
+/*@} end of CMSIS_Core_SysTickFunctions */
844
+
845
+
846
+
847
+
848
+#ifdef __cplusplus
849
+}
850
+#endif
851
+
852
+#endif /* __CORE_CM0PLUS_H_DEPENDANT */
853
+
854
+#endif /* __CMSIS_GENERIC */

+ 1693
- 0
lib/mbed/TARGET_LPC1768/core_cm3.h
File diff suppressed because it is too large
View File


+ 1858
- 0
lib/mbed/TARGET_LPC1768/core_cm4.h
File diff suppressed because it is too large
View File


+ 673
- 0
lib/mbed/TARGET_LPC1768/core_cm4_simd.h View File

@@ -0,0 +1,673 @@
1
+/**************************************************************************//**
2
+ * @file     core_cm4_simd.h
3
+ * @brief    CMSIS Cortex-M4 SIMD Header File
4
+ * @version  V3.20
5
+ * @date     25. February 2013
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2013 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#ifdef __cplusplus
39
+ extern "C" {
40
+#endif
41
+
42
+#ifndef __CORE_CM4_SIMD_H
43
+#define __CORE_CM4_SIMD_H
44
+
45
+
46
+/*******************************************************************************
47
+ *                Hardware Abstraction Layer
48
+ ******************************************************************************/
49
+
50
+
51
+/* ###################  Compiler specific Intrinsics  ########################### */
52
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
53
+  Access to dedicated SIMD instructions
54
+  @{
55
+*/
56
+
57
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
58
+/* ARM armcc specific functions */
59
+
60
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
61
+#define __SADD8                           __sadd8
62
+#define __QADD8                           __qadd8
63
+#define __SHADD8                          __shadd8
64
+#define __UADD8                           __uadd8
65
+#define __UQADD8                          __uqadd8
66
+#define __UHADD8                          __uhadd8
67
+#define __SSUB8                           __ssub8
68
+#define __QSUB8                           __qsub8
69
+#define __SHSUB8                          __shsub8
70
+#define __USUB8                           __usub8
71
+#define __UQSUB8                          __uqsub8
72
+#define __UHSUB8                          __uhsub8
73
+#define __SADD16                          __sadd16
74
+#define __QADD16                          __qadd16
75
+#define __SHADD16                         __shadd16
76
+#define __UADD16                          __uadd16
77
+#define __UQADD16                         __uqadd16
78
+#define __UHADD16                         __uhadd16
79
+#define __SSUB16                          __ssub16
80
+#define __QSUB16                          __qsub16
81
+#define __SHSUB16                         __shsub16
82
+#define __USUB16                          __usub16
83
+#define __UQSUB16                         __uqsub16
84
+#define __UHSUB16                         __uhsub16
85
+#define __SASX                            __sasx
86
+#define __QASX                            __qasx
87
+#define __SHASX                           __shasx
88
+#define __UASX                            __uasx
89
+#define __UQASX                           __uqasx
90
+#define __UHASX                           __uhasx
91
+#define __SSAX                            __ssax
92
+#define __QSAX                            __qsax
93
+#define __SHSAX                           __shsax
94
+#define __USAX                            __usax
95
+#define __UQSAX                           __uqsax
96
+#define __UHSAX                           __uhsax
97
+#define __USAD8                           __usad8
98
+#define __USADA8                          __usada8
99
+#define __SSAT16                          __ssat16
100
+#define __USAT16                          __usat16
101
+#define __UXTB16                          __uxtb16
102
+#define __UXTAB16                         __uxtab16
103
+#define __SXTB16                          __sxtb16
104
+#define __SXTAB16                         __sxtab16
105
+#define __SMUAD                           __smuad
106
+#define __SMUADX                          __smuadx
107
+#define __SMLAD                           __smlad
108
+#define __SMLADX                          __smladx
109
+#define __SMLALD                          __smlald
110
+#define __SMLALDX                         __smlaldx
111
+#define __SMUSD                           __smusd
112
+#define __SMUSDX                          __smusdx
113
+#define __SMLSD                           __smlsd
114
+#define __SMLSDX                          __smlsdx
115
+#define __SMLSLD                          __smlsld
116
+#define __SMLSLDX                         __smlsldx
117
+#define __SEL                             __sel
118
+#define __QADD                            __qadd
119
+#define __QSUB                            __qsub
120
+
121
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
122
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
123
+
124
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
125
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
126
+
127
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
128
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
129
+
130
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
131
+
132
+
133
+
134
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
135
+/* IAR iccarm specific functions */
136
+
137
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
138
+#include <cmsis_iar.h>
139
+
140
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
141
+
142
+
143
+
144
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
145
+/* TI CCS specific functions */
146
+
147
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
148
+#include <cmsis_ccs.h>
149
+
150
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
151
+
152
+
153
+
154
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
155
+/* GNU gcc specific functions */
156
+
157
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
158
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
159
+{
160
+  uint32_t result;
161
+
162
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
163
+  return(result);
164
+}
165
+
166
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
167
+{
168
+  uint32_t result;
169
+
170
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
171
+  return(result);
172
+}
173
+
174
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
175
+{
176
+  uint32_t result;
177
+
178
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
179
+  return(result);
180
+}
181
+
182
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
183
+{
184
+  uint32_t result;
185
+
186
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
187
+  return(result);
188
+}
189
+
190
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
191
+{
192
+  uint32_t result;
193
+
194
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
195
+  return(result);
196
+}
197
+
198
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
199
+{
200
+  uint32_t result;
201
+
202
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
203
+  return(result);
204
+}
205
+
206
+
207
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
208
+{
209
+  uint32_t result;
210
+
211
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
212
+  return(result);
213
+}
214
+
215
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
216
+{
217
+  uint32_t result;
218
+
219
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
220
+  return(result);
221
+}
222
+
223
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
224
+{
225
+  uint32_t result;
226
+
227
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
228
+  return(result);
229
+}
230
+
231
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
232
+{
233
+  uint32_t result;
234
+
235
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
236
+  return(result);
237
+}
238
+
239
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
240
+{
241
+  uint32_t result;
242
+
243
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
244
+  return(result);
245
+}
246
+
247
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
248
+{
249
+  uint32_t result;
250
+
251
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
252
+  return(result);
253
+}
254
+
255
+
256
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
257
+{
258
+  uint32_t result;
259
+
260
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
261
+  return(result);
262
+}
263
+
264
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
265
+{
266
+  uint32_t result;
267
+
268
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
269
+  return(result);
270
+}
271
+
272
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
273
+{
274
+  uint32_t result;
275
+
276
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
277
+  return(result);
278
+}
279
+
280
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
281
+{
282
+  uint32_t result;
283
+
284
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
285
+  return(result);
286
+}
287
+
288
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
289
+{
290
+  uint32_t result;
291
+
292
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
293
+  return(result);
294
+}
295
+
296
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
297
+{
298
+  uint32_t result;
299
+
300
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
301
+  return(result);
302
+}
303
+
304
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
305
+{
306
+  uint32_t result;
307
+
308
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
309
+  return(result);
310
+}
311
+
312
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
313
+{
314
+  uint32_t result;
315
+
316
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
317
+  return(result);
318
+}
319
+
320
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
321
+{
322
+  uint32_t result;
323
+
324
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
325
+  return(result);
326
+}
327
+
328
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
329
+{
330
+  uint32_t result;
331
+
332
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
333
+  return(result);
334
+}
335
+
336
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
337
+{
338
+  uint32_t result;
339
+
340
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
341
+  return(result);
342
+}
343
+
344
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
345
+{
346
+  uint32_t result;
347
+
348
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
349
+  return(result);
350
+}
351
+
352
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
353
+{
354
+  uint32_t result;
355
+
356
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
357
+  return(result);
358
+}
359
+
360
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
361
+{
362
+  uint32_t result;
363
+
364
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
365
+  return(result);
366
+}
367
+
368
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
369
+{
370
+  uint32_t result;
371
+
372
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
373
+  return(result);
374
+}
375
+
376
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
377
+{
378
+  uint32_t result;
379
+
380
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
381
+  return(result);
382
+}
383
+
384
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
385
+{
386
+  uint32_t result;
387
+
388
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
389
+  return(result);
390
+}
391
+
392
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
393
+{
394
+  uint32_t result;
395
+
396
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
397
+  return(result);
398
+}
399
+
400
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
401
+{
402
+  uint32_t result;
403
+
404
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
405
+  return(result);
406
+}
407
+
408
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
409
+{
410
+  uint32_t result;
411
+
412
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
413
+  return(result);
414
+}
415
+
416
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
417
+{
418
+  uint32_t result;
419
+
420
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
421
+  return(result);
422
+}
423
+
424
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
425
+{
426
+  uint32_t result;
427
+
428
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
429
+  return(result);
430
+}
431
+
432
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
433
+{
434
+  uint32_t result;
435
+
436
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
437
+  return(result);
438
+}
439
+
440
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
441
+{
442
+  uint32_t result;
443
+
444
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
445
+  return(result);
446
+}
447
+
448
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
449
+{
450
+  uint32_t result;
451
+
452
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
453
+  return(result);
454
+}
455
+
456
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
457
+{
458
+  uint32_t result;
459
+
460
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
461
+  return(result);
462
+}
463
+
464
+#define __SSAT16(ARG1,ARG2) \
465
+({                          \
466
+  uint32_t __RES, __ARG1 = (ARG1); \
467
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
468
+  __RES; \
469
+ })
470
+
471
+#define __USAT16(ARG1,ARG2) \
472
+({                          \
473
+  uint32_t __RES, __ARG1 = (ARG1); \
474
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
475
+  __RES; \
476
+ })
477
+
478
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
479
+{
480
+  uint32_t result;
481
+
482
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
483
+  return(result);
484
+}
485
+
486
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
487
+{
488
+  uint32_t result;
489
+
490
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
491
+  return(result);
492
+}
493
+
494
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
495
+{
496
+  uint32_t result;
497
+
498
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
499
+  return(result);
500
+}
501
+
502
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
503
+{
504
+  uint32_t result;
505
+
506
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
507
+  return(result);
508
+}
509
+
510
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
511
+{
512
+  uint32_t result;
513
+
514
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
515
+  return(result);
516
+}
517
+
518
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
519
+{
520
+  uint32_t result;
521
+
522
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
523
+  return(result);
524
+}
525
+
526
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
527
+{
528
+  uint32_t result;
529
+
530
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
531
+  return(result);
532
+}
533
+
534
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
535
+{
536
+  uint32_t result;
537
+
538
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
539
+  return(result);
540
+}
541
+
542
+#define __SMLALD(ARG1,ARG2,ARG3) \
543
+({ \
544
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
545
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
546
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
547
+ })
548
+
549
+#define __SMLALDX(ARG1,ARG2,ARG3) \
550
+({ \
551
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
552
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
553
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
554
+ })
555
+
556
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
557
+{
558
+  uint32_t result;
559
+
560
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
561
+  return(result);
562
+}
563
+
564
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
565
+{
566
+  uint32_t result;
567
+
568
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
569
+  return(result);
570
+}
571
+
572
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
573
+{
574
+  uint32_t result;
575
+
576
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
577
+  return(result);
578
+}
579
+
580
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
581
+{
582
+  uint32_t result;
583
+
584
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
585
+  return(result);
586
+}
587
+
588
+#define __SMLSLD(ARG1,ARG2,ARG3) \
589
+({ \
590
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
591
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
592
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
593
+ })
594
+
595
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
596
+({ \
597
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
598
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
599
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
600
+ })
601
+
602
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
603
+{
604
+  uint32_t result;
605
+
606
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
607
+  return(result);
608
+}
609
+
610
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
611
+{
612
+  uint32_t result;
613
+
614
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
615
+  return(result);
616
+}
617
+
618
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
619
+{
620
+  uint32_t result;
621
+
622
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
623
+  return(result);
624
+}
625
+
626
+#define __PKHBT(ARG1,ARG2,ARG3) \
627
+({                          \
628
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
629
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
630
+  __RES; \
631
+ })
632
+
633
+#define __PKHTB(ARG1,ARG2,ARG3) \
634
+({                          \
635
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
636
+  if (ARG3 == 0) \
637
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
638
+  else \
639
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
640
+  __RES; \
641
+ })
642
+
643
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
644
+{
645
+ int32_t result;
646
+
647
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
648
+ return(result);
649
+}
650
+
651
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
652
+
653
+
654
+
655
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
656
+/* TASKING carm specific functions */
657
+
658
+
659
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
660
+/* not yet supported */
661
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
662
+
663
+
664
+#endif
665
+
666
+/*@} end of group CMSIS_SIMD_intrinsics */
667
+
668
+
669
+#endif /* __CORE_CM4_SIMD_H */
670
+
671
+#ifdef __cplusplus
672
+}
673
+#endif

+ 2397
- 0
lib/mbed/TARGET_LPC1768/core_cm7.h
File diff suppressed because it is too large
View File


+ 664
- 0
lib/mbed/TARGET_LPC1768/core_cmFunc.h View File

@@ -0,0 +1,664 @@
1
+/**************************************************************************//**
2
+ * @file     core_cmFunc.h
3
+ * @brief    CMSIS Cortex-M Core Function Access Header File
4
+ * @version  V4.10
5
+ * @date     18. March 2015
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2015 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#ifndef __CORE_CMFUNC_H
39
+#define __CORE_CMFUNC_H
40
+
41
+
42
+/* ###########################  Core Function Access  ########################### */
43
+/** \ingroup  CMSIS_Core_FunctionInterface
44
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
45
+  @{
46
+ */
47
+
48
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
49
+/* ARM armcc specific functions */
50
+
51
+#if (__ARMCC_VERSION < 400677)
52
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
53
+#endif
54
+
55
+/* intrinsic void __enable_irq();     */
56
+/* intrinsic void __disable_irq();    */
57
+
58
+/** \brief  Get Control Register
59
+
60
+    This function returns the content of the Control Register.
61
+
62
+    \return               Control Register value
63
+ */
64
+__STATIC_INLINE uint32_t __get_CONTROL(void)
65
+{
66
+  register uint32_t __regControl         __ASM("control");
67
+  return(__regControl);
68
+}
69
+
70
+
71
+/** \brief  Set Control Register
72
+
73
+    This function writes the given value to the Control Register.
74
+
75
+    \param [in]    control  Control Register value to set
76
+ */
77
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
78
+{
79
+  register uint32_t __regControl         __ASM("control");
80
+  __regControl = control;
81
+}
82
+
83
+
84
+/** \brief  Get IPSR Register
85
+
86
+    This function returns the content of the IPSR Register.
87
+
88
+    \return               IPSR Register value
89
+ */
90
+__STATIC_INLINE uint32_t __get_IPSR(void)
91
+{
92
+  register uint32_t __regIPSR          __ASM("ipsr");
93
+  return(__regIPSR);
94
+}
95
+
96
+
97
+/** \brief  Get APSR Register
98
+
99
+    This function returns the content of the APSR Register.
100
+
101
+    \return               APSR Register value
102
+ */
103
+__STATIC_INLINE uint32_t __get_APSR(void)
104
+{
105
+  register uint32_t __regAPSR          __ASM("apsr");
106
+  return(__regAPSR);
107
+}
108
+
109
+
110
+/** \brief  Get xPSR Register
111
+
112
+    This function returns the content of the xPSR Register.
113
+
114
+    \return               xPSR Register value
115
+ */
116
+__STATIC_INLINE uint32_t __get_xPSR(void)
117
+{
118
+  register uint32_t __regXPSR          __ASM("xpsr");
119
+  return(__regXPSR);
120
+}
121
+
122
+
123
+/** \brief  Get Process Stack Pointer
124
+
125
+    This function returns the current value of the Process Stack Pointer (PSP).
126
+
127
+    \return               PSP Register value
128
+ */
129
+__STATIC_INLINE uint32_t __get_PSP(void)
130
+{
131
+  register uint32_t __regProcessStackPointer  __ASM("psp");
132
+  return(__regProcessStackPointer);
133
+}
134
+
135
+
136
+/** \brief  Set Process Stack Pointer
137
+
138
+    This function assigns the given value to the Process Stack Pointer (PSP).
139
+
140
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
141
+ */
142
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
143
+{
144
+  register uint32_t __regProcessStackPointer  __ASM("psp");
145
+  __regProcessStackPointer = topOfProcStack;
146
+}
147
+
148
+
149
+/** \brief  Get Main Stack Pointer
150
+
151
+    This function returns the current value of the Main Stack Pointer (MSP).
152
+
153
+    \return               MSP Register value
154
+ */
155
+__STATIC_INLINE uint32_t __get_MSP(void)
156
+{
157
+  register uint32_t __regMainStackPointer     __ASM("msp");
158
+  return(__regMainStackPointer);
159
+}
160
+
161
+
162
+/** \brief  Set Main Stack Pointer
163
+
164
+    This function assigns the given value to the Main Stack Pointer (MSP).
165
+
166
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
167
+ */
168
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
169
+{
170
+  register uint32_t __regMainStackPointer     __ASM("msp");
171
+  __regMainStackPointer = topOfMainStack;
172
+}
173
+
174
+
175
+/** \brief  Get Priority Mask
176
+
177
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
178
+
179
+    \return               Priority Mask value
180
+ */
181
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
182
+{
183
+  register uint32_t __regPriMask         __ASM("primask");
184
+  return(__regPriMask);
185
+}
186
+
187
+
188
+/** \brief  Set Priority Mask
189
+
190
+    This function assigns the given value to the Priority Mask Register.
191
+
192
+    \param [in]    priMask  Priority Mask
193
+ */
194
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
195
+{
196
+  register uint32_t __regPriMask         __ASM("primask");
197
+  __regPriMask = (priMask);
198
+}
199
+
200
+
201
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
202
+
203
+/** \brief  Enable FIQ
204
+
205
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
206
+    Can only be executed in Privileged modes.
207
+ */
208
+#define __enable_fault_irq                __enable_fiq
209
+
210
+
211
+/** \brief  Disable FIQ
212
+
213
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
214
+    Can only be executed in Privileged modes.
215
+ */
216
+#define __disable_fault_irq               __disable_fiq
217
+
218
+
219
+/** \brief  Get Base Priority
220
+
221
+    This function returns the current value of the Base Priority register.
222
+
223
+    \return               Base Priority register value
224
+ */
225
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
226
+{
227
+  register uint32_t __regBasePri         __ASM("basepri");
228
+  return(__regBasePri);
229
+}
230
+
231
+
232
+/** \brief  Set Base Priority
233
+
234
+    This function assigns the given value to the Base Priority register.
235
+
236
+    \param [in]    basePri  Base Priority value to set
237
+ */
238
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
239
+{
240
+  register uint32_t __regBasePri         __ASM("basepri");
241
+  __regBasePri = (basePri & 0xff);
242
+}
243
+
244
+
245
+/** \brief  Set Base Priority with condition
246
+
247
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
248
+    or the new value increases the BASEPRI priority level.
249
+
250
+    \param [in]    basePri  Base Priority value to set
251
+ */
252
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
253
+{
254
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
255
+  __regBasePriMax = (basePri & 0xff);
256
+}
257
+
258
+
259
+/** \brief  Get Fault Mask
260
+
261
+    This function returns the current value of the Fault Mask register.
262
+
263
+    \return               Fault Mask register value
264
+ */
265
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
266
+{
267
+  register uint32_t __regFaultMask       __ASM("faultmask");
268
+  return(__regFaultMask);
269
+}
270
+
271
+
272
+/** \brief  Set Fault Mask
273
+
274
+    This function assigns the given value to the Fault Mask register.
275
+
276
+    \param [in]    faultMask  Fault Mask value to set
277
+ */
278
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
279
+{
280
+  register uint32_t __regFaultMask       __ASM("faultmask");
281
+  __regFaultMask = (faultMask & (uint32_t)1);
282
+}
283
+
284
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
285
+
286
+
287
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
288
+
289
+/** \brief  Get FPSCR
290
+
291
+    This function returns the current value of the Floating Point Status/Control register.
292
+
293
+    \return               Floating Point Status/Control register value
294
+ */
295
+__STATIC_INLINE uint32_t __get_FPSCR(void)
296
+{
297
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
298
+  register uint32_t __regfpscr         __ASM("fpscr");
299
+  return(__regfpscr);
300
+#else
301
+   return(0);
302
+#endif
303
+}
304
+
305
+
306
+/** \brief  Set FPSCR
307
+
308
+    This function assigns the given value to the Floating Point Status/Control register.
309
+
310
+    \param [in]    fpscr  Floating Point Status/Control value to set
311
+ */
312
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
313
+{
314
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
315
+  register uint32_t __regfpscr         __ASM("fpscr");
316
+  __regfpscr = (fpscr);
317
+#endif
318
+}
319
+
320
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
321
+
322
+
323
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
324
+/* GNU gcc specific functions */
325
+
326
+/** \brief  Enable IRQ Interrupts
327
+
328
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
329
+  Can only be executed in Privileged modes.
330
+ */
331
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
332
+{
333
+  __ASM volatile ("cpsie i" : : : "memory");
334
+}
335
+
336
+
337
+/** \brief  Disable IRQ Interrupts
338
+
339
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
340
+  Can only be executed in Privileged modes.
341
+ */
342
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
343
+{
344
+  __ASM volatile ("cpsid i" : : : "memory");
345
+}
346
+
347
+
348
+/** \brief  Get Control Register
349
+
350
+    This function returns the content of the Control Register.
351
+
352
+    \return               Control Register value
353
+ */
354
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
355
+{
356
+  uint32_t result;
357
+
358
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
359
+  return(result);
360
+}
361
+
362
+
363
+/** \brief  Set Control Register
364
+
365
+    This function writes the given value to the Control Register.
366
+
367
+    \param [in]    control  Control Register value to set
368
+ */
369
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
370
+{
371
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
372
+}
373
+
374
+
375
+/** \brief  Get IPSR Register
376
+
377
+    This function returns the content of the IPSR Register.
378
+
379
+    \return               IPSR Register value
380
+ */
381
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
382
+{
383
+  uint32_t result;
384
+
385
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
386
+  return(result);
387
+}
388
+
389
+
390
+/** \brief  Get APSR Register
391
+
392
+    This function returns the content of the APSR Register.
393
+
394
+    \return               APSR Register value
395
+ */
396
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
397
+{
398
+  uint32_t result;
399
+
400
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
401
+  return(result);
402
+}
403
+
404
+
405
+/** \brief  Get xPSR Register
406
+
407
+    This function returns the content of the xPSR Register.
408
+
409
+    \return               xPSR Register value
410
+ */
411
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
412
+{
413
+  uint32_t result;
414
+
415
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
416
+  return(result);
417
+}
418
+
419
+
420
+/** \brief  Get Process Stack Pointer
421
+
422
+    This function returns the current value of the Process Stack Pointer (PSP).
423
+
424
+    \return               PSP Register value
425
+ */
426
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
427
+{
428
+  register uint32_t result;
429
+
430
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
431
+  return(result);
432
+}
433
+
434
+
435
+/** \brief  Set Process Stack Pointer
436
+
437
+    This function assigns the given value to the Process Stack Pointer (PSP).
438
+
439
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
440
+ */
441
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
442
+{
443
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
444
+}
445
+
446
+
447
+/** \brief  Get Main Stack Pointer
448
+
449
+    This function returns the current value of the Main Stack Pointer (MSP).
450
+
451
+    \return               MSP Register value
452
+ */
453
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
454
+{
455
+  register uint32_t result;
456
+
457
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
458
+  return(result);
459
+}
460
+
461
+
462
+/** \brief  Set Main Stack Pointer
463
+
464
+    This function assigns the given value to the Main Stack Pointer (MSP).
465
+
466
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
467
+ */
468
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
469
+{
470
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
471
+}
472
+
473
+
474
+/** \brief  Get Priority Mask
475
+
476
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
477
+
478
+    \return               Priority Mask value
479
+ */
480
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
481
+{
482
+  uint32_t result;
483
+
484
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
485
+  return(result);
486
+}
487
+
488
+
489
+/** \brief  Set Priority Mask
490
+
491
+    This function assigns the given value to the Priority Mask Register.
492
+
493
+    \param [in]    priMask  Priority Mask
494
+ */
495
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
496
+{
497
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
498
+}
499
+
500
+
501
+#if       (__CORTEX_M >= 0x03)
502
+
503
+/** \brief  Enable FIQ
504
+
505
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
506
+    Can only be executed in Privileged modes.
507
+ */
508
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
509
+{
510
+  __ASM volatile ("cpsie f" : : : "memory");
511
+}
512
+
513
+
514
+/** \brief  Disable FIQ
515
+
516
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
517
+    Can only be executed in Privileged modes.
518
+ */
519
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
520
+{
521
+  __ASM volatile ("cpsid f" : : : "memory");
522
+}
523
+
524
+
525
+/** \brief  Get Base Priority
526
+
527
+    This function returns the current value of the Base Priority register.
528
+
529
+    \return               Base Priority register value
530
+ */
531
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
532
+{
533
+  uint32_t result;
534
+
535
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
536
+  return(result);
537
+}
538
+
539
+
540
+/** \brief  Set Base Priority
541
+
542
+    This function assigns the given value to the Base Priority register.
543
+
544
+    \param [in]    basePri  Base Priority value to set
545
+ */
546
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
547
+{
548
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
549
+}
550
+
551
+
552
+/** \brief  Set Base Priority with condition
553
+
554
+    This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
555
+	or the new value increases the BASEPRI priority level.
556
+
557
+    \param [in]    basePri  Base Priority value to set
558
+ */
559
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
560
+{
561
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
562
+}
563
+
564
+
565
+/** \brief  Get Fault Mask
566
+
567
+    This function returns the current value of the Fault Mask register.
568
+
569
+    \return               Fault Mask register value
570
+ */
571
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
572
+{
573
+  uint32_t result;
574
+
575
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
576
+  return(result);
577
+}
578
+
579
+
580
+/** \brief  Set Fault Mask
581
+
582
+    This function assigns the given value to the Fault Mask register.
583
+
584
+    \param [in]    faultMask  Fault Mask value to set
585
+ */
586
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
587
+{
588
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
589
+}
590
+
591
+#endif /* (__CORTEX_M >= 0x03) */
592
+
593
+
594
+#if       (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
595
+
596
+/** \brief  Get FPSCR
597
+
598
+    This function returns the current value of the Floating Point Status/Control register.
599
+
600
+    \return               Floating Point Status/Control register value
601
+ */
602
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
603
+{
604
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
605
+  uint32_t result;
606
+
607
+  /* Empty asm statement works as a scheduling barrier */
608
+  __ASM volatile ("");
609
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
610
+  __ASM volatile ("");
611
+  return(result);
612
+#else
613
+   return(0);
614
+#endif
615
+}
616
+
617
+
618
+/** \brief  Set FPSCR
619
+
620
+    This function assigns the given value to the Floating Point Status/Control register.
621
+
622
+    \param [in]    fpscr  Floating Point Status/Control value to set
623
+ */
624
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
625
+{
626
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
627
+  /* Empty asm statement works as a scheduling barrier */
628
+  __ASM volatile ("");
629
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
630
+  __ASM volatile ("");
631
+#endif
632
+}
633
+
634
+#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
635
+
636
+
637
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
638
+/* IAR iccarm specific functions */
639
+#include <cmsis_iar.h>
640
+
641
+
642
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
643
+/* TI CCS specific functions */
644
+#include <cmsis_ccs.h>
645
+
646
+
647
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
648
+/* TASKING carm specific functions */
649
+/*
650
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
651
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
652
+ * Including the CMSIS ones.
653
+ */
654
+
655
+
656
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
657
+/* Cosmic specific functions */
658
+#include <cmsis_csm.h>
659
+
660
+#endif
661
+
662
+/*@} end of CMSIS_Core_RegAccFunctions */
663
+
664
+#endif /* __CORE_CMFUNC_H */

+ 916
- 0
lib/mbed/TARGET_LPC1768/core_cmInstr.h View File

@@ -0,0 +1,916 @@
1
+/**************************************************************************//**
2
+ * @file     core_cmInstr.h
3
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
4
+ * @version  V4.10
5
+ * @date     18. March 2015
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2014 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#ifndef __CORE_CMINSTR_H
39
+#define __CORE_CMINSTR_H
40
+
41
+
42
+/* ##########################  Core Instruction Access  ######################### */
43
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
44
+  Access to dedicated instructions
45
+  @{
46
+*/
47
+
48
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
49
+/* ARM armcc specific functions */
50
+
51
+#if (__ARMCC_VERSION < 400677)
52
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
53
+#endif
54
+
55
+
56
+/** \brief  No Operation
57
+
58
+    No Operation does nothing. This instruction can be used for code alignment purposes.
59
+ */
60
+#define __NOP                             __nop
61
+
62
+
63
+/** \brief  Wait For Interrupt
64
+
65
+    Wait For Interrupt is a hint instruction that suspends execution
66
+    until one of a number of events occurs.
67
+ */
68
+#define __WFI                             __wfi
69
+
70
+
71
+/** \brief  Wait For Event
72
+
73
+    Wait For Event is a hint instruction that permits the processor to enter
74
+    a low-power state until one of a number of events occurs.
75
+ */
76
+#define __WFE                             __wfe
77
+
78
+
79
+/** \brief  Send Event
80
+
81
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
82
+ */
83
+#define __SEV                             __sev
84
+
85
+
86
+/** \brief  Instruction Synchronization Barrier
87
+
88
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
89
+    so that all instructions following the ISB are fetched from cache or
90
+    memory, after the instruction has been completed.
91
+ */
92
+#define __ISB() do {\
93
+                   __schedule_barrier();\
94
+                   __isb(0xF);\
95
+                   __schedule_barrier();\
96
+                } while (0)
97
+
98
+/** \brief  Data Synchronization Barrier
99
+
100
+    This function acts as a special kind of Data Memory Barrier.
101
+    It completes when all explicit memory accesses before this instruction complete.
102
+ */
103
+#define __DSB() do {\
104
+                   __schedule_barrier();\
105
+                   __dsb(0xF);\
106
+                   __schedule_barrier();\
107
+                } while (0)
108
+
109
+/** \brief  Data Memory Barrier
110
+
111
+    This function ensures the apparent order of the explicit memory operations before
112
+    and after the instruction, without ensuring their completion.
113
+ */
114
+#define __DMB() do {\
115
+                   __schedule_barrier();\
116
+                   __dmb(0xF);\
117
+                   __schedule_barrier();\
118
+                } while (0)
119
+
120
+/** \brief  Reverse byte order (32 bit)
121
+
122
+    This function reverses the byte order in integer value.
123
+
124
+    \param [in]    value  Value to reverse
125
+    \return               Reversed value
126
+ */
127
+#define __REV                             __rev
128
+
129
+
130
+/** \brief  Reverse byte order (16 bit)
131
+
132
+    This function reverses the byte order in two unsigned short values.
133
+
134
+    \param [in]    value  Value to reverse
135
+    \return               Reversed value
136
+ */
137
+#ifndef __NO_EMBEDDED_ASM
138
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
139
+{
140
+  rev16 r0, r0
141
+  bx lr
142
+}
143
+#endif
144
+
145
+/** \brief  Reverse byte order in signed short value
146
+
147
+    This function reverses the byte order in a signed short value with sign extension to integer.
148
+
149
+    \param [in]    value  Value to reverse
150
+    \return               Reversed value
151
+ */
152
+#ifndef __NO_EMBEDDED_ASM
153
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
154
+{
155
+  revsh r0, r0
156
+  bx lr
157
+}
158
+#endif
159
+
160
+
161
+/** \brief  Rotate Right in unsigned value (32 bit)
162
+
163
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
164
+
165
+    \param [in]    value  Value to rotate
166
+    \param [in]    value  Number of Bits to rotate
167
+    \return               Rotated value
168
+ */
169
+#define __ROR                             __ror
170
+
171
+
172
+/** \brief  Breakpoint
173
+
174
+    This function causes the processor to enter Debug state.
175
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
176
+
177
+    \param [in]    value  is ignored by the processor.
178
+                   If required, a debugger can use it to store additional information about the breakpoint.
179
+ */
180
+#define __BKPT(value)                       __breakpoint(value)
181
+
182
+
183
+/** \brief  Reverse bit order of value
184
+
185
+    This function reverses the bit order of the given value.
186
+
187
+    \param [in]    value  Value to reverse
188
+    \return               Reversed value
189
+ */
190
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
191
+  #define __RBIT                          __rbit
192
+#else
193
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
194
+{
195
+  uint32_t result;
196
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
197
+
198
+  result = value;                      // r will be reversed bits of v; first get LSB of v
199
+  for (value >>= 1; value; value >>= 1)
200
+  {
201
+    result <<= 1;
202
+    result |= value & 1;
203
+    s--;
204
+  }
205
+  result <<= s;                       // shift when v's highest bits are zero
206
+  return(result);
207
+}
208
+#endif
209
+
210
+
211
+/** \brief  Count leading zeros
212
+
213
+    This function counts the number of leading zeros of a data value.
214
+
215
+    \param [in]  value  Value to count the leading zeros
216
+    \return             number of leading zeros in value
217
+ */
218
+#define __CLZ                             __clz
219
+
220
+
221
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
222
+
223
+/** \brief  LDR Exclusive (8 bit)
224
+
225
+    This function executes a exclusive LDR instruction for 8 bit value.
226
+
227
+    \param [in]    ptr  Pointer to data
228
+    \return             value of type uint8_t at (*ptr)
229
+ */
230
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
231
+
232
+
233
+/** \brief  LDR Exclusive (16 bit)
234
+
235
+    This function executes a exclusive LDR instruction for 16 bit values.
236
+
237
+    \param [in]    ptr  Pointer to data
238
+    \return        value of type uint16_t at (*ptr)
239
+ */
240
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
241
+
242
+
243
+/** \brief  LDR Exclusive (32 bit)
244
+
245
+    This function executes a exclusive LDR instruction for 32 bit values.
246
+
247
+    \param [in]    ptr  Pointer to data
248
+    \return        value of type uint32_t at (*ptr)
249
+ */
250
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
251
+
252
+
253
+/** \brief  STR Exclusive (8 bit)
254
+
255
+    This function executes a exclusive STR instruction for 8 bit values.
256
+
257
+    \param [in]  value  Value to store
258
+    \param [in]    ptr  Pointer to location
259
+    \return          0  Function succeeded
260
+    \return          1  Function failed
261
+ */
262
+#define __STREXB(value, ptr)              __strex(value, ptr)
263
+
264
+
265
+/** \brief  STR Exclusive (16 bit)
266
+
267
+    This function executes a exclusive STR instruction for 16 bit values.
268
+
269
+    \param [in]  value  Value to store
270
+    \param [in]    ptr  Pointer to location
271
+    \return          0  Function succeeded
272
+    \return          1  Function failed
273
+ */
274
+#define __STREXH(value, ptr)              __strex(value, ptr)
275
+
276
+
277
+/** \brief  STR Exclusive (32 bit)
278
+
279
+    This function executes a exclusive STR instruction for 32 bit values.
280
+
281
+    \param [in]  value  Value to store
282
+    \param [in]    ptr  Pointer to location
283
+    \return          0  Function succeeded
284
+    \return          1  Function failed
285
+ */
286
+#define __STREXW(value, ptr)              __strex(value, ptr)
287
+
288
+
289
+/** \brief  Remove the exclusive lock
290
+
291
+    This function removes the exclusive lock which is created by LDREX.
292
+
293
+ */
294
+#define __CLREX                           __clrex
295
+
296
+
297
+/** \brief  Signed Saturate
298
+
299
+    This function saturates a signed value.
300
+
301
+    \param [in]  value  Value to be saturated
302
+    \param [in]    sat  Bit position to saturate to (1..32)
303
+    \return             Saturated value
304
+ */
305
+#define __SSAT                            __ssat
306
+
307
+
308
+/** \brief  Unsigned Saturate
309
+
310
+    This function saturates an unsigned value.
311
+
312
+    \param [in]  value  Value to be saturated
313
+    \param [in]    sat  Bit position to saturate to (0..31)
314
+    \return             Saturated value
315
+ */
316
+#define __USAT                            __usat
317
+
318
+
319
+/** \brief  Rotate Right with Extend (32 bit)
320
+
321
+    This function moves each bit of a bitstring right by one bit.
322
+    The carry input is shifted in at the left end of the bitstring.
323
+
324
+    \param [in]    value  Value to rotate
325
+    \return               Rotated value
326
+ */
327
+#ifndef __NO_EMBEDDED_ASM
328
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
329
+{
330
+  rrx r0, r0
331
+  bx lr
332
+}
333
+#endif
334
+
335
+
336
+/** \brief  LDRT Unprivileged (8 bit)
337
+
338
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
339
+
340
+    \param [in]    ptr  Pointer to data
341
+    \return             value of type uint8_t at (*ptr)
342
+ */
343
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
344
+
345
+
346
+/** \brief  LDRT Unprivileged (16 bit)
347
+
348
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
349
+
350
+    \param [in]    ptr  Pointer to data
351
+    \return        value of type uint16_t at (*ptr)
352
+ */
353
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
354
+
355
+
356
+/** \brief  LDRT Unprivileged (32 bit)
357
+
358
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
359
+
360
+    \param [in]    ptr  Pointer to data
361
+    \return        value of type uint32_t at (*ptr)
362
+ */
363
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
364
+
365
+
366
+/** \brief  STRT Unprivileged (8 bit)
367
+
368
+    This function executes a Unprivileged STRT instruction for 8 bit values.
369
+
370
+    \param [in]  value  Value to store
371
+    \param [in]    ptr  Pointer to location
372
+ */
373
+#define __STRBT(value, ptr)               __strt(value, ptr)
374
+
375
+
376
+/** \brief  STRT Unprivileged (16 bit)
377
+
378
+    This function executes a Unprivileged STRT instruction for 16 bit values.
379
+
380
+    \param [in]  value  Value to store
381
+    \param [in]    ptr  Pointer to location
382
+ */
383
+#define __STRHT(value, ptr)               __strt(value, ptr)
384
+
385
+
386
+/** \brief  STRT Unprivileged (32 bit)
387
+
388
+    This function executes a Unprivileged STRT instruction for 32 bit values.
389
+
390
+    \param [in]  value  Value to store
391
+    \param [in]    ptr  Pointer to location
392
+ */
393
+#define __STRT(value, ptr)                __strt(value, ptr)
394
+
395
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
396
+
397
+
398
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
399
+/* GNU gcc specific functions */
400
+
401
+/* Define macros for porting to both thumb1 and thumb2.
402
+ * For thumb1, use low register (r0-r7), specified by constrant "l"
403
+ * Otherwise, use general registers, specified by constrant "r" */
404
+#if defined (__thumb__) && !defined (__thumb2__)
405
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
406
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
407
+#else
408
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
409
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
410
+#endif
411
+
412
+/** \brief  No Operation
413
+
414
+    No Operation does nothing. This instruction can be used for code alignment purposes.
415
+ */
416
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
417
+{
418
+  __ASM volatile ("nop");
419
+}
420
+
421
+
422
+/** \brief  Wait For Interrupt
423
+
424
+    Wait For Interrupt is a hint instruction that suspends execution
425
+    until one of a number of events occurs.
426
+ */
427
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
428
+{
429
+  __ASM volatile ("wfi");
430
+}
431
+
432
+
433
+/** \brief  Wait For Event
434
+
435
+    Wait For Event is a hint instruction that permits the processor to enter
436
+    a low-power state until one of a number of events occurs.
437
+ */
438
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
439
+{
440
+  __ASM volatile ("wfe");
441
+}
442
+
443
+
444
+/** \brief  Send Event
445
+
446
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
447
+ */
448
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
449
+{
450
+  __ASM volatile ("sev");
451
+}
452
+
453
+
454
+/** \brief  Instruction Synchronization Barrier
455
+
456
+    Instruction Synchronization Barrier flushes the pipeline in the processor,
457
+    so that all instructions following the ISB are fetched from cache or
458
+    memory, after the instruction has been completed.
459
+ */
460
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
461
+{
462
+  __ASM volatile ("isb 0xF":::"memory");
463
+}
464
+
465
+
466
+/** \brief  Data Synchronization Barrier
467
+
468
+    This function acts as a special kind of Data Memory Barrier.
469
+    It completes when all explicit memory accesses before this instruction complete.
470
+ */
471
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
472
+{
473
+  __ASM volatile ("dsb 0xF":::"memory");
474
+}
475
+
476
+
477
+/** \brief  Data Memory Barrier
478
+
479
+    This function ensures the apparent order of the explicit memory operations before
480
+    and after the instruction, without ensuring their completion.
481
+ */
482
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
483
+{
484
+  __ASM volatile ("dmb 0xF":::"memory");
485
+}
486
+
487
+
488
+/** \brief  Reverse byte order (32 bit)
489
+
490
+    This function reverses the byte order in integer value.
491
+
492
+    \param [in]    value  Value to reverse
493
+    \return               Reversed value
494
+ */
495
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
496
+{
497
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
498
+  return __builtin_bswap32(value);
499
+#else
500
+  uint32_t result;
501
+
502
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
503
+  return(result);
504
+#endif
505
+}
506
+
507
+
508
+/** \brief  Reverse byte order (16 bit)
509
+
510
+    This function reverses the byte order in two unsigned short values.
511
+
512
+    \param [in]    value  Value to reverse
513
+    \return               Reversed value
514
+ */
515
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
516
+{
517
+  uint32_t result;
518
+
519
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
520
+  return(result);
521
+}
522
+
523
+
524
+/** \brief  Reverse byte order in signed short value
525
+
526
+    This function reverses the byte order in a signed short value with sign extension to integer.
527
+
528
+    \param [in]    value  Value to reverse
529
+    \return               Reversed value
530
+ */
531
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
532
+{
533
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
534
+  return (short)__builtin_bswap16(value);
535
+#else
536
+  uint32_t result;
537
+
538
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
539
+  return(result);
540
+#endif
541
+}
542
+
543
+
544
+/** \brief  Rotate Right in unsigned value (32 bit)
545
+
546
+    This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
547
+
548
+    \param [in]    value  Value to rotate
549
+    \param [in]    value  Number of Bits to rotate
550
+    \return               Rotated value
551
+ */
552
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
553
+{
554
+  return (op1 >> op2) | (op1 << (32 - op2));
555
+}
556
+
557
+
558
+/** \brief  Breakpoint
559
+
560
+    This function causes the processor to enter Debug state.
561
+    Debug tools can use this to investigate system state when the instruction at a particular address is reached.
562
+
563
+    \param [in]    value  is ignored by the processor.
564
+                   If required, a debugger can use it to store additional information about the breakpoint.
565
+ */
566
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
567
+
568
+
569
+/** \brief  Reverse bit order of value
570
+
571
+    This function reverses the bit order of the given value.
572
+
573
+    \param [in]    value  Value to reverse
574
+    \return               Reversed value
575
+ */
576
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
577
+{
578
+  uint32_t result;
579
+
580
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
581
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
582
+#else
583
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end
584
+
585
+  result = value;                      // r will be reversed bits of v; first get LSB of v
586
+  for (value >>= 1; value; value >>= 1)
587
+  {
588
+    result <<= 1;
589
+    result |= value & 1;
590
+    s--;
591
+  }
592
+  result <<= s;                       // shift when v's highest bits are zero
593
+#endif
594
+  return(result);
595
+}
596
+
597
+
598
+/** \brief  Count leading zeros
599
+
600
+    This function counts the number of leading zeros of a data value.
601
+
602
+    \param [in]  value  Value to count the leading zeros
603
+    \return             number of leading zeros in value
604
+ */
605
+#define __CLZ             __builtin_clz
606
+
607
+
608
+#if       (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
609
+
610
+/** \brief  LDR Exclusive (8 bit)
611
+
612
+    This function executes a exclusive LDR instruction for 8 bit value.
613
+
614
+    \param [in]    ptr  Pointer to data
615
+    \return             value of type uint8_t at (*ptr)
616
+ */
617
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
618
+{
619
+    uint32_t result;
620
+
621
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
622
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
623
+#else
624
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
625
+       accepted by assembler. So has to use following less efficient pattern.
626
+    */
627
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
628
+#endif
629
+   return ((uint8_t) result);    /* Add explicit type cast here */
630
+}
631
+
632
+
633
+/** \brief  LDR Exclusive (16 bit)
634
+
635
+    This function executes a exclusive LDR instruction for 16 bit values.
636
+
637
+    \param [in]    ptr  Pointer to data
638
+    \return        value of type uint16_t at (*ptr)
639
+ */
640
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
641
+{
642
+    uint32_t result;
643
+
644
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
645
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
646
+#else
647
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
648
+       accepted by assembler. So has to use following less efficient pattern.
649
+    */
650
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
651
+#endif
652
+   return ((uint16_t) result);    /* Add explicit type cast here */
653
+}
654
+
655
+
656
+/** \brief  LDR Exclusive (32 bit)
657
+
658
+    This function executes a exclusive LDR instruction for 32 bit values.
659
+
660
+    \param [in]    ptr  Pointer to data
661
+    \return        value of type uint32_t at (*ptr)
662
+ */
663
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
664
+{
665
+    uint32_t result;
666
+
667
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
668
+   return(result);
669
+}
670
+
671
+
672
+/** \brief  STR Exclusive (8 bit)
673
+
674
+    This function executes a exclusive STR instruction for 8 bit values.
675
+
676
+    \param [in]  value  Value to store
677
+    \param [in]    ptr  Pointer to location
678
+    \return          0  Function succeeded
679
+    \return          1  Function failed
680
+ */
681
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
682
+{
683
+   uint32_t result;
684
+
685
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
686
+   return(result);
687
+}
688
+
689
+
690
+/** \brief  STR Exclusive (16 bit)
691
+
692
+    This function executes a exclusive STR instruction for 16 bit values.
693
+
694
+    \param [in]  value  Value to store
695
+    \param [in]    ptr  Pointer to location
696
+    \return          0  Function succeeded
697
+    \return          1  Function failed
698
+ */
699
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
700
+{
701
+   uint32_t result;
702
+
703
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
704
+   return(result);
705
+}
706
+
707
+
708
+/** \brief  STR Exclusive (32 bit)
709
+
710
+    This function executes a exclusive STR instruction for 32 bit values.
711
+
712
+    \param [in]  value  Value to store
713
+    \param [in]    ptr  Pointer to location
714
+    \return          0  Function succeeded
715
+    \return          1  Function failed
716
+ */
717
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
718
+{
719
+   uint32_t result;
720
+
721
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
722
+   return(result);
723
+}
724
+
725
+
726
+/** \brief  Remove the exclusive lock
727
+
728
+    This function removes the exclusive lock which is created by LDREX.
729
+
730
+ */
731
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
732
+{
733
+  __ASM volatile ("clrex" ::: "memory");
734
+}
735
+
736
+
737
+/** \brief  Signed Saturate
738
+
739
+    This function saturates a signed value.
740
+
741
+    \param [in]  value  Value to be saturated
742
+    \param [in]    sat  Bit position to saturate to (1..32)
743
+    \return             Saturated value
744
+ */
745
+#define __SSAT(ARG1,ARG2) \
746
+({                          \
747
+  uint32_t __RES, __ARG1 = (ARG1); \
748
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
749
+  __RES; \
750
+ })
751
+
752
+
753
+/** \brief  Unsigned Saturate
754
+
755
+    This function saturates an unsigned value.
756
+
757
+    \param [in]  value  Value to be saturated
758
+    \param [in]    sat  Bit position to saturate to (0..31)
759
+    \return             Saturated value
760
+ */
761
+#define __USAT(ARG1,ARG2) \
762
+({                          \
763
+  uint32_t __RES, __ARG1 = (ARG1); \
764
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
765
+  __RES; \
766
+ })
767
+
768
+
769
+/** \brief  Rotate Right with Extend (32 bit)
770
+
771
+    This function moves each bit of a bitstring right by one bit.
772
+    The carry input is shifted in at the left end of the bitstring.
773
+
774
+    \param [in]    value  Value to rotate
775
+    \return               Rotated value
776
+ */
777
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
778
+{
779
+  uint32_t result;
780
+
781
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
782
+  return(result);
783
+}
784
+
785
+
786
+/** \brief  LDRT Unprivileged (8 bit)
787
+
788
+    This function executes a Unprivileged LDRT instruction for 8 bit value.
789
+
790
+    \param [in]    ptr  Pointer to data
791
+    \return             value of type uint8_t at (*ptr)
792
+ */
793
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)
794
+{
795
+    uint32_t result;
796
+
797
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
798
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );
799
+#else
800
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
801
+       accepted by assembler. So has to use following less efficient pattern.
802
+    */
803
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
804
+#endif
805
+   return ((uint8_t) result);    /* Add explicit type cast here */
806
+}
807
+
808
+
809
+/** \brief  LDRT Unprivileged (16 bit)
810
+
811
+    This function executes a Unprivileged LDRT instruction for 16 bit values.
812
+
813
+    \param [in]    ptr  Pointer to data
814
+    \return        value of type uint16_t at (*ptr)
815
+ */
816
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)
817
+{
818
+    uint32_t result;
819
+
820
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
821
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );
822
+#else
823
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
824
+       accepted by assembler. So has to use following less efficient pattern.
825
+    */
826
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
827
+#endif
828
+   return ((uint16_t) result);    /* Add explicit type cast here */
829
+}
830
+
831
+
832
+/** \brief  LDRT Unprivileged (32 bit)
833
+
834
+    This function executes a Unprivileged LDRT instruction for 32 bit values.
835
+
836
+    \param [in]    ptr  Pointer to data
837
+    \return        value of type uint32_t at (*ptr)
838
+ */
839
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)
840
+{
841
+    uint32_t result;
842
+
843
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );
844
+   return(result);
845
+}
846
+
847
+
848
+/** \brief  STRT Unprivileged (8 bit)
849
+
850
+    This function executes a Unprivileged STRT instruction for 8 bit values.
851
+
852
+    \param [in]  value  Value to store
853
+    \param [in]    ptr  Pointer to location
854
+ */
855
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)
856
+{
857
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
858
+}
859
+
860
+
861
+/** \brief  STRT Unprivileged (16 bit)
862
+
863
+    This function executes a Unprivileged STRT instruction for 16 bit values.
864
+
865
+    \param [in]  value  Value to store
866
+    \param [in]    ptr  Pointer to location
867
+ */
868
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)
869
+{
870
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );
871
+}
872
+
873
+
874
+/** \brief  STRT Unprivileged (32 bit)
875
+
876
+    This function executes a Unprivileged STRT instruction for 32 bit values.
877
+
878
+    \param [in]  value  Value to store
879
+    \param [in]    ptr  Pointer to location
880
+ */
881
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)
882
+{
883
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );
884
+}
885
+
886
+#endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
887
+
888
+
889
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
890
+/* IAR iccarm specific functions */
891
+#include <cmsis_iar.h>
892
+
893
+
894
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
895
+/* TI CCS specific functions */
896
+#include <cmsis_ccs.h>
897
+
898
+
899
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
900
+/* TASKING carm specific functions */
901
+/*
902
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
903
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
904
+ * Including the CMSIS ones.
905
+ */
906
+
907
+
908
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
909
+/* Cosmic specific functions */
910
+#include <cmsis_csm.h>
911
+
912
+#endif
913
+
914
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
915
+
916
+#endif /* __CORE_CMINSTR_H */

+ 697
- 0
lib/mbed/TARGET_LPC1768/core_cmSimd.h View File

@@ -0,0 +1,697 @@
1
+/**************************************************************************//**
2
+ * @file     core_cmSimd.h
3
+ * @brief    CMSIS Cortex-M SIMD Header File
4
+ * @version  V4.10
5
+ * @date     18. March 2015
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2014 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#if defined ( __ICCARM__ )
39
+ #pragma system_include  /* treat file as system include file for MISRA check */
40
+#endif
41
+
42
+#ifndef __CORE_CMSIMD_H
43
+#define __CORE_CMSIMD_H
44
+
45
+#ifdef __cplusplus
46
+ extern "C" {
47
+#endif
48
+
49
+
50
+/*******************************************************************************
51
+ *                Hardware Abstraction Layer
52
+ ******************************************************************************/
53
+
54
+
55
+/* ###################  Compiler specific Intrinsics  ########################### */
56
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
57
+  Access to dedicated SIMD instructions
58
+  @{
59
+*/
60
+
61
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
62
+/* ARM armcc specific functions */
63
+#define __SADD8                           __sadd8
64
+#define __QADD8                           __qadd8
65
+#define __SHADD8                          __shadd8
66
+#define __UADD8                           __uadd8
67
+#define __UQADD8                          __uqadd8
68
+#define __UHADD8                          __uhadd8
69
+#define __SSUB8                           __ssub8
70
+#define __QSUB8                           __qsub8
71
+#define __SHSUB8                          __shsub8
72
+#define __USUB8                           __usub8
73
+#define __UQSUB8                          __uqsub8
74
+#define __UHSUB8                          __uhsub8
75
+#define __SADD16                          __sadd16
76
+#define __QADD16                          __qadd16
77
+#define __SHADD16                         __shadd16
78
+#define __UADD16                          __uadd16
79
+#define __UQADD16                         __uqadd16
80
+#define __UHADD16                         __uhadd16
81
+#define __SSUB16                          __ssub16
82
+#define __QSUB16                          __qsub16
83
+#define __SHSUB16                         __shsub16
84
+#define __USUB16                          __usub16
85
+#define __UQSUB16                         __uqsub16
86
+#define __UHSUB16                         __uhsub16
87
+#define __SASX                            __sasx
88
+#define __QASX                            __qasx
89
+#define __SHASX                           __shasx
90
+#define __UASX                            __uasx
91
+#define __UQASX                           __uqasx
92
+#define __UHASX                           __uhasx
93
+#define __SSAX                            __ssax
94
+#define __QSAX                            __qsax
95
+#define __SHSAX                           __shsax
96
+#define __USAX                            __usax
97
+#define __UQSAX                           __uqsax
98
+#define __UHSAX                           __uhsax
99
+#define __USAD8                           __usad8
100
+#define __USADA8                          __usada8
101
+#define __SSAT16                          __ssat16
102
+#define __USAT16                          __usat16
103
+#define __UXTB16                          __uxtb16
104
+#define __UXTAB16                         __uxtab16
105
+#define __SXTB16                          __sxtb16
106
+#define __SXTAB16                         __sxtab16
107
+#define __SMUAD                           __smuad
108
+#define __SMUADX                          __smuadx
109
+#define __SMLAD                           __smlad
110
+#define __SMLADX                          __smladx
111
+#define __SMLALD                          __smlald
112
+#define __SMLALDX                         __smlaldx
113
+#define __SMUSD                           __smusd
114
+#define __SMUSDX                          __smusdx
115
+#define __SMLSD                           __smlsd
116
+#define __SMLSDX                          __smlsdx
117
+#define __SMLSLD                          __smlsld
118
+#define __SMLSLDX                         __smlsldx
119
+#define __SEL                             __sel
120
+#define __QADD                            __qadd
121
+#define __QSUB                            __qsub
122
+
123
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
124
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
125
+
126
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
127
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
128
+
129
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
130
+                                                      ((int64_t)(ARG3) << 32)      ) >> 32))
131
+
132
+
133
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
134
+/* GNU gcc specific functions */
135
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
136
+{
137
+  uint32_t result;
138
+
139
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
140
+  return(result);
141
+}
142
+
143
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
144
+{
145
+  uint32_t result;
146
+
147
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
148
+  return(result);
149
+}
150
+
151
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
152
+{
153
+  uint32_t result;
154
+
155
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
156
+  return(result);
157
+}
158
+
159
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
160
+{
161
+  uint32_t result;
162
+
163
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
164
+  return(result);
165
+}
166
+
167
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
168
+{
169
+  uint32_t result;
170
+
171
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
172
+  return(result);
173
+}
174
+
175
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
176
+{
177
+  uint32_t result;
178
+
179
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
180
+  return(result);
181
+}
182
+
183
+
184
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
185
+{
186
+  uint32_t result;
187
+
188
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
189
+  return(result);
190
+}
191
+
192
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
193
+{
194
+  uint32_t result;
195
+
196
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
197
+  return(result);
198
+}
199
+
200
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
201
+{
202
+  uint32_t result;
203
+
204
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
205
+  return(result);
206
+}
207
+
208
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
209
+{
210
+  uint32_t result;
211
+
212
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
213
+  return(result);
214
+}
215
+
216
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
217
+{
218
+  uint32_t result;
219
+
220
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
221
+  return(result);
222
+}
223
+
224
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
225
+{
226
+  uint32_t result;
227
+
228
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
229
+  return(result);
230
+}
231
+
232
+
233
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
234
+{
235
+  uint32_t result;
236
+
237
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
238
+  return(result);
239
+}
240
+
241
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
242
+{
243
+  uint32_t result;
244
+
245
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
246
+  return(result);
247
+}
248
+
249
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
250
+{
251
+  uint32_t result;
252
+
253
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
254
+  return(result);
255
+}
256
+
257
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
258
+{
259
+  uint32_t result;
260
+
261
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
262
+  return(result);
263
+}
264
+
265
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
266
+{
267
+  uint32_t result;
268
+
269
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
270
+  return(result);
271
+}
272
+
273
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
274
+{
275
+  uint32_t result;
276
+
277
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
278
+  return(result);
279
+}
280
+
281
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
282
+{
283
+  uint32_t result;
284
+
285
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
286
+  return(result);
287
+}
288
+
289
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
290
+{
291
+  uint32_t result;
292
+
293
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
294
+  return(result);
295
+}
296
+
297
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
298
+{
299
+  uint32_t result;
300
+
301
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
302
+  return(result);
303
+}
304
+
305
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
306
+{
307
+  uint32_t result;
308
+
309
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
310
+  return(result);
311
+}
312
+
313
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
314
+{
315
+  uint32_t result;
316
+
317
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
318
+  return(result);
319
+}
320
+
321
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
322
+{
323
+  uint32_t result;
324
+
325
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
326
+  return(result);
327
+}
328
+
329
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
330
+{
331
+  uint32_t result;
332
+
333
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
334
+  return(result);
335
+}
336
+
337
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
338
+{
339
+  uint32_t result;
340
+
341
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
342
+  return(result);
343
+}
344
+
345
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
346
+{
347
+  uint32_t result;
348
+
349
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
350
+  return(result);
351
+}
352
+
353
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
354
+{
355
+  uint32_t result;
356
+
357
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
358
+  return(result);
359
+}
360
+
361
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
362
+{
363
+  uint32_t result;
364
+
365
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
366
+  return(result);
367
+}
368
+
369
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
370
+{
371
+  uint32_t result;
372
+
373
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
374
+  return(result);
375
+}
376
+
377
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
378
+{
379
+  uint32_t result;
380
+
381
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
382
+  return(result);
383
+}
384
+
385
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
386
+{
387
+  uint32_t result;
388
+
389
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
390
+  return(result);
391
+}
392
+
393
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
394
+{
395
+  uint32_t result;
396
+
397
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
398
+  return(result);
399
+}
400
+
401
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
402
+{
403
+  uint32_t result;
404
+
405
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
406
+  return(result);
407
+}
408
+
409
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
410
+{
411
+  uint32_t result;
412
+
413
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
414
+  return(result);
415
+}
416
+
417
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
418
+{
419
+  uint32_t result;
420
+
421
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
422
+  return(result);
423
+}
424
+
425
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
426
+{
427
+  uint32_t result;
428
+
429
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
430
+  return(result);
431
+}
432
+
433
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
434
+{
435
+  uint32_t result;
436
+
437
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
438
+  return(result);
439
+}
440
+
441
+#define __SSAT16(ARG1,ARG2) \
442
+({                          \
443
+  uint32_t __RES, __ARG1 = (ARG1); \
444
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
445
+  __RES; \
446
+ })
447
+
448
+#define __USAT16(ARG1,ARG2) \
449
+({                          \
450
+  uint32_t __RES, __ARG1 = (ARG1); \
451
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
452
+  __RES; \
453
+ })
454
+
455
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
456
+{
457
+  uint32_t result;
458
+
459
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
460
+  return(result);
461
+}
462
+
463
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
464
+{
465
+  uint32_t result;
466
+
467
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
468
+  return(result);
469
+}
470
+
471
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
472
+{
473
+  uint32_t result;
474
+
475
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
476
+  return(result);
477
+}
478
+
479
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
480
+{
481
+  uint32_t result;
482
+
483
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
484
+  return(result);
485
+}
486
+
487
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
488
+{
489
+  uint32_t result;
490
+
491
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
492
+  return(result);
493
+}
494
+
495
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
496
+{
497
+  uint32_t result;
498
+
499
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
500
+  return(result);
501
+}
502
+
503
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
504
+{
505
+  uint32_t result;
506
+
507
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
508
+  return(result);
509
+}
510
+
511
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
512
+{
513
+  uint32_t result;
514
+
515
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
516
+  return(result);
517
+}
518
+
519
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
520
+{
521
+  union llreg_u{
522
+    uint32_t w32[2];
523
+    uint64_t w64;
524
+  } llr;
525
+  llr.w64 = acc;
526
+
527
+#ifndef __ARMEB__   // Little endian
528
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
529
+#else               // Big endian
530
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
531
+#endif
532
+
533
+  return(llr.w64);
534
+}
535
+
536
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
537
+{
538
+  union llreg_u{
539
+    uint32_t w32[2];
540
+    uint64_t w64;
541
+  } llr;
542
+  llr.w64 = acc;
543
+
544
+#ifndef __ARMEB__   // Little endian
545
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
546
+#else               // Big endian
547
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
548
+#endif
549
+
550
+  return(llr.w64);
551
+}
552
+
553
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
554
+{
555
+  uint32_t result;
556
+
557
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
558
+  return(result);
559
+}
560
+
561
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
562
+{
563
+  uint32_t result;
564
+
565
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
566
+  return(result);
567
+}
568
+
569
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
570
+{
571
+  uint32_t result;
572
+
573
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
574
+  return(result);
575
+}
576
+
577
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
578
+{
579
+  uint32_t result;
580
+
581
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
582
+  return(result);
583
+}
584
+
585
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
586
+{
587
+  union llreg_u{
588
+    uint32_t w32[2];
589
+    uint64_t w64;
590
+  } llr;
591
+  llr.w64 = acc;
592
+
593
+#ifndef __ARMEB__   // Little endian
594
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
595
+#else               // Big endian
596
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
597
+#endif
598
+
599
+  return(llr.w64);
600
+}
601
+
602
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
603
+{
604
+  union llreg_u{
605
+    uint32_t w32[2];
606
+    uint64_t w64;
607
+  } llr;
608
+  llr.w64 = acc;
609
+
610
+#ifndef __ARMEB__   // Little endian
611
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
612
+#else               // Big endian
613
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
614
+#endif
615
+
616
+  return(llr.w64);
617
+}
618
+
619
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
620
+{
621
+  uint32_t result;
622
+
623
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
624
+  return(result);
625
+}
626
+
627
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
628
+{
629
+  uint32_t result;
630
+
631
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
632
+  return(result);
633
+}
634
+
635
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
636
+{
637
+  uint32_t result;
638
+
639
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
640
+  return(result);
641
+}
642
+
643
+#define __PKHBT(ARG1,ARG2,ARG3) \
644
+({                          \
645
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
646
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
647
+  __RES; \
648
+ })
649
+
650
+#define __PKHTB(ARG1,ARG2,ARG3) \
651
+({                          \
652
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
653
+  if (ARG3 == 0) \
654
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
655
+  else \
656
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
657
+  __RES; \
658
+ })
659
+
660
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
661
+{
662
+ int32_t result;
663
+
664
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
665
+ return(result);
666
+}
667
+
668
+
669
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
670
+/* IAR iccarm specific functions */
671
+#include <cmsis_iar.h>
672
+
673
+
674
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
675
+/* TI CCS specific functions */
676
+#include <cmsis_ccs.h>
677
+
678
+
679
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
680
+/* TASKING carm specific functions */
681
+/* not yet supported */
682
+
683
+
684
+#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
685
+/* Cosmic specific functions */
686
+#include <cmsis_csm.h>
687
+
688
+#endif
689
+
690
+/*@} end of group CMSIS_SIMD_intrinsics */
691
+
692
+
693
+#ifdef __cplusplus
694
+}
695
+#endif
696
+
697
+#endif /* __CORE_CMSIMD_H */

+ 864
- 0
lib/mbed/TARGET_LPC1768/core_sc000.h View File

@@ -0,0 +1,864 @@
1
+/**************************************************************************//**
2
+ * @file     core_sc000.h
3
+ * @brief    CMSIS SC000 Core Peripheral Access Layer Header File
4
+ * @version  V4.10
5
+ * @date     18. March 2015
6
+ *
7
+ * @note
8
+ *
9
+ ******************************************************************************/
10
+/* Copyright (c) 2009 - 2015 ARM LIMITED
11
+
12
+   All rights reserved.
13
+   Redistribution and use in source and binary forms, with or without
14
+   modification, are permitted provided that the following conditions are met:
15
+   - Redistributions of source code must retain the above copyright
16
+     notice, this list of conditions and the following disclaimer.
17
+   - Redistributions in binary form must reproduce the above copyright
18
+     notice, this list of conditions and the following disclaimer in the
19
+     documentation and/or other materials provided with the distribution.
20
+   - Neither the name of ARM nor the names of its contributors may be used
21
+     to endorse or promote products derived from this software without
22
+     specific prior written permission.
23
+   *
24
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
+   POSSIBILITY OF SUCH DAMAGE.
35
+   ---------------------------------------------------------------------------*/
36
+
37
+
38
+#if defined ( __ICCARM__ )
39
+ #pragma system_include  /* treat file as system include file for MISRA check */
40
+#endif
41
+
42
+#ifndef __CORE_SC000_H_GENERIC
43
+#define __CORE_SC000_H_GENERIC
44
+
45
+#ifdef __cplusplus
46
+ extern "C" {
47
+#endif
48
+
49
+/** \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
50
+  CMSIS violates the following MISRA-C:2004 rules:
51
+
52
+   \li Required Rule 8.5, object/function definition in header file.<br>
53
+     Function definitions in header files are used to allow 'inlining'.
54
+
55
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56
+     Unions are used for effective representation of core registers.
57
+
58
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
59
+     Function-like macros are used to allow more efficient code.
60
+ */
61
+
62
+
63
+/*******************************************************************************
64
+ *                 CMSIS definitions
65
+ ******************************************************************************/
66
+/** \ingroup SC000
67
+  @{
68
+ */
69
+
70
+/*  CMSIS SC000 definitions */
71
+#define __SC000_CMSIS_VERSION_MAIN  (0x04)                                   /*!< [31:16] CMSIS HAL main version */
72
+#define __SC000_CMSIS_VERSION_SUB   (0x00)                                   /*!< [15:0]  CMSIS HAL sub version  */
73
+#define __SC000_CMSIS_VERSION       ((__SC000_CMSIS_VERSION_MAIN << 16) | \
74
+                                      __SC000_CMSIS_VERSION_SUB          )   /*!< CMSIS HAL version number       */
75
+
76
+#define __CORTEX_SC                 (000)                                       /*!< Cortex secure core             */
77
+
78
+
79
+#if   defined ( __CC_ARM )
80
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
81
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
82
+  #define __STATIC_INLINE  static __inline
83
+
84
+#elif defined ( __GNUC__ )
85
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
86
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
87
+  #define __STATIC_INLINE  static inline
88
+
89
+#elif defined ( __ICCARM__ )
90
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler          */
91
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
92
+  #define __STATIC_INLINE  static inline
93
+
94
+#elif defined ( __TMS470__ )
95
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler       */
96
+  #define __STATIC_INLINE  static inline
97
+
98
+#elif defined ( __TASKING__ )
99
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
100
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
101
+  #define __STATIC_INLINE  static inline
102
+
103
+#elif defined ( __CSMC__ )
104
+  #define __packed
105
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler      */
106
+  #define __INLINE         inline                                    /*use -pc99 on compile line !< inline keyword for COSMIC Compiler   */
107
+  #define __STATIC_INLINE  static inline
108
+
109
+#endif
110
+
111
+/** __FPU_USED indicates whether an FPU is used or not.
112
+    This core does not support an FPU at all
113
+*/
114
+#define __FPU_USED       0
115
+
116
+#if defined ( __CC_ARM )
117
+  #if defined __TARGET_FPU_VFP
118
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
119
+  #endif
120
+
121
+#elif defined ( __GNUC__ )
122
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
123
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
124
+  #endif
125
+
126
+#elif defined ( __ICCARM__ )
127
+  #if defined __ARMVFP__
128
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129
+  #endif
130
+
131
+#elif defined ( __TMS470__ )
132
+  #if defined __TI__VFP_SUPPORT____
133
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134
+  #endif
135
+
136
+#elif defined ( __TASKING__ )
137
+  #if defined __FPU_VFP__
138
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139
+  #endif
140
+
141
+#elif defined ( __CSMC__ )		/* Cosmic */
142
+  #if ( __CSMC__ & 0x400)		// FPU present for parser
143
+    #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144
+  #endif
145
+#endif
146
+
147
+#include <stdint.h>                      /* standard types definitions                      */
148
+#include <core_cmInstr.h>                /* Core Instruction Access                         */
149
+#include <core_cmFunc.h>                 /* Core Function Access                            */
150
+
151
+#ifdef __cplusplus
152
+}
153
+#endif
154
+
155
+#endif /* __CORE_SC000_H_GENERIC */
156
+
157
+#ifndef __CMSIS_GENERIC
158
+
159
+#ifndef __CORE_SC000_H_DEPENDANT
160
+#define __CORE_SC000_H_DEPENDANT
161
+
162
+#ifdef __cplusplus
163
+ extern "C" {
164
+#endif
165
+
166
+/* check device defines and use defaults */
167
+#if defined __CHECK_DEVICE_DEFINES
168
+  #ifndef __SC000_REV
169
+    #define __SC000_REV             0x0000
170
+    #warning "__SC000_REV not defined in device header file; using default!"
171
+  #endif
172
+
173
+  #ifndef __MPU_PRESENT
174
+    #define __MPU_PRESENT             0
175
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
176
+  #endif
177
+
178
+  #ifndef __NVIC_PRIO_BITS
179
+    #define __NVIC_PRIO_BITS          2
180
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
181
+  #endif
182
+
183
+  #ifndef __Vendor_SysTickConfig
184
+    #define __Vendor_SysTickConfig    0
185
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
186
+  #endif
187
+#endif
188
+
189
+/* IO definitions (access restrictions to peripheral registers) */
190
+/**
191
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
192
+
193
+    <strong>IO Type Qualifiers</strong> are used
194
+    \li to specify the access to peripheral variables.
195
+    \li for automatic generation of peripheral register debug information.
196
+*/
197
+#ifdef __cplusplus
198
+  #define   __I     volatile             /*!< Defines 'read only' permissions                 */
199
+#else
200
+  #define   __I     volatile const       /*!< Defines 'read only' permissions                 */
201
+#endif
202
+#define     __O     volatile             /*!< Defines 'write only' permissions                */
203
+#define     __IO    volatile             /*!< Defines 'read / write' permissions              */
204
+
205
+/*@} end of group SC000 */
206
+
207
+
208
+
209
+/*******************************************************************************
210
+ *                 Register Abstraction
211
+  Core Register contain:
212
+  - Core Register
213
+  - Core NVIC Register
214
+  - Core SCB Register
215
+  - Core SysTick Register
216
+  - Core MPU Register
217
+ ******************************************************************************/
218
+/** \defgroup CMSIS_core_register Defines and Type Definitions
219
+    \brief Type definitions and defines for Cortex-M processor based devices.
220
+*/
221
+
222
+/** \ingroup    CMSIS_core_register
223
+    \defgroup   CMSIS_CORE  Status and Control Registers
224
+    \brief  Core Register type definitions.
225
+  @{
226
+ */
227
+
228
+/** \brief  Union type to access the Application Program Status Register (APSR).
229
+ */
230
+typedef union
231
+{
232
+  struct
233
+  {
234
+    uint32_t _reserved0:28;              /*!< bit:  0..27  Reserved                           */
235
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
236
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
237
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
238
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
239
+  } b;                                   /*!< Structure used for bit  access                  */
240
+  uint32_t w;                            /*!< Type      used for word access                  */
241
+} APSR_Type;
242
+
243
+/* APSR Register Definitions */
244
+#define APSR_N_Pos                         31                                             /*!< APSR: N Position */
245
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
246
+
247
+#define APSR_Z_Pos                         30                                             /*!< APSR: Z Position */
248
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
249
+
250
+#define APSR_C_Pos                         29                                             /*!< APSR: C Position */
251
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
252
+
253
+#define APSR_V_Pos                         28                                             /*!< APSR: V Position */
254
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
255
+
256
+
257
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
258
+ */
259
+typedef union
260
+{
261
+  struct
262
+  {
263
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
264
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
265
+  } b;                                   /*!< Structure used for bit  access                  */
266
+  uint32_t w;                            /*!< Type      used for word access                  */
267
+} IPSR_Type;
268
+
269
+/* IPSR Register Definitions */
270
+#define IPSR_ISR_Pos                        0                                             /*!< IPSR: ISR Position */
271
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
272
+
273
+
274
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
275
+ */
276
+typedef union
277
+{
278
+  struct
279
+  {
280
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
281
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
282
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
283
+    uint32_t _reserved1:3;               /*!< bit: 25..27  Reserved                           */
284
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
285
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
286
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
287
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
288
+  } b;                                   /*!< Structure used for bit  access                  */
289
+  uint32_t w;                            /*!< Type      used for word access                  */
290
+} xPSR_Type;
291
+
292
+/* xPSR Register Definitions */
293
+#define xPSR_N_Pos                         31                                             /*!< xPSR: N Position */
294
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
295
+
296
+#define xPSR_Z_Pos                         30                                             /*!< xPSR: Z Position */
297
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
298
+
299
+#define xPSR_C_Pos                         29                                             /*!< xPSR: C Position */
300
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
301
+
302
+#define xPSR_V_Pos                         28                                             /*!< xPSR: V Position */
303
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
304
+
305
+#define xPSR_T_Pos                         24                                             /*!< xPSR: T Position */
306
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
307
+
308
+#define xPSR_ISR_Pos                        0                                             /*!< xPSR: ISR Position */
309
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
310
+
311
+
312
+/** \brief  Union type to access the Control Registers (CONTROL).
313
+ */
314
+typedef union
315
+{
316
+  struct
317
+  {
318
+    uint32_t _reserved0:1;               /*!< bit:      0  Reserved                           */
319
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
320
+    uint32_t _reserved1:30;              /*!< bit:  2..31  Reserved                           */
321
+  } b;                                   /*!< Structure used for bit  access                  */
322
+  uint32_t w;                            /*!< Type      used for word access                  */
323
+} CONTROL_Type;
324
+
325
+/* CONTROL Register Definitions */
326
+#define CONTROL_SPSEL_Pos                   1                                             /*!< CONTROL: SPSEL Position */
327
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
328
+
329
+/*@} end of group CMSIS_CORE */
330
+
331
+
332
+/** \ingroup    CMSIS_core_register
333
+    \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
334
+    \brief      Type definitions for the NVIC Registers
335
+  @{
336
+ */
337
+
338
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
339
+ */
340
+typedef struct
341
+{
342
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
343
+       uint32_t RESERVED0[31];
344
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
345
+       uint32_t RSERVED1[31];
346
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
347
+       uint32_t RESERVED2[31];
348
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
349
+       uint32_t RESERVED3[31];
350
+       uint32_t RESERVED4[64];
351
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
352
+}  NVIC_Type;
353
+
354
+/*@} end of group CMSIS_NVIC */
355
+
356
+
357
+/** \ingroup  CMSIS_core_register
358
+    \defgroup CMSIS_SCB     System Control Block (SCB)
359
+    \brief      Type definitions for the System Control Block Registers
360
+  @{
361
+ */
362
+
363
+/** \brief  Structure type to access the System Control Block (SCB).
364
+ */
365
+typedef struct
366
+{
367
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
368
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
369
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
370
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
371
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
372
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
373
+       uint32_t RESERVED0[1];
374
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
375
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
376
+       uint32_t RESERVED1[154];
377
+  __IO uint32_t SFCR;                    /*!< Offset: 0x290 (R/W)  Security Features Control Register                    */
378
+} SCB_Type;
379
+
380
+/* SCB CPUID Register Definitions */
381
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
382
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
383
+
384
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
385
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
386
+
387
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
388
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
389
+
390
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
391
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
392
+
393
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
394
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
395
+
396
+/* SCB Interrupt Control State Register Definitions */
397
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
398
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
399
+
400
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
401
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
402
+
403
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
404
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
405
+
406
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
407
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
408
+
409
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
410
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
411
+
412
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
413
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
414
+
415
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
416
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
417
+
418
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
419
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
420
+
421
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
422
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
423
+
424
+/* SCB Interrupt Control State Register Definitions */
425
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
426
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
427
+
428
+/* SCB Application Interrupt and Reset Control Register Definitions */
429
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
430
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
431
+
432
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
433
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
434
+
435
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
436
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
437
+
438
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
439
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
440
+
441
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
442
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
443
+
444
+/* SCB System Control Register Definitions */
445
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
446
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
447
+
448
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
449
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
450
+
451
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
452
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
453
+
454
+/* SCB Configuration Control Register Definitions */
455
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
456
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
457
+
458
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
459
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
460
+
461
+/* SCB System Handler Control and State Register Definitions */
462
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
463
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
464
+
465
+/*@} end of group CMSIS_SCB */
466
+
467
+
468
+/** \ingroup  CMSIS_core_register
469
+    \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
470
+    \brief      Type definitions for the System Control and ID Register not in the SCB
471
+  @{
472
+ */
473
+
474
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
475
+ */
476
+typedef struct
477
+{
478
+       uint32_t RESERVED0[2];
479
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
480
+} SCnSCB_Type;
481
+
482
+/* Auxiliary Control Register Definitions */
483
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
484
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
485
+
486
+/*@} end of group CMSIS_SCnotSCB */
487
+
488
+
489
+/** \ingroup  CMSIS_core_register
490
+    \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
491
+    \brief      Type definitions for the System Timer Registers.
492
+  @{
493
+ */
494
+
495
+/** \brief  Structure type to access the System Timer (SysTick).
496
+ */
497
+typedef struct
498
+{
499
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
500
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
501
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
502
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
503
+} SysTick_Type;
504
+
505
+/* SysTick Control / Status Register Definitions */
506
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
507
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
508
+
509
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
510
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
511
+
512
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
513
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
514
+
515
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
516
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
517
+
518
+/* SysTick Reload Register Definitions */
519
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
520
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
521
+
522
+/* SysTick Current Register Definitions */
523
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
524
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
525
+
526
+/* SysTick Calibration Register Definitions */
527
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
528
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
529
+
530
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
531
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
532
+
533
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
534
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
535
+
536
+/*@} end of group CMSIS_SysTick */
537
+
538
+#if (__MPU_PRESENT == 1)
539
+/** \ingroup  CMSIS_core_register
540
+    \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
541
+    \brief      Type definitions for the Memory Protection Unit (MPU)
542
+  @{
543
+ */
544
+
545
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
546
+ */
547
+typedef struct
548
+{
549
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
550
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
551
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
552
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
553
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
554
+} MPU_Type;
555
+
556
+/* MPU Type Register */
557
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
558
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
559
+
560
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
561
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
562
+
563
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
564
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
565
+
566
+/* MPU Control Register */
567
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
568
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
569
+
570
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
571
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
572
+
573
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
574
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
575
+
576
+/* MPU Region Number Register */
577
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
578
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
579
+
580
+/* MPU Region Base Address Register */
581
+#define MPU_RBAR_ADDR_Pos                   8                                             /*!< MPU RBAR: ADDR Position */
582
+#define MPU_RBAR_ADDR_Msk                  (0xFFFFFFUL << MPU_RBAR_ADDR_Pos)              /*!< MPU RBAR: ADDR Mask */
583
+
584
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
585
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
586
+
587
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
588
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
589
+
590
+/* MPU Region Attribute and Size Register */
591
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
592
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
593
+
594
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: ATTRS.XN Position */
595
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
596
+
597
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: ATTRS.AP Position */
598
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
599
+
600
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: ATTRS.TEX Position */
601
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
602
+
603
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: ATTRS.S Position */
604
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
605
+
606
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: ATTRS.C Position */
607
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
608
+
609
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: ATTRS.B Position */
610
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
611
+
612
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
613
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
614
+
615
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
616
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
617
+
618
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
619
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
620
+
621
+/*@} end of group CMSIS_MPU */
622
+#endif
623
+
624
+
625
+/** \ingroup  CMSIS_core_register
626
+    \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
627
+    \brief      SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
628
+                are only accessible over DAP and not via processor. Therefore
629
+                they are not covered by the Cortex-M0 header file.
630
+  @{
631
+ */
632
+/*@} end of group CMSIS_CoreDebug */
633
+
634
+
635
+/** \ingroup    CMSIS_core_register
636
+    \defgroup   CMSIS_core_base     Core Definitions
637
+    \brief      Definitions for base addresses, unions, and structures.
638
+  @{
639
+ */
640
+
641
+/* Memory mapping of SC000 Hardware */
642
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
643
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
644
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
645
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
646
+
647
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
648
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
649
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
650
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
651
+
652
+#if (__MPU_PRESENT == 1)
653
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
654
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
655
+#endif
656
+
657
+/*@} */
658
+
659
+
660
+
661
+/*******************************************************************************
662
+ *                Hardware Abstraction Layer
663
+  Core Function Interface contains:
664
+  - Core NVIC Functions
665
+  - Core SysTick Functions
666
+  - Core Register Access Functions
667
+ ******************************************************************************/
668
+/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
669
+*/
670
+
671
+
672
+
673
+/* ##########################   NVIC functions  #################################### */
674
+/** \ingroup  CMSIS_Core_FunctionInterface
675
+    \defgroup CMSIS_Core_NVICFunctions NVIC Functions
676
+    \brief      Functions that manage interrupts and exceptions via the NVIC.
677
+    @{
678
+ */
679
+
680
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
681
+/* The following MACROS handle generation of the register offset and byte masks */
682
+#define _BIT_SHIFT(IRQn)         (  ((((uint32_t)(int32_t)(IRQn))         )      &  0x03UL) * 8UL)
683
+#define _SHP_IDX(IRQn)           ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >>    2UL)      )
684
+#define _IP_IDX(IRQn)            (   (((uint32_t)(int32_t)(IRQn))                >>    2UL)      )
685
+
686
+
687
+/** \brief  Enable External Interrupt
688
+
689
+    The function enables a device-specific interrupt in the NVIC interrupt controller.
690
+
691
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
692
+ */
693
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
694
+{
695
+  NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
696
+}
697
+
698
+
699
+/** \brief  Disable External Interrupt
700
+
701
+    The function disables a device-specific interrupt in the NVIC interrupt controller.
702
+
703
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
704
+ */
705
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
706
+{
707
+  NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
708
+}
709
+
710
+
711
+/** \brief  Get Pending Interrupt
712
+
713
+    The function reads the pending register in the NVIC and returns the pending bit
714
+    for the specified interrupt.
715
+
716
+    \param [in]      IRQn  Interrupt number.
717
+
718
+    \return             0  Interrupt status is not pending.
719
+    \return             1  Interrupt status is pending.
720
+ */
721
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
722
+{
723
+  return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
724
+}
725
+
726
+
727
+/** \brief  Set Pending Interrupt
728
+
729
+    The function sets the pending bit of an external interrupt.
730
+
731
+    \param [in]      IRQn  Interrupt number. Value cannot be negative.
732
+ */
733
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
734
+{
735
+  NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
736
+}
737
+
738
+
739
+/** \brief  Clear Pending Interrupt
740
+
741
+    The function clears the pending bit of an external interrupt.
742
+
743
+    \param [in]      IRQn  External interrupt number. Value cannot be negative.
744
+ */
745
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
746
+{
747
+  NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
748
+}
749
+
750
+
751
+/** \brief  Set Interrupt Priority
752
+
753
+    The function sets the priority of an interrupt.
754
+
755
+    \note The priority cannot be set for every core interrupt.
756
+
757
+    \param [in]      IRQn  Interrupt number.
758
+    \param [in]  priority  Priority to set.
759
+ */
760
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
761
+{
762
+  if((int32_t)(IRQn) < 0) {
763
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
764
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
765
+  }
766
+  else {
767
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
768
+       (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
769
+  }
770
+}
771
+
772
+
773
+/** \brief  Get Interrupt Priority
774
+
775
+    The function reads the priority of an interrupt. The interrupt
776
+    number can be positive to specify an external (device specific)
777
+    interrupt, or negative to specify an internal (core) interrupt.
778
+
779
+
780
+    \param [in]   IRQn  Interrupt number.
781
+    \return             Interrupt Priority. Value is aligned automatically to the implemented
782
+                        priority bits of the microcontroller.
783
+ */
784
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
785
+{
786
+
787
+  if((int32_t)(IRQn) < 0) {
788
+    return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
789
+  }
790
+  else {
791
+    return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
792
+  }
793
+}
794
+
795
+
796
+/** \brief  System Reset
797
+
798
+    The function initiates a system reset request to reset the MCU.
799
+ */
800
+__STATIC_INLINE void NVIC_SystemReset(void)
801
+{
802
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
803
+                                                                  buffered write are completed before reset */
804
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
805
+                 SCB_AIRCR_SYSRESETREQ_Msk);
806
+  __DSB();                                                     /* Ensure completion of memory access */
807
+  while(1) { __NOP(); }                                        /* wait until reset */
808
+}
809
+
810
+/*@} end of CMSIS_Core_NVICFunctions */
811
+
812
+
813
+
814
+/* ##################################    SysTick function  ############################################ */
815
+/** \ingroup  CMSIS_Core_FunctionInterface
816
+    \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
817
+    \brief      Functions that configure the System.
818
+  @{
819
+ */
820
+
821
+#if (__Vendor_SysTickConfig == 0)
822
+
823
+/** \brief  System Tick Configuration
824
+
825
+    The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
826
+    Counter is in free running mode to generate periodic interrupts.
827
+
828
+    \param [in]  ticks  Number of ticks between two interrupts.
829
+
830
+    \return          0  Function succeeded.
831
+    \return          1  Function failed.
832
+
833
+    \note     When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
834
+    function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
835
+    must contain a vendor-specific implementation of this function.
836
+
837
+ */
838
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
839
+{
840
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);}      /* Reload value impossible */
841
+
842
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
843
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
844
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
845
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
846
+                   SysTick_CTRL_TICKINT_Msk   |
847
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
848
+  return (0UL);                                                     /* Function successful */
849
+}
850
+
851
+#endif
852
+
853
+/*@} end of CMSIS_Core_SysTickFunctions */
854
+
855
+
856
+
857
+
858
+#ifdef __cplusplus
859
+}
860
+#endif
861
+
862
+#endif /* __CORE_SC000_H_DEPENDANT */
863
+
864
+#endif /* __CMSIS_GENERIC */

+ 1675
- 0
lib/mbed/TARGET_LPC1768/core_sc300.h
File diff suppressed because it is too large
View File


+ 60
- 0
lib/mbed/TARGET_LPC1768/system_LPC17xx.h View File

@@ -0,0 +1,60 @@
1
+/******************************************************************************
2
+ * @file:    system_LPC17xx.h
3
+ * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Header File
4
+ *           for the NXP LPC17xx Device Series 
5
+ * @version: V1.02
6
+ * @date:    27. July 2009
7
+ *----------------------------------------------------------------------------
8
+ *
9
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
10
+ *
11
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M3 
12
+ * processor based microcontrollers.  This file can be freely distributed 
13
+ * within development tools that are supporting such ARM based processors. 
14
+ *
15
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
16
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
17
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
18
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
19
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
20
+ *
21
+ ******************************************************************************/
22
+
23
+
24
+#ifndef __SYSTEM_LPC17xx_H
25
+#define __SYSTEM_LPC17xx_H
26
+
27
+#ifdef __cplusplus
28
+ extern "C" {
29
+#endif 
30
+
31
+extern uint32_t SystemCoreClock;     /*!< System Clock Frequency (Core Clock)  */
32
+
33
+
34
+/**
35
+ * Initialize the system
36
+ *
37
+ * @param  none
38
+ * @return none
39
+ *
40
+ * @brief  Setup the microcontroller system.
41
+ *         Initialize the System and update the SystemCoreClock variable.
42
+ */
43
+extern void SystemInit (void);
44
+
45
+/**
46
+ * Update SystemCoreClock variable
47
+ *
48
+ * @param  none
49
+ * @return none
50
+ *
51
+ * @brief  Updates the SystemCoreClock with current core Clock 
52
+ *         retrieved from cpu registers.
53
+ */
54
+extern void SystemCoreClockUpdate (void);
55
+
56
+#ifdef __cplusplus
57
+}
58
+#endif
59
+
60
+#endif /* __SYSTEM_LPC17xx_H */

+ 127
- 0
lib/mbed/Ticker.h View File

@@ -0,0 +1,127 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_TICKER_H
17
+#define MBED_TICKER_H
18
+
19
+#include "TimerEvent.h"
20
+#include "FunctionPointer.h"
21
+
22
+namespace mbed {
23
+
24
+/** A Ticker is used to call a function at a recurring interval
25
+ *
26
+ *  You can use as many seperate Ticker objects as you require.
27
+ *
28
+ * Example:
29
+ * @code
30
+ * // Toggle the blinking led after 5 seconds
31
+ *
32
+ * #include "mbed.h"
33
+ *
34
+ * Ticker timer;
35
+ * DigitalOut led1(LED1);
36
+ * DigitalOut led2(LED2);
37
+ *
38
+ * int flip = 0;
39
+ *
40
+ * void attime() {
41
+ *     flip = !flip;
42
+ * }
43
+ *
44
+ * int main() {
45
+ *     timer.attach(&attime, 5);
46
+ *     while(1) {
47
+ *         if(flip == 0) {
48
+ *             led1 = !led1;
49
+ *         } else {
50
+ *             led2 = !led2;
51
+ *         }
52
+ *         wait(0.2);
53
+ *     }
54
+ * }
55
+ * @endcode
56
+ */
57
+class Ticker : public TimerEvent {
58
+
59
+public:
60
+    Ticker() : TimerEvent() {
61
+    }
62
+
63
+    Ticker(const ticker_data_t *data) : TimerEvent(data) {
64
+    }
65
+
66
+    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
67
+     *
68
+     *  @param fptr pointer to the function to be called
69
+     *  @param t the time between calls in seconds
70
+     */
71
+    void attach(void (*fptr)(void), float t) {
72
+        attach_us(fptr, t * 1000000.0f);
73
+    }
74
+
75
+    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
76
+     *
77
+     *  @param tptr pointer to the object to call the member function on
78
+     *  @param mptr pointer to the member function to be called
79
+     *  @param t the time between calls in seconds
80
+     */
81
+    template<typename T>
82
+    void attach(T* tptr, void (T::*mptr)(void), float t) {
83
+        attach_us(tptr, mptr, t * 1000000.0f);
84
+    }
85
+
86
+    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
87
+     *
88
+     *  @param fptr pointer to the function to be called
89
+     *  @param t the time between calls in micro-seconds
90
+     */
91
+    void attach_us(void (*fptr)(void), timestamp_t t) {
92
+        _function.attach(fptr);
93
+        setup(t);
94
+    }
95
+
96
+    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
97
+     *
98
+     *  @param tptr pointer to the object to call the member function on
99
+     *  @param mptr pointer to the member function to be called
100
+     *  @param t the time between calls in micro-seconds
101
+     */
102
+    template<typename T>
103
+    void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {
104
+        _function.attach(tptr, mptr);
105
+        setup(t);
106
+    }
107
+
108
+    virtual ~Ticker() {
109
+        detach();
110
+    }
111
+
112
+    /** Detach the function
113
+     */
114
+    void detach();
115
+
116
+protected:
117
+    void setup(timestamp_t t);
118
+    virtual void handler();
119
+
120
+protected:
121
+    timestamp_t     _delay;     /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
122
+    FunctionPointer _function;  /**< Callback. */
123
+};
124
+
125
+} // namespace mbed
126
+
127
+#endif

+ 59
- 0
lib/mbed/Timeout.h View File

@@ -0,0 +1,59 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_TIMEOUT_H
17
+#define MBED_TIMEOUT_H
18
+
19
+#include "Ticker.h"
20
+
21
+namespace mbed {
22
+
23
+/** A Timeout is used to call a function at a point in the future
24
+ *
25
+ * You can use as many seperate Timeout objects as you require.
26
+ *
27
+ * Example:
28
+ * @code
29
+ * // Blink until timeout.
30
+ *
31
+ * #include "mbed.h"
32
+ *
33
+ * Timeout timeout;
34
+ * DigitalOut led(LED1);
35
+ *
36
+ * int on = 1;
37
+ *
38
+ * void attimeout() {
39
+ *     on = 0;
40
+ * }
41
+ *
42
+ * int main() {
43
+ *     timeout.attach(&attimeout, 5);
44
+ *     while(on) {
45
+ *         led = !led;
46
+ *         wait(0.2);
47
+ *     }
48
+ * }
49
+ * @endcode
50
+ */
51
+class Timeout : public Ticker {
52
+
53
+protected:
54
+    virtual void handler();
55
+};
56
+
57
+} // namespace mbed
58
+
59
+#endif

+ 91
- 0
lib/mbed/Timer.h View File

@@ -0,0 +1,91 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_TIMER_H
17
+#define MBED_TIMER_H
18
+
19
+#include "platform.h"
20
+#include "ticker_api.h"
21
+
22
+namespace mbed {
23
+
24
+/** A general purpose timer
25
+ *
26
+ * Example:
27
+ * @code
28
+ * // Count the time to toggle a LED
29
+ *
30
+ * #include "mbed.h"
31
+ *
32
+ * Timer timer;
33
+ * DigitalOut led(LED1);
34
+ * int begin, end;
35
+ *
36
+ * int main() {
37
+ *     timer.start();
38
+ *     begin = timer.read_us();
39
+ *     led = !led;
40
+ *     end = timer.read_us();
41
+ *     printf("Toggle the led takes %d us", end - begin);
42
+ * }
43
+ * @endcode
44
+ */
45
+class Timer {
46
+
47
+public:
48
+    Timer();
49
+    Timer(const ticker_data_t *data);
50
+
51
+    /** Start the timer
52
+     */
53
+    void start();
54
+
55
+    /** Stop the timer
56
+     */
57
+    void stop();
58
+
59
+    /** Reset the timer to 0.
60
+     *
61
+     * If it was already counting, it will continue
62
+     */
63
+    void reset();
64
+
65
+    /** Get the time passed in seconds
66
+     */
67
+    float read();
68
+
69
+    /** Get the time passed in mili-seconds
70
+     */
71
+    int read_ms();
72
+
73
+    /** Get the time passed in micro-seconds
74
+     */
75
+    int read_us();
76
+
77
+#ifdef MBED_OPERATORS
78
+    operator float();
79
+#endif
80
+
81
+protected:
82
+    int slicetime();
83
+    int _running;          // whether the timer is running
84
+    unsigned int _start;   // the start time of the latest slice
85
+    int _time;             // any accumulated time from previous slices
86
+    const ticker_data_t *_ticker_data;
87
+};
88
+
89
+} // namespace mbed
90
+
91
+#endif

+ 56
- 0
lib/mbed/TimerEvent.h View File

@@ -0,0 +1,56 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_TIMEREVENT_H
17
+#define MBED_TIMEREVENT_H
18
+
19
+#include "ticker_api.h"
20
+#include "us_ticker_api.h"
21
+
22
+namespace mbed {
23
+
24
+/** Base abstraction for timer interrupts
25
+*/
26
+class TimerEvent {
27
+public:
28
+    TimerEvent();
29
+    TimerEvent(const ticker_data_t *data);
30
+
31
+    /** The handler registered with the underlying timer interrupt
32
+     */
33
+    static void irq(uint32_t id);
34
+
35
+    /** Destruction removes it...
36
+     */
37
+    virtual ~TimerEvent();
38
+
39
+protected:
40
+    // The handler called to service the timer event of the derived class
41
+    virtual void handler() = 0;
42
+
43
+    // insert in to linked list
44
+    void insert(timestamp_t timestamp);
45
+
46
+    // remove from linked list, if in it
47
+    void remove();
48
+
49
+    ticker_event_t event;
50
+
51
+    const ticker_data_t *_ticker_data;
52
+};
53
+
54
+} // namespace mbed
55
+
56
+#endif

+ 73
- 0
lib/mbed/Transaction.h View File

@@ -0,0 +1,73 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_TRANSACTION_H
17
+#define MBED_TRANSACTION_H
18
+
19
+#include "platform.h"
20
+#include "FunctionPointer.h"
21
+
22
+namespace mbed {
23
+
24
+/** Transaction structure
25
+ */
26
+typedef struct {
27
+    void *tx_buffer;           /**< Tx buffer */
28
+    size_t tx_length;          /**< Length of Tx buffer*/
29
+    void *rx_buffer;           /**< Rx buffer */
30
+    size_t rx_length;          /**< Length of Rx buffer */
31
+    uint32_t event;            /**< Event for a transaction */
32
+    event_callback_t callback; /**< User's callback */
33
+    uint8_t width;             /**< Buffer's word width (8, 16, 32, 64) */
34
+} transaction_t;
35
+
36
+/** Transaction class defines a transaction.
37
+ */
38
+template<typename Class>
39
+class Transaction {
40
+public:
41
+    Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
42
+    }
43
+
44
+    Transaction() : _obj(), _data() {
45
+    }
46
+
47
+    ~Transaction() {
48
+    }
49
+
50
+    /** Get object's instance for the transaction
51
+     *
52
+     * @return The object which was stored
53
+     */
54
+    Class* get_object() {
55
+        return _obj;
56
+    }
57
+
58
+    /** Get the transaction
59
+     *
60
+     * @return The transaction which was stored
61
+     */
62
+    transaction_t* get_transaction() {
63
+        return &_data;
64
+    }
65
+
66
+private:
67
+    Class* _obj;
68
+    transaction_t _data;
69
+};
70
+
71
+}
72
+
73
+#endif

+ 39
- 0
lib/mbed/analogin_api.h View File

@@ -0,0 +1,39 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ANALOGIN_API_H
17
+#define MBED_ANALOGIN_API_H
18
+
19
+#include "device.h"
20
+
21
+#if DEVICE_ANALOGIN
22
+
23
+#ifdef __cplusplus
24
+extern "C" {
25
+#endif
26
+
27
+typedef struct analogin_s analogin_t;
28
+
29
+void     analogin_init    (analogin_t *obj, PinName pin);
30
+float    analogin_read    (analogin_t *obj);
31
+uint16_t analogin_read_u16(analogin_t *obj);
32
+
33
+#ifdef __cplusplus
34
+}
35
+#endif
36
+
37
+#endif
38
+
39
+#endif

+ 42
- 0
lib/mbed/analogout_api.h View File

@@ -0,0 +1,42 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ANALOGOUT_API_H
17
+#define MBED_ANALOGOUT_API_H
18
+
19
+#include "device.h"
20
+
21
+#if DEVICE_ANALOGOUT
22
+
23
+#ifdef __cplusplus
24
+extern "C" {
25
+#endif
26
+
27
+typedef struct dac_s dac_t;
28
+
29
+void     analogout_init     (dac_t *obj, PinName pin);
30
+void     analogout_free     (dac_t *obj);
31
+void     analogout_write    (dac_t *obj, float value);
32
+void     analogout_write_u16(dac_t *obj, uint16_t value);
33
+float    analogout_read     (dac_t *obj);
34
+uint16_t analogout_read_u16 (dac_t *obj);
35
+
36
+#ifdef __cplusplus
37
+}
38
+#endif
39
+
40
+#endif
41
+
42
+#endif

+ 30
- 0
lib/mbed/buffer.h View File

@@ -0,0 +1,30 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2014-2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_BUFFER_H
17
+#define MBED_BUFFER_H
18
+
19
+#include <stddef.h>
20
+
21
+/** Generic buffer structure
22
+ */
23
+typedef struct buffer_s {
24
+    void    *buffer; /**< the pointer to a buffer */
25
+    size_t   length; /**< the buffer length */
26
+    size_t   pos;    /**< actual buffer position */
27
+    uint8_t  width;  /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
28
+} buffer_t;
29
+
30
+#endif

+ 80
- 0
lib/mbed/can_api.h View File

@@ -0,0 +1,80 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2016 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_CAN_API_H
17
+#define MBED_CAN_API_H
18
+
19
+#include "device.h"
20
+
21
+#if DEVICE_CAN
22
+
23
+#include "PinNames.h"
24
+#include "PeripheralNames.h"
25
+#include "can_helper.h"
26
+
27
+#ifdef __cplusplus
28
+extern "C" {
29
+#endif
30
+
31
+typedef enum {
32
+    IRQ_RX,
33
+    IRQ_TX,
34
+    IRQ_ERROR,
35
+    IRQ_OVERRUN,
36
+    IRQ_WAKEUP,
37
+    IRQ_PASSIVE,
38
+    IRQ_ARB,
39
+    IRQ_BUS,
40
+    IRQ_READY
41
+} CanIrqType;
42
+
43
+
44
+typedef enum {
45
+    MODE_RESET,
46
+    MODE_NORMAL,
47
+    MODE_SILENT,
48
+    MODE_TEST_LOCAL,
49
+    MODE_TEST_GLOBAL,
50
+    MODE_TEST_SILENT
51
+} CanMode;
52
+
53
+typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
54
+
55
+typedef struct can_s can_t;
56
+
57
+void          can_init     (can_t *obj, PinName rd, PinName td);
58
+void          can_free     (can_t *obj);
59
+int           can_frequency(can_t *obj, int hz);
60
+
61
+void          can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
62
+void          can_irq_free (can_t *obj);
63
+void          can_irq_set  (can_t *obj, CanIrqType irq, uint32_t enable);
64
+
65
+int           can_write    (can_t *obj, CAN_Message, int cc);
66
+int           can_read     (can_t *obj, CAN_Message *msg, int handle);
67
+int           can_mode     (can_t *obj, CanMode mode);
68
+int           can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
69
+void          can_reset    (can_t *obj);
70
+unsigned char can_rderror  (can_t *obj);
71
+unsigned char can_tderror  (can_t *obj);
72
+void          can_monitor  (can_t *obj, int silent);
73
+
74
+#ifdef __cplusplus
75
+};
76
+#endif
77
+
78
+#endif    // MBED_CAN_API_H
79
+
80
+#endif

+ 53
- 0
lib/mbed/can_helper.h View File

@@ -0,0 +1,53 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_CAN_HELPER_H
17
+#define MBED_CAN_HELPER_H
18
+
19
+#if DEVICE_CAN
20
+
21
+#ifdef __cplusplus
22
+extern "C" {
23
+#endif
24
+
25
+enum CANFormat {
26
+    CANStandard = 0,
27
+    CANExtended = 1,
28
+    CANAny = 2
29
+};
30
+typedef enum CANFormat CANFormat;
31
+
32
+enum CANType {
33
+    CANData   = 0,
34
+    CANRemote = 1
35
+};
36
+typedef enum CANType CANType;
37
+
38
+struct CAN_Message {
39
+    unsigned int   id;                 // 29 bit identifier
40
+    unsigned char  data[8];            // Data field
41
+    unsigned char  len;                // Length of data field in bytes
42
+    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
43
+    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
44
+};
45
+typedef struct CAN_Message CAN_Message;
46
+
47
+#ifdef __cplusplus
48
+};
49
+#endif
50
+
51
+#endif
52
+
53
+#endif // MBED_CAN_HELPER_H

+ 45
- 0
lib/mbed/dma_api.h View File

@@ -0,0 +1,45 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2014-2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_DMA_API_H
17
+#define MBED_DMA_API_H
18
+
19
+#include <stdint.h>
20
+
21
+#define DMA_ERROR_OUT_OF_CHANNELS (-1)
22
+
23
+typedef enum {
24
+    DMA_USAGE_NEVER,
25
+    DMA_USAGE_OPPORTUNISTIC,
26
+    DMA_USAGE_ALWAYS,
27
+    DMA_USAGE_TEMPORARY_ALLOCATED,
28
+    DMA_USAGE_ALLOCATED
29
+} DMAUsage;
30
+
31
+#ifdef __cplusplus
32
+extern "C" {
33
+#endif
34
+
35
+void dma_init(void);
36
+
37
+int dma_channel_allocate(uint32_t capabilities);
38
+
39
+int dma_channel_free(int channelid);
40
+
41
+#ifdef __cplusplus
42
+}
43
+#endif
44
+
45
+#endif

+ 63
- 0
lib/mbed/ethernet_api.h View File

@@ -0,0 +1,63 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ETHERNET_API_H
17
+#define MBED_ETHERNET_API_H
18
+
19
+#include "device.h"
20
+
21
+#if DEVICE_ETHERNET
22
+
23
+#ifdef __cplusplus
24
+extern "C" {
25
+#endif
26
+
27
+// Connection constants
28
+
29
+int ethernet_init(void);
30
+void ethernet_free(void);
31
+
32
+// write size bytes from data to ethernet buffer
33
+// return num bytes written
34
+// or -1 if size is too big
35
+int ethernet_write(const char *data, int size);
36
+
37
+// send ethernet write buffer, returning the packet size sent
38
+int ethernet_send(void);
39
+
40
+// recieve from ethernet buffer, returning packet size, or 0 if no packet
41
+int ethernet_receive(void);
42
+
43
+// read size bytes in to data, return actual num bytes read (0..size)
44
+// if data == NULL, throw the bytes away
45
+int ethernet_read(char *data, int size);
46
+
47
+// get the ethernet address
48
+void ethernet_address(char *mac);
49
+
50
+// see if the link is up
51
+int ethernet_link(void);
52
+
53
+// force link settings
54
+void ethernet_set_link(int speed, int duplex);
55
+
56
+#ifdef __cplusplus
57
+}
58
+#endif
59
+
60
+#endif
61
+
62
+#endif
63
+

+ 57
- 0
lib/mbed/gpio_api.h View File

@@ -0,0 +1,57 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_GPIO_API_H
17
+#define MBED_GPIO_API_H
18
+
19
+#include "device.h"
20
+
21
+#ifdef __cplusplus
22
+extern "C" {
23
+#endif
24
+
25
+/* Set the given pin as GPIO
26
+ * @param pin The pin to be set as GPIO
27
+ * @return The GPIO port mask for this pin
28
+ **/
29
+uint32_t gpio_set(PinName pin);
30
+
31
+/* Checks if gpio object is connected (pin was not initialized with NC)
32
+ * @param pin The pin to be set as GPIO
33
+ * @return 0 if port is initialized with NC
34
+ **/
35
+int gpio_is_connected(const gpio_t *obj);
36
+
37
+/* GPIO object */
38
+void gpio_init(gpio_t *obj, PinName pin);
39
+
40
+void gpio_mode (gpio_t *obj, PinMode mode);
41
+void gpio_dir  (gpio_t *obj, PinDirection direction);
42
+
43
+void gpio_write(gpio_t *obj, int value);
44
+int  gpio_read (gpio_t *obj);
45
+
46
+// the following set of functions are generic and are implemented in the common gpio.c file
47
+void gpio_init_in(gpio_t* gpio, PinName pin);
48
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
49
+void gpio_init_out(gpio_t* gpio, PinName pin);
50
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
51
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
52
+
53
+#ifdef __cplusplus
54
+}
55
+#endif
56
+
57
+#endif

+ 49
- 0
lib/mbed/gpio_irq_api.h View File

@@ -0,0 +1,49 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_GPIO_IRQ_API_H
17
+#define MBED_GPIO_IRQ_API_H
18
+
19
+#include "device.h"
20
+
21
+#if DEVICE_INTERRUPTIN
22
+
23
+#ifdef __cplusplus
24
+extern "C" {
25
+#endif
26
+
27
+typedef enum {
28
+    IRQ_NONE,
29
+    IRQ_RISE,
30
+    IRQ_FALL
31
+} gpio_irq_event;
32
+
33
+typedef struct gpio_irq_s gpio_irq_t;
34
+
35
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
36
+
37
+int  gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
38
+void gpio_irq_free(gpio_irq_t *obj);
39
+void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
40
+void gpio_irq_enable(gpio_irq_t *obj);
41
+void gpio_irq_disable(gpio_irq_t *obj);
42
+
43
+#ifdef __cplusplus
44
+}
45
+#endif
46
+
47
+#endif
48
+
49
+#endif

+ 224
- 0
lib/mbed/i2c_api.h View File

@@ -0,0 +1,224 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_I2C_API_H
17
+#define MBED_I2C_API_H
18
+
19
+#include "device.h"
20
+#include "buffer.h"
21
+#include "dma_api.h"
22
+
23
+#if DEVICE_I2C
24
+
25
+/**
26
+ * @defgroup I2CEvents I2C Events Macros
27
+ *
28
+ * @{
29
+ */
30
+#define I2C_EVENT_ERROR               (1 << 1)
31
+#define I2C_EVENT_ERROR_NO_SLAVE      (1 << 2)
32
+#define I2C_EVENT_TRANSFER_COMPLETE   (1 << 3)
33
+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
34
+#define I2C_EVENT_ALL                 (I2C_EVENT_ERROR |  I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
35
+
36
+/**@}*/
37
+
38
+#if DEVICE_I2C_ASYNCH
39
+/** Asynch i2c hal structure
40
+ */
41
+typedef struct {
42
+    struct i2c_s    i2c;     /**< Target specific i2c structure */
43
+    struct buffer_s tx_buff; /**< Tx buffer */
44
+    struct buffer_s rx_buff; /**< Rx buffer */
45
+} i2c_t;
46
+
47
+#else
48
+/** Non-asynch i2c hal structure
49
+ */
50
+typedef struct i2c_s i2c_t;
51
+
52
+#endif
53
+
54
+enum {
55
+  I2C_ERROR_NO_SLAVE = -1,
56
+  I2C_ERROR_BUS_BUSY = -2
57
+};
58
+
59
+#ifdef __cplusplus
60
+extern "C" {
61
+#endif
62
+
63
+/**
64
+ * \defgroup GeneralI2C I2C Configuration Functions
65
+ * @{
66
+ */
67
+
68
+/** Initialize the I2C peripheral. It sets the default parameters for I2C
69
+ *  peripheral, and configure its specifieds pins.
70
+ *  @param obj  The i2c object
71
+ *  @param sda  The sda pin
72
+ *  @param scl  The scl pin
73
+ */
74
+void i2c_init(i2c_t *obj, PinName sda, PinName scl);
75
+
76
+/** Configure the I2C frequency.
77
+ *  @param obj The i2c object
78
+ *  @param hz  Frequency in Hz
79
+ */
80
+void i2c_frequency(i2c_t *obj, int hz);
81
+
82
+/** Send START command.
83
+ *  @param obj The i2c object
84
+ */
85
+int  i2c_start(i2c_t *obj);
86
+
87
+/** Send STOP command.
88
+ *  @param obj The i2c object
89
+ */
90
+int  i2c_stop(i2c_t *obj);
91
+
92
+/** Blocking reading data.
93
+ *  @param obj     The i2c object
94
+ *  @param address 7-bit address (last bit is 1)
95
+ *  @param data    The buffer for receiving
96
+ *  @param length  Number of bytes to read
97
+ *  @param stop    Stop to be generated after the transfer is done
98
+ *  @return Number of read bytes
99
+ */
100
+int  i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
101
+
102
+/** Blocking sending data.
103
+ *  @param obj     The i2c object
104
+ *  @param address 7-bit address (last bit is 0)
105
+ *  @param data    The buffer for sending
106
+ *  @param length  Number of bytes to wrte
107
+ *  @param stop    Stop to be generated after the transfer is done
108
+ *  @return Number of written bytes
109
+ */
110
+int  i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
111
+
112
+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop().
113
+ *  @param obj The i2c object
114
+ */
115
+void i2c_reset(i2c_t *obj);
116
+
117
+/** Read one byte.
118
+ *  @param obj The i2c object
119
+ *  @param last Acknoledge
120
+ *  @return The read byte
121
+ */
122
+int  i2c_byte_read(i2c_t *obj, int last);
123
+
124
+/** Write one byte.
125
+ *  @param obj The i2c object
126
+ *  @param data Byte to be written
127
+ *  @return 1 if NAK was received, 0 if ACK was received, 2 for timeout.
128
+ */
129
+int  i2c_byte_write(i2c_t *obj, int data);
130
+
131
+/**@}*/
132
+
133
+#if DEVICE_I2CSLAVE
134
+
135
+/**
136
+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
137
+ * @{
138
+ */
139
+
140
+/** Configure I2C as slave or master.
141
+ *  @param obj The I2C object
142
+ *  @return non-zero if a value is available
143
+ */
144
+void i2c_slave_mode(i2c_t *obj, int enable_slave);
145
+
146
+/** Check to see if the I2C slave has been addressed.
147
+ *  @param obj The I2C object
148
+ *  @return The status - 1 - read addresses, 2 - write to all slaves,
149
+ *         3 write addressed, 0 - the slave has not been addressed
150
+ */
151
+int  i2c_slave_receive(i2c_t *obj);
152
+
153
+/** Configure I2C as slave or master.
154
+ *  @param obj The I2C object
155
+ *  @return non-zero if a value is available
156
+ */
157
+int  i2c_slave_read(i2c_t *obj, char *data, int length);
158
+
159
+/** Configure I2C as slave or master.
160
+ *  @param obj The I2C object
161
+ *  @return non-zero if a value is available
162
+ */
163
+int  i2c_slave_write(i2c_t *obj, const char *data, int length);
164
+
165
+/** Configure I2C address.
166
+ *  @param obj     The I2C object
167
+ *  @param idx     Currently not used
168
+ *  @param address The address to be set
169
+ *  @param mask    Currently not used
170
+ */
171
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
172
+
173
+#endif
174
+
175
+/**@}*/
176
+
177
+#if DEVICE_I2C_ASYNCH
178
+
179
+/**
180
+ * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer
181
+ * @{
182
+ */
183
+
184
+/** Start i2c asynchronous transfer.
185
+ *  @param obj       The I2C object
186
+ *  @param tx        The buffer to send
187
+ *  @param tx_length The number of words to transmit
188
+ *  @param rx        The buffer to receive
189
+ *  @param rx_length The number of words to receive
190
+ *  @param address   The address to be set - 7bit or 9 bit
191
+ *  @param stop      If true, stop will be generated after the transfer is done
192
+ *  @param handler   The I2C IRQ handler to be set
193
+ *  @param hint      DMA hint usage
194
+ */
195
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
196
+
197
+/** The asynchronous IRQ handler
198
+ *  @param obj The I2C object which holds the transfer information
199
+ *  @return event flags if a transfer termination condition was met or 0 otherwise.
200
+ */
201
+uint32_t i2c_irq_handler_asynch(i2c_t *obj);
202
+
203
+/** Attempts to determine if I2C peripheral is already in use.
204
+ *  @param obj The I2C object
205
+ *  @return non-zero if the I2C module is active or zero if it is not
206
+ */
207
+uint8_t i2c_active(i2c_t *obj);
208
+
209
+/** Abort ongoing asynchronous transaction.
210
+ *  @param obj The I2C object
211
+ */
212
+void i2c_abort_asynch(i2c_t *obj);
213
+
214
+#endif
215
+
216
+/**@}*/
217
+
218
+#ifdef __cplusplus
219
+}
220
+#endif
221
+
222
+#endif
223
+
224
+#endif

+ 82
- 0
lib/mbed/lp_ticker_api.h View File

@@ -0,0 +1,82 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2015 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_LPTICKER_API_H
17
+#define MBED_LPTICKER_API_H
18
+
19
+#include "device.h"
20
+
21
+#if DEVICE_LOWPOWERTIMER
22
+
23
+#include "ticker_api.h"
24
+
25
+#ifdef __cplusplus
26
+extern "C" {
27
+#endif
28
+
29
+/**
30
+ * \defgroup LpTicker Low Power Ticker Functions
31
+ * @{
32
+ */
33
+
34
+/** Get low power ticker's data
35
+ *
36
+ * @return The low power ticker data
37
+ */
38
+const ticker_data_t* get_lp_ticker_data(void);
39
+
40
+/** The wrapper for ticker_irq_handler, to pass lp ticker's data
41
+ *
42
+ */
43
+void lp_ticker_irq_handler(void);
44
+
45
+/* HAL lp ticker */
46
+
47
+/** Initialize the low power ticker
48
+ *
49
+ */
50
+void lp_ticker_init(void);
51
+
52
+/** Read the current counter
53
+ *
54
+ * @return The current timer's counter value in microseconds
55
+ */
56
+uint32_t lp_ticker_read(void);
57
+
58
+/** Set interrupt for specified timestamp
59
+ *
60
+ * @param timestamp The time in microseconds to be set
61
+ */
62
+void lp_ticker_set_interrupt(timestamp_t timestamp);
63
+
64
+/** Disable low power ticker interrupt
65
+ *
66
+ */
67
+void lp_ticker_disable_interrupt(void);
68
+
69
+/** Clear the low power ticker interrupt
70
+ *
71
+ */
72
+void lp_ticker_clear_interrupt(void);
73
+
74
+/**@}*/
75
+
76
+#ifdef __cplusplus
77
+}
78
+#endif
79
+
80
+#endif
81
+
82
+#endif

+ 70
- 0
lib/mbed/mbed.h View File

@@ -0,0 +1,70 @@
1
+
2
+/* mbed Microcontroller Library
3
+ * Copyright (c) 2006-2013 ARM Limited
4
+ *
5
+ * Licensed under the Apache License, Version 2.0 (the "License");
6
+ * you may not use this file except in compliance with the License.
7
+ * You may obtain a copy of the License at
8
+ *
9
+ *     http://www.apache.org/licenses/LICENSE-2.0
10
+ *
11
+ * Unless required by applicable law or agreed to in writing, software
12
+ * distributed under the License is distributed on an "AS IS" BASIS,
13
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
+ * See the License for the specific language governing permissions and
15
+ * limitations under the License.
16
+ */
17
+#ifndef MBED_H
18
+#define MBED_H
19
+
20
+#define MBED_LIBRARY_VERSION 119
21
+
22
+#include "platform.h"
23
+
24
+// Useful C libraries
25
+#include <math.h>
26
+#include <time.h>
27
+
28
+// mbed Debug libraries
29
+#include "mbed_error.h"
30
+#include "mbed_interface.h"
31
+
32
+// mbed Peripheral components
33
+#include "DigitalIn.h"
34
+#include "DigitalOut.h"
35
+#include "DigitalInOut.h"
36
+#include "BusIn.h"
37
+#include "BusOut.h"
38
+#include "BusInOut.h"
39
+#include "PortIn.h"
40
+#include "PortInOut.h"
41
+#include "PortOut.h"
42
+#include "AnalogIn.h"
43
+#include "AnalogOut.h"
44
+#include "PwmOut.h"
45
+#include "Serial.h"
46
+#include "SPI.h"
47
+#include "SPISlave.h"
48
+#include "I2C.h"
49
+#include "I2CSlave.h"
50
+#include "Ethernet.h"
51
+#include "CAN.h"
52
+#include "RawSerial.h"
53
+
54
+// mbed Internal components
55
+#include "Timer.h"
56
+#include "Ticker.h"
57
+#include "Timeout.h"
58
+#include "LowPowerTimeout.h"
59
+#include "LowPowerTicker.h"
60
+#include "LowPowerTimer.h"
61
+#include "LocalFileSystem.h"
62
+#include "InterruptIn.h"
63
+#include "wait_api.h"
64
+#include "sleep_api.h"
65
+#include "rtc_time.h"
66
+
67
+using namespace mbed;
68
+using namespace std;
69
+
70
+#endif

+ 49
- 0
lib/mbed/mbed_assert.h View File

@@ -0,0 +1,49 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ASSERT_H
17
+#define MBED_ASSERT_H
18
+
19
+#ifdef __cplusplus
20
+extern "C" {
21
+#endif
22
+
23
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
24
+ *  This function is active only if NDEBUG is not defined prior to including this
25
+ *  assert header file.
26
+ *  In case of MBED_ASSERT failing condition, error() is called with the assertation message.
27
+ *  @param expr Expresion to be checked.
28
+ *  @param file File where assertation failed.
29
+ *  @param line Failing assertation line number.
30
+ */
31
+void mbed_assert_internal(const char *expr, const char *file, int line);
32
+
33
+#ifdef __cplusplus
34
+}
35
+#endif
36
+
37
+#ifdef NDEBUG
38
+#define MBED_ASSERT(expr) ((void)0)
39
+
40
+#else
41
+#define MBED_ASSERT(expr)                                \
42
+do {                                                     \
43
+    if (!(expr)) {                                       \
44
+        mbed_assert_internal(#expr, __FILE__, __LINE__); \
45
+    }                                                    \
46
+} while (0)
47
+#endif
48
+
49
+#endif

+ 66
- 0
lib/mbed/mbed_debug.h View File

@@ -0,0 +1,66 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_DEBUG_H
17
+#define MBED_DEBUG_H
18
+#include "device.h"
19
+
20
+#ifdef __cplusplus
21
+extern "C" {
22
+#endif
23
+
24
+#if DEVICE_STDIO_MESSAGES
25
+#include <stdio.h>
26
+#include <stdarg.h>
27
+
28
+/** Output a debug message
29
+ *
30
+ * @param format printf-style format string, followed by variables
31
+ */
32
+static inline void debug(const char *format, ...) {
33
+    va_list args;
34
+    va_start(args, format);
35
+    vfprintf(stderr, format, args);
36
+    va_end(args);
37
+}
38
+
39
+/** Conditionally output a debug message
40
+ *
41
+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization
42
+ * level is greater than 0, then the whole function will be compiled away.
43
+ *
44
+ * @param condition output only if condition is true (== 1)
45
+ * @param format printf-style format string, followed by variables
46
+ */
47
+static inline void debug_if(int condition, const char *format, ...) {
48
+    if (condition == 1) {
49
+        va_list args;
50
+        va_start(args, format);
51
+        vfprintf(stderr, format, args);
52
+        va_end(args);
53
+    }
54
+}
55
+
56
+#else
57
+static inline void debug(const char *format, ...) {}
58
+static inline void debug_if(int condition, const char *format, ...) {}
59
+
60
+#endif
61
+
62
+#ifdef __cplusplus
63
+}
64
+#endif
65
+
66
+#endif

+ 66
- 0
lib/mbed/mbed_error.h View File

@@ -0,0 +1,66 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_ERROR_H
17
+#define MBED_ERROR_H
18
+
19
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
20
+ *
21
+ * @code
22
+ * #error "That shouldn't have happened!"
23
+ * @endcode
24
+ *
25
+ * If the compiler evaluates this line, it will report the error and stop the compile.
26
+ *
27
+ * For example, you could use this to check some user-defined compile-time variables:
28
+ *
29
+ * @code
30
+ * #define NUM_PORTS 7
31
+ * #if (NUM_PORTS > 4)
32
+ *     #error "NUM_PORTS must be less than 4"
33
+ * #endif
34
+ * @endcode
35
+ *
36
+ * Reporting Run-Time Errors:
37
+ * To generate a fatal run-time error, you can use the mbed error() function.
38
+ *
39
+ * @code
40
+ * error("That shouldn't have happened!");
41
+ * @endcode
42
+ *
43
+ * If the mbed running the program executes this function, it will print the
44
+ * message via the USB serial port, and then die with the blue lights of death!
45
+ *
46
+ * The message can use printf-style formatting, so you can report variables in the
47
+ * message too. For example, you could use this to check a run-time condition:
48
+ *
49
+ * @code
50
+ * if(x >= 5) {
51
+ *     error("expected x to be less than 5, but got %d", x);
52
+ * }
53
+ * #endcode
54
+ */
55
+
56
+#ifdef __cplusplus
57
+extern "C" {
58
+#endif
59
+
60
+void error(const char* format, ...);
61
+
62
+#ifdef __cplusplus
63
+}
64
+#endif
65
+
66
+#endif

+ 114
- 0
lib/mbed/mbed_interface.h View File

@@ -0,0 +1,114 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_INTERFACE_H
17
+#define MBED_INTERFACE_H
18
+
19
+#include "device.h"
20
+
21
+/* Mbed interface mac address
22
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
23
+ * otherwise MAC_ADD_x are used.
24
+ */
25
+#define MBED_MAC_ADDR_INTERFACE 0x00
26
+#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE
27
+#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE
28
+#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE
29
+#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE
30
+#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE
31
+#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE
32
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
33
+
34
+#ifdef __cplusplus
35
+extern "C" {
36
+#endif
37
+
38
+#if DEVICE_SEMIHOST
39
+
40
+/** Functions to control the mbed interface
41
+ *
42
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
43
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
44
+ * system. These functions provide means to control the interface suing semihost
45
+ * calls it supports.
46
+ */
47
+
48
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
49
+ *
50
+ *  @returns
51
+ *    1 if interface is connected,
52
+ *    0 otherwise
53
+ */
54
+int mbed_interface_connected(void);
55
+
56
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
57
+ *
58
+ *  @returns
59
+ *    1 if successful,
60
+ *    0 otherwise (e.g. interface not present)
61
+ */
62
+int mbed_interface_reset(void);
63
+
64
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
65
+ * The interface will still support the USB serial aspect
66
+ *
67
+ *  @returns
68
+ *    0 if successful,
69
+ *   -1 otherwise (e.g. interface not present)
70
+ */
71
+int mbed_interface_disconnect(void);
72
+
73
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
74
+ * connected, also power down the interface. If the USB cable is connected, the interface
75
+ * will remain powered up and visible to the host
76
+ *
77
+ *  @returns
78
+ *    0 if successful,
79
+ *   -1 otherwise (e.g. interface not present)
80
+ */
81
+int mbed_interface_powerdown(void);
82
+
83
+/** This returns a string containing the 32-character UID of the mbed interface
84
+ *  This is a weak function that can be overwritten if required
85
+ *
86
+ *  @param uid A 33-byte array to write the null terminated 32-byte string
87
+ *
88
+ *  @returns
89
+ *    0 if successful,
90
+ *   -1 otherwise (e.g. interface not present)
91
+ */
92
+int mbed_interface_uid(char *uid);
93
+
94
+#endif
95
+
96
+/** This returns a unique 6-byte MAC address, based on the interface UID
97
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
98
+ *
99
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
100
+ * provide a MAC address.
101
+ *
102
+ *  @param mac A 6-byte array to write the MAC address
103
+ */
104
+void mbed_mac_address(char *mac);
105
+
106
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
107
+ */
108
+void mbed_die(void);
109
+
110
+#ifdef __cplusplus
111
+}
112
+#endif
113
+
114
+#endif

+ 45
- 0
lib/mbed/pinmap.h View File

@@ -0,0 +1,45 @@
1
+/* mbed Microcontroller Library
2
+ * Copyright (c) 2006-2013 ARM Limited
3
+ *
4
+ * Licensed under the Apache License, Version 2.0 (the "License");
5
+ * you may not use this file except in compliance with the License.
6
+ * You may obtain a copy of the License at
7
+ *
8
+ *     http://www.apache.org/licenses/LICENSE-2.0
9
+ *
10
+ * Unless required by applicable law or agreed to in writing, software
11
+ * distributed under the License is distributed on an "AS IS" BASIS,
12
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13
+ * See the License for the specific language governing permissions and
14
+ * limitations under the License.
15
+ */
16
+#ifndef MBED_PINMAP_H
17
+#define MBED_PINMAP_H
18
+
19
+#include "PinNames.h"
20
+
21
+#ifdef __cplusplus
22
+extern "C" {
23
+#endif
24
+
25
+typedef struct {
26
+    PinName pin;
27
+    int peripheral;
28
+    int function;
29
+} PinMap;
30
+
31
+void pin_function(PinName pin, int function);
32
+void pin_mode    (PinName pin, PinMode mode);
33
+
34
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
35
+uint32_t pinmap_function(PinName pin, const PinMap* map);
36
+uint32_t pinmap_merge     (uint32_t a, uint32_t b);
37
+void     pinmap_pinout    (PinName pin, const PinMap *map);
38
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
39
+uint32_t pinmap_find_function(PinName pin, const PinMap* map);
40
+
41
+#ifdef __cplusplus
42
+}
43
+#endif
44
+
45
+#endif

+ 0
- 0
lib/mbed/platform.h View File


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