- Also implemented real endstop reading on interrupt.

Disabling an ISR on ARM has 3 instructions of latency. A Memory barrier is REQUIRED to ensure proper and predictable disabling. Memory barriers are expensive, so avoid disabling if already disabled (See https://mcuoneclipse.com/2015/10/16/nvic-disabling-interrupts-on-arm-cortex-m-and-the-need-for-a-memory-barrier-instruction/)

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

Use macros that explicitly avoid double-evaluation and can be used for any datatype, replacing `min`, `max`, `abs`, `fabs`, `labs`, and `FABS`.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

- Cleanups, fixes for Due HAL code.
- TC_IER is write-only. Use TC_IMR to test ISR state.

Co-Authored-By: ejtagle <ejtagle@hotmail.com>

* AVR: Atomic bit set and clear

The critical section can be dropped, saving 3 cycles per access. Also simplified pin toggling for all ports.

Also simplify logic on all ARM-based interrupts. Now, it is REQUIRED to properly configure interrupt priority. USART should have highest priority, followed by Stepper, and then all others.

- And implement the `backtrace()` function call

- Watchdog reset during SD Card initialization.
- Move `DebugMonitor` to `DebugMonitor_Due.cpp`.
- Since the watchdog is enabled on boot do extra resets during init.
- Have `thermalManager` do watchdog reset before its ISR starts to prevent reset.
- Ensure that timers are stopped before reprogramming them to address tone issues.
- Improve SAM3XE reset when reflashed through the native port.

@Bob-the-Kuhn — Please set your git options to remove trailing whitespace on commit.

added device & comm drivers for shared SPI LCDs

mistyped some updates in ultralcd_impl_DOGM.h

remove unwanted changes in onfiguration.h

still can't type

Update HAL_LCD_class_defines.h

include USB mass storage & misc

Followup to #9985